1 השעון Hertz=1/sec מחשב פנטיום במהירות של פירושו שהוא מבצע...

השעון

Hertz=1/sec

מחשב פנטיום במהירות של

. מחזורי שעון בשניה2 *10^8פירושו שהוא מבצע

כל מחזור שעון לוקח

200MHZ

5*10^-9=5nanosecond

?כמה לוקחת פקודה בימינו

Gotta Do Laundry° Ann, Brian, Cathy, Dave

each have one load of clothes to wash, dry, fold, and put away

A B C D

° Dryer takes 30 minutes

° “Folder” takes 30 minutes

° “Stasher” takes 30 minutes to put clothes into drawers

° Washer takes 30 minutes

Sequential Laundry

• Sequential laundry takes 8 hours for 4 loads

30Time

3030 3030 30 3030 3030 3030 3030 3030

6 PM 7 8 9 10 11 12 1 2 AM

Pipelined Laundry

• Pipelined laundry takes 3.5 hours for 4 loads!

12 2 AM6 PM 7 8 9 10 11 1

Time303030 3030 3030

General Definitions

• Latency: time to completely execute a certain task– for example, time to read a sector from disk is

disk access time or disk latency

• Throughput: amount of work that can be done over a period of time

Pipelining Lessons (1/2)

• Pipelining doesn’t help latency of single task, it helps throughput of entire workload

• Multiple tasks operating simultaneously using different resources

• Potential speedup = Number pipe stages

• Time to “fill” pipeline and time to “drain” it reduces speedup:2.3X v. 4X in this example

6 PM 7 8 9

303030 3030 3030Task

Pipelining Lessons (2/2)

• Suppose new Washer takes 20 minutes, new Stasher takes 20 minutes. How much faster is pipeline?

• Pipeline rate limited by slowest pipeline stage

• Unbalanced lengths of pipe stages also reduces speedup

6 PM 7 8 9

303030 3030 3030Task

Steps in Executing MIPS

1) IFetch: Fetch Instruction, Increment PC2) Decode Instruction, Read Registers3) Execute: Mem-ref: Calculate Address Arith-log: Perform Operation

4) Memory: Load: Read Data from Memory Store: Write Data to Memory

5) Write Back: Write Data to Register

Pipelined Execution Representation

• Every instruction must take same number of steps, also called pipeline “stages”, so some will go idle sometimes

IFtch Dcd Exec Mem WB

Review: Datapath for MIPS

Stage 1 Stage 2 Stage 3Stage 4 Stage 5

• Use datapath figure to represent pipelineIFtch Dcd Exec Mem WB

U I$ Reg D$ Reg

1. InstructionFetch

2. Decode/ Register Read

3. Execute 4. Memory5. Write

Graphical Pipeline Representation

Instr.

Time (clock cycles)

Reg Reg

(In Reg, right half highlight read, left half write)

Example• Suppose 2 ns for memory access, 2 ns for ALU operation, and 1 ns for register file read or write

• Nonpipelined Execution:–lw : IF + Read Reg + ALU + Memory + Write Reg

= 2 + 1 + 2 + 2 + 1 = 8 ns–add: IF + Read Reg + ALU + Write Reg

= 2 + 1 + 2 + 1 = 6 ns

• Pipelined Execution:–Max(IF,Read Reg,ALU,Memory,Write Reg) = 2

PIPELINE הרעיון מאחורי

Instructionfetch

Reg ALUData

accessReg

8 nsInstruction

fetchReg ALU

Dataaccess

8 nsInstruction

lw $1, 100($0)

lw $2, 200($0)

lw $3, 300($0)

2 4 6 8 10 12 14 16 18

2 4 6 8 10 12 14

Programexecutionorder(in instructions)

Instructionfetch

Reg ALUData

accessReg

lw $1, 100($0)

lw $2, 200($0)

lw $3, 300($0)

2 nsInstruction

fetchReg ALU

Dataaccess

2 nsInstruction

fetchReg ALU

Dataaccess

2 ns 2 ns 2 ns 2 ns 2 ns

Never waste time !!!

חלוקה לשלבים

Instructionmemory

Address

Add Addresult

Shiftleft 2

Instruction

0Writedata

1Registers

Readdata 1

Readdata 2

Readregister 1

Readregister 2

16Sign

extend

Writeregister

Writedata

ReaddataAddress

Datamemory

ALUresult

ALUZero

IF: Instruction fetch ID: Instruction decode/register file read

EX: Execute/address calculation

MEM: Memory access WB: Write back

הוספת הרגיסטרים

Instructionmemory

Address

Add Addresult

Shiftleft 2

IF/ID EX/MEM MEM/WB

0Writedata

1Registers

Readdata 1

Readdata 2

Readregister 1

Readregister 2

16Sign

extend

Writeregister

Writedata

Readdata

ALUresult

ALUZero

Datamemory

Address

In struc t ion

m e m o ry

Add re ss

A ddA d d

re s u lt

S h if t

le f t 2

IF /I D E X / M E M M E M /W B

0W ri teda ta

R eg iste rs

R e a dd a ta 1

R e a dd a ta 2

R e a dre g is te r 1

16S ig n

e xte nd

W ritere g is te r

W rited ata

R ea dda ta

A LUre s u lt

Z e ro

ID /E X

In s tr u c t io n fe tc h

In struc t ion

m e m o ry

A dd re ss

A ddA dd

res u lt

S h if t

le ft 2

IF / I D E X / M E M

0W r iteda ta

R eg iste rs

R e a dda ta 1

R e a dda ta 2

16S i gn

e xte nd

W r itere g is te r

W rited ata

R ea dda ta

A LUre s u lt

ID /E X M E M /W B

I n s t r u c t io n d e c o d e

A d d re s s

m e m o ry

Instructionmemory

Address

Add Addresult

Shiftleft 2

IF/ID EX/MEM

0Writedata

1Registers

Readdata 1

Readdata 2

Readregister 1

Readregister 2

16Sign

extend

Writeregister

Writedata

Readdata

ALUresult

ALUZero

ID/EX MEM/WB

Execution

Address

Datamemory

EX/MEM

In s tru c t ion

m e m or y

A dd res s

A d dA dd

r e su lt

S h if t

le ft 2

I F /ID E X/M E M

0W rit ed a ta

R e g is te rs

R ea dd ata 1

R ea dd ata 2

R e adre g is ter 1

R e adre g is ter 2

16S ig n

e xte nd

W ritere g is ter

W riteda ta

R e add at a

D a ta

m em o ry

A L Ures u lt

Z er o

ID /E X M E M /W B

M e m o r y

A d dre ss

MEM/WB

In stru ct ion

m em ory

A dd res s

Ad dA dd

r esu lt

S h ift

l e ft 2

I F /ID E X /M E M

0W rit ed a ta

R eg iste rs

R e add ata 1

R e add ata 2

R e a dre g is ter 1

R e a dre g is ter 2

16S ig n

e xte nd

W rited a ta

R e a ddat aD a ta

m e m o ry

A LUre s u lt

ID /EX M E M /W B

W r it e b a c k

W ritere g is te r

A d dre s s

A correction !!! תיקון

Keep the right Rd all the way!

Instructionmemory

Address

Add Addresult

Shiftleft 2

IF/ID EX/MEM MEM/WB

Address

Writedata

1Registers

Readdata 1

Readdata 2

Readregister 1

Readregister 2

16Sign

extend

Writeregister

Writedata

Readdata

Datamemory

ALUresult

ALUZero

Instructionmemory

Address

Add Addresult

Shiftleft 2

IF/ID EX/MEM MEM/WB

0Writedata

1Registers

Readdata 1

Readdata 2

Readregister 1

Readregister 2

16Sign

extend

Writeregister

Writedata

Readdata

ALUresult

ALUZero

Address

Datamemory

So here is the updated CPU;

תצוגה גרפית

IM Reg DM Reg

CC 1 CC 2 CC 3 CC 4 CC 5 CC 6

Time (in clock cycles)

lw $10, 20($1)

sub $11, $2, $3

Control

Instructionmemory

Address

Instruction[20– 16]

MemtoReg

Branch

RegDst

ALUSrc

16 32Instruction[15– 0]

0Registers

Writeregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

1Write

data Mux

ALUcontrol

RegWrite

MemRead

IF/ID ID/EX EX/MEM MEM/WB

MemWrite

Address

Datamemory

AddAdd

result

Shiftleft 2

ALUresult

קווי הבקרהExecution/Address Calculation

stage control linesMemory access stage

control lines

Write-back stage control

InstructionReg Dst

ALU Op1

ALU Op0

ALU Src Branch

Mem Read

Mem Write

Reg write

Mem to Reg

R-format 1 1 0 0 0 0 0 1 0lw 0 0 0 1 0 1 0 1 1sw X 0 0 1 0 0 1 0 Xbeq X 0 1 0 1 0 0 0 X

Control

IF/ID ID/EX EX/MEM MEM/WB

Instruction

Instructionmemory

Branch

RegDst

ALUSrc

Add Addresult

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

ALUresult

Writedata

Readdata

ALUcontrol

Shiftleft 2

MemRead

Control

WBIF/ID

EX/MEM

MEM/WB

AddressData

memory

Address

Datapath with Control

דוגמאA demonstration of a sequence of instructions:

Lw $10,20($1)

Sub $11,$2,$3

And $12,$4,$5

Or $13,$6,$7

Add $14,$8,$9

Instructionmemory

Branch

RegDst

ALUSrc

Add Addresult

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

ALUresult

ALUcontrol

Shiftleft 2

MemRead

Control

IF/ID EX/MEMID/EX

ID: before<1> EX: before<2> MEM: before<3> WB: before<4>

MEM/WB

IF: lw $10, 20($1)

Datamemory

Address

Writedata

Readdata

Instructionmemory

Branch

RegDst

ALUSrc

Add Addresult

Writeregister

Writedata

ALUresult

ALUcontrol

Shiftleft 2

IF/ID EX/MEMID/EX

ID: lw $10, 20($1) EX: before<1> MEM: before<2> WB: before<3>

MEM/WB

IF: sub $11, $2, $3

0Writedata

Readdata

lwControl

Registers

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Instruction[15– 0] Sign

extend

MemReadM

Datamemory

Address

Clock 2

Clock 1

Instructionmemory

Address

Branch

ALUSrc

Add Addresult

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

ALUresult

Shiftleft 2

MemRead

Control

IF/ID EX/MEMID/EX

ID: sub $11, $2, $3 EX: lw $10, . . . MEM: before<1> WB: before<2>

MEM/WB

IF: and $12, $4, $5

0Writedata

Readdata

Instructionmemory

Address

Branch

RegDst

ALUSrc

Add Addresult

Writeregister

Writedata 1

ALUresult

ALUcontrol

Shiftleft 2

IF/ID EX/MEMID/EX

ID: and $12, $2, $3 EX: sub $11, . . . MEM: lw $10, . . . WB: before<1>

MEM/WB

IF: or $13, $6, $7

0Writedata

andControl

Registers

Readdata 1

Readdata 2

Readregister 1

Readregister 2

MemReadM

RegDst

ALUcontrol

ALUAddress Read

dataData

memory

Signextend

Datamemory

Address

Clock 3

Clock 4

ID: and $12, $4, $5

Instructionmemory

Address

Branch

ALUSrc

Add Addresult

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

ALUresult

Shiftleft 2

MemRead

Control

IF/ID EX/MEMID/EX

ID: or $13, $6, $7 EX: and $12, . . . MEM: sub $11, . . . WB: lw $10, . . .

MEM/WB

IF: add $14, $8, $9

0Writedata

Readdata

Instructionmemory

Address

Branch

RegDst

ALUSrc

Add Addresult

ALUresult

ALUcontrol

Shiftleft 2

IF/ID EX/MEMID/EX

ID: add $14, $8, $9 EX: or $13, . . . MEM: and $12, . . . WB: sub $11, . . .

MEM/WB

IF: after<1>

0Writedata

addControl

Registers

Readdata 1

Readdata 2

Readregister 1

Readregister 2

MemReadM

RegDst

ALUcontrol

ALUReaddata

Writeregister

Writedata

Datamemory

Address

Datamemory

Address

Signextend

Clock 5

Clock 6

Instructionmemory

Address

Branch

ALUSrc

Add Addresult

Writedata

ALUresult

Shiftleft 2

MemRead

Control

Signextend

IF/ID EX/MEMID/EX

ID: after<1> EX: add $14, . . . MEM: or $13, . . . WB: and $12, . . .

MEM/WB

IF: after<2>

0Writedata

Readdata

Instructionmemory

Address

Branch

RegDst

ALUSrc

Add Addresult

ALUresult

ALUcontrol

Shiftleft 2

IF/ID EX/MEMID/EX

ID: after<2> EX: after<1> MEM: add $14, . . . WB: or $13, . . .

MEM/WB

IF: after<3>

0Writedata

Control

Registers

Readdata 1

Readdata 2

Readregister 1

Readregister 2

extend

MemReadM

RegDst

ALUcontrol

ALUReaddata

Writeregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2 Zero

Datamemory

Address

Datamemory

Address

Clock 7

Clock 8

Instructionmemory

Address

Branch

RegDst

ALUSrc

Add Addresult

ALUresult

ALUcontrol

Shiftleft 2R

IF/ID EX/MEMID/EX

ID: after<3> EX: after<2> MEM: after<1> WB: add $14, . . .

MEM/ WB

IF: after<4>

0Writedata

Control

Registers

Readdata 1

Readdata 2

Readregister 1

Readregister 2

extend

Instru ction[15– 11]

MemRead

ALUReaddata

Writeregister

Writedata

Datamemory

Address

Clock 9

Pipeline Hazard: Matching socks in later load

A depends on D; stall since folder tied up

bubble

12 2 AM6 PM 7 8 9 10 11 1

Time303030 3030 3030

Problems for Computers• Limits to pipelining: Hazards prevent next

instruction from executing during its designated clock cycle– Structural hazards: HW cannot support this combination

of instructions (single person to fold and put clothes away)

– Control hazards: Pipelining of branches & other instructions stall the pipeline until the hazard “bubbles” in the pipeline

– Data hazards: Instruction depends on result of prior instruction still in the pipeline (missing sock)

An example for data hazards:

sub $2, $1, $3

and $12, $2, $5

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)

An example for data hazards:

sub $2, $1, $3

and $12, $2, $5

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)

An example for data hazards:Register $2 is updated only at the WB phase, i.e., the 5th clock cycle (actually at the end of the 5th clock cycle). However, we try to use it at the 3rd clock cycle when we read $2 at the decode phase of the and instruction

Graphic representation of data hazards:

IM Reg

sub $2, $1, $3

and $12, $2, $5

IM Reg DM Reg

IM DM Reg

CC 7 CC 8 CC 9

10 10 10 10 10/– 20 – 20 – 20 – 20 – 20

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)

Value of register $2:

DM Reg

sub $2, $1, $3

and $12, $2, $5

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)

Solving data hazards by adding nops

and $12, $2, $

or $13, $6, $ 2

add $14, $2, $

sw $15, 100( $2

IM Reg

IM Reg DM Reg

IM DM Reg

IM DM Re

IM Reg DMReg

IM Reg DM Reg

IM Reg DMReg

sub $2, $1, $ 3

CC 7 CC 8 CC 9

10 10 10 10 10/– 20 – 20 – 20 – 20 – 20

CC 10 CC 11 CC 12

– 20 – 20 – 20

Graphic representation of data hazards:

IM Reg

sub $2, $1, $3

and $12, $2, $5

IM Reg DM Reg

IM DM Reg

CC 7 CC 8 CC 9

10 10 10 10 10/– 20 – 20 – 20 – 20 – 20

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)

DM Reg

Forwarding – גניבת הערכים

IM Reg

sub $2, $1, $3

Programexecution order(in instructions)

and $12, $2, $5

IM Reg DM Reg

IM DM Reg

CC 7 CC 8 CC 9

10 10 10 10 10/– 20 – 20 – 20 – 20 – 20

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)

Value of register $2 :

DM Reg

X X X – 20 X X X X XValue of EX/MEM :X X X X – 20 X X X XValue of MEM/WB :

Forwarding (done at the execute phase)

PCInstruction

memory

Registers

Control

EX/MEM

MEM/WB

Datamemory

Forwardingunit

RdEX/MEM.RegisterRd

MEM/WB.RegisterRd

IF/ID.RegisterRd

IF/ID.RegisterRt

IF/ID.RegisterRs

If ID/EX.Rs=EX/MEM.Rd, i.e., the Rd of the previous instruction equals the Rs of the current instruction (which is in the “decode” phase), then we use the “ALUout” of the previous instruction

instead of the output of the GPR. If ID/EX.Rs=MEM/WB.Rd, i.e., the Rd of the previous instruction equals the Rs of the current instruction (which is in the “decode” phase), then we use the “ALUout” of the previous instruction instead of the output of the GPR. [ similarly, compare also ID/EX.Rt to MEM/WB.Rd ]

Similarly, compare also ID/EX.Rt to EX/MEM.Rd and to MEM/WB.Rd

Data hazard from previous instruction:

ALU Src A:

If (ID/EX.Rs = = EX/MEM.Rd) use the “ALUOut” instead of Rs

I.e., if Rs of the current executing instruction = = Rd of the previous instruction

The actual equations are:

if ((EX/MEM.RegWrite = = ‘1”)&& (EX/MEM.Rd <> 0)&& (ID/EX.Rs = = EX/MEM.Rd)) => ForwardA=“1,0”

ALU Src B:

If (ID/EX.Rt = = EX/MEM.Rd) use the “ALUOut” instead of Rt

I.e., if Rt of the current executing instruction = = Rd of the previous instruction

if ((EX/MEM.RegWrite = = ‘1”)&& (EX/MEM.Rd <> 0)&& (ID/EX.Rt = = EX/MEM.Rd)) => ForwardB=“1,0”

Data hazard from 2 instructions back:ALU Src A:

If (ID/EX.Rs = = MEM/WB.Rd) use the GPR “write data” instead of Rs

I.e., if Rs of the current executing instruction = = Rd of 2 instructions ago

if ((MEM/WB.RegWrite = = ‘1”)&& (MEM/WB.Rd <> 0)&& (ID/EX.Rs = = MEM/WB.Rd)) => ForwardA=“0,1”

ALU Src B:

If (ID/EX.Rt = = MEM/WB.Rd) use the GPR “write data” instead of Rt

I.e., if Rt of the current executing instruction = = Rd of 2 instructions ago

if ((MEM/WB.RegWrite = = ‘1”)&& (MEM/WB.Rd <> 0)&& (ID/EX.Rt = = MEM/WB.Rd)) => ForwardB=“0,1”

Double hazard: If there is a hazard from previous inst and the instruction before that?We should chhose the data from the previous instruction, it is up to date (“newer”)!

An example for forwarding דוגמא

Sub $2, $1, $3

And $4, $2, $5 needs forwarding from the previous instruction

Or $4, $4, $2 needs forwarding from two instructions back

Add $9, $4, $2 needs forwarding from 3 instructions back (thru the “transparent” GPR)

Here we discuss the $2 register only

(The first two cases are handled in the execute phase, the last one, in the decode phase).

An example for forwarding דוגמא

Sub $2, $1, $3

And $4, $2, $5

Or $4, $4, $2 needs forwarding from the previous instruction

Add $9, $4, $2 needs forwarding from the previous instruction

Here we discuss the $4 register and there are two case (the 2nd one in purple)

PCInstruction

memory

Registers

Datamemory

Forwardingunit

and $4, $2, $5 sub $2, $1, $3

before<1>

EX/MEM

before<2>

MEM/WB

or $4, $4, $2

Clock 3

Control

PCInstruction

memory

Registers

Datamemory

Forwardingunit

or $4, $4, $2 and $4, $2, $5

sub $2, . . .

EX/MEM

before<1>

MEM/WB

add $9, $4, $2

Clock 4

Control

Since Rs=2 and Rd of previous inst. was 2, we use ALUout instead of Rs

PCInstruction

memory

Registers

Datamemory

Forwardingunit

add $9, $4, $2 or $4, $4, $2

and $4, . . .

EX/MEM

sub $2, . . .

MEM/WB

after<1>

Clock 5

Control

PCInstruction

memory

Datamemory

Forwardingunit

after<1>after<2> add $9, $4, $2 or $4, . . .

EX/MEM

and $4, . . .

MEM/WB

Clock 6

Registers

Control

In red we see forwarding from two instructions back (Mem->Exec.), in purple, from previous instruction (WB->Exec.), in blue, from 3 instructions back (WB->Decode).

The solution does not work for lw - לא תמיד הפתרון עובד(in lw we do not have the data in the pipe!, it comes from the data memory!)

lw $2, 20($1)

and $4, $2, $5

IM Reg DM Reg

IM DM Reg

CC 7 CC 8 CC 9

or $8, $2, $6

add $9, $4, $2

slt $1, $6, $7

DM Reg

If the previous instruction was lw to a register and we try to use the register in the current instruction, we have a problem, since we cannot go back in time!

One solution is to avoid such cases by adding a nop (by the Assembler) whenever Rt of the lw is equal to Rs or Rt of the following instruction.

Another h/w solution is to add Bubbles,i.e., add nop by hardware

lw $2, 20($1)

and $4, $2, $5

or $8, $2, $6

add $9, $4, $2

slt $1, $6, $7

CC 1 CC 2 CC 3 CC 4 CC 5 CC 6Time (in clock cycles)

IM Reg DM RegIM

IM DM Reg

CC 7 CC 8 CC 9 CC 10

DM Reg

RegReg

bubble

“nop”

We need to hold IF/ID for one ck cycle and insert a “nop: into ID/EX. This is equal to adding a nop instruction by the Assembler.

Hazard detection unit

PCInstruction

memory

Registers

Control

EX/MEM

MEM/WB

Datamemory

Hazarddetection

Forwardingunit

ID/EX.MemRead

ID/EX.RegisterRt

IF/ID.RegisterRd

IF/ID.RegisterRt

IF/ID.RegisterRs

Rt EX/MEM.RegisterRd

MEM/WB.RegisterRd

We need to hold the IF/ID and PC for one ck cycle and insert a “nop: into ID/EX. This is equal to adding a nop instruction by the Assembler.

If (ID/EX.MemRd)&& ( (ID/EX.Rt= =IF/ID.Rs) || (ID/EX.Rt= =IF/ID.Rt) ) we must “stall” the pipeline! This means that prev. inst was lw and it was to the current Rs or Rt. (of course if one of them is not used, don’t stall)

Holding means”freeze” the IF/ID and the PC for 1 clock cycle

Hold the IF/ID by not giving a IF/IDWrire signal and do not increment the PC (which already points at the nex instruction) by not giving the PCWrite signal. Inserting a nop is by clearing all control signals.

Rt from prev. inst.

Rs, Rt of current inst.

identifies lw

An example for lw hazard detection דוגמא

lw $2, 20($1)

And $4, $2, $5

Or $4, $4, $2

Add $9, $4, $2

Hazarddetection

ID/EX.RegisterRt

lw $2, 20($1)

PCInstruction

memory

Registers

Datamemory

Forwardingunit

and $4, $2, $5

before<1>

EX/MEM

before<2>

MEM/WB

or $4, $4, $2

Clock 3

500 11

Control

Hazarddetection

ID/EX.RegisterRt

ID/EX.MemRead

before<3>

PCInstruction

memory

Registers

Datamemory

Forwardingunit

EX/MEM

MEM/WB

and $4, $2, $5 lw $2, 20($1) before<1> before<2>

Clock 2

Control

Hazarddetection

ID/EX.RegisterRt

Hazarddetection

ID/EX.RegisterRt

PCInstruction

memory

Registers

Datamemory

and $4, $2, $5 bubble

lw $2, . . .

EX/MEM

before<1>

MEM/WB

Clock 4

Control

bubble lw $2, . . .

PCInstruction

memory

Registers

Datamemory

Forwardingunit

and $4, $2, $5

EX/MEM

MEM/WB

add $9, $4, $2

Clock 5

210 10

Control

ID/EX.MemRead

or $4, $4, $2

The lw instruction is in the WB phase. $2 is “being written”. We can use $2 in the Execute phase of the and instruction, with the help of forwarding.

Registers

Control

PCInstruction

memory

PCInstruction

memory

Hazarddetection

ID/EX.RegisterRt

bubble

Registers

Datamemory

add $9, $4, $2

and $4, . . .

EX/MEM

MEM/WB

Clock 6

210 10

Control

add $9, $4, $2 or $4, . . . and $4, . . .after<2> after<1>

after<1>

Clock 7

Datamemory

Forwardingunit

EX/MEM

MEM/WB

Hazarddetection

ID/EX.RegisterRt

or $4, $4, $2

ID/EX.MemRead

Instructionmemory

Branch

RegDst

ALUSrc

Add Addresult

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

ALUresult

Writedata

Readdata

ALUcontrol

Shiftleft 2

MemRead

Control

WBIF/ID

EX/MEM

MEM/WB

AddressData

memory

Address

Just to remind us how branch is handled we show again the Datapath with Control

Branch Hazards

40 beq $1, $3, 7

IM Reg

DM Reg

Reg Reg

44 and $12, $2, $5

48 or $13, $6, $2

52 add $14, $2, $2

72 lw $4, 50($7)

CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9

Here we calc.Rs-Rt

Here we decide to branch (switching the address to the PC and issuing PCWrite Cond)

These 3 instructions should be “killed” before they do harm, I.e., change any register.

In cc5 we already use the new PC calculated by the branch. (PC=72)

Instructionmemory

Branch

RegDst

ALUSrc

Add Addresult

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

ALUresult

Writedata

Readdata

ALUcontrol

Shiftleft 2

MemRead

Control

WBIF/ID

EX/MEM

MEM/WB

AddressData

memory

Address

The situation was better if we some how “moved” the branch address calculation one ck earlier. This is easy to dosince sign extension and shift are only wires. We just need to move the branch address ALU 1 register to the left. Rverything happens 1 ck earlier and so we’ll have to “kill” only two instructions.

Next, we’ll add a fast comparator which will compare Rs and Rt at the same ck cycle of the “decode” phase. (Instead of using the ALU to calc. Rs-Rt, we’ll built a simple and fast xor circuit). This means extra h/w but now we earned one more ck cycle. So, we have to kill only a single instruction.

Killing an instruction also called “flushing” the pipeline, is easily done by clraing the IF/ID register of the instruction following the branch (if the branch is successful)

Flushing

PCInstruction

memory

Registers

EX/MEM

MEM/WB

Datamemory

Hazarddetection

Forwardingunit

IF.Flush

Signextend

Control

Shiftleft 2

An example for flushing דוגמא

sub $10, $4, $8

beq $1, $3, 7

and $12, $2, $5

lw $4, 50($7)

PCInstruction

memory

Registers

Signextend

Control

Hazarddetection

Forwardingunit

IF.Flush

and $12, $2, $5 beq $1, $3, 7 sub $10, $4, $8

MEM/WB

EX/MEM

Clock 3

ALUData

memory

bubble (nop)lw $4, 50($7)

Clock 4

Shiftleft 2

before<1>

beq $1, $3, 7 sub $10, . . . before<1>

before<2>

PC Instructionmemory

Registers

Signextend

Control

Hazarddetection

Forwardingunit

IF.Flush

MEM/WB

EX/MEM

ALUData

memory

Shiftleft 2

sub $10, $4, $8

beq $1, $3, 7

and $12, $2, $5

lw $4, 50($7)

Summary of hazardsData hazards:

* Forward from previous instruction

* Forward from two instructions ago

* (Forward thru “transparent”GPR = from 3 instructions ago)

* If we cannot forward, (after lw) we stall the pipe by inserting a nop and freezing IF/ID and PC for 1 ck cycle

Control hazards:

* If branch is successful we flush the instruction following the branch (which is at the IF/ID register. We

just clear the register)

Notes:

In the real MIPS CPU, no flush was employed. This give the compiler the opportunity to put useful instructions following the branch. This explains why the simulator always performs the instruction following the branch.this is called a delayed branch.

Also, in the real MIPS CPU no lw stall was used. Again this give some freedom to the compiler to

choose whether to put a nop following lw or some useful instruction. This is called a delayed load.

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