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Microcontroller & ApplicationsWeek 2Week 2

Instructor:

Syed Ashad Mustufa Younus HP: +92 (0) 300 240 8943Email: sashad@iqra.edu.pk: s s d@ q .ed .p

Digital SystemDigital System

Logic FamiliesLogic Families

TTL CMOS BIMOS ECL DTLTTL CMOS BIMOS ECL DTL

Logic LevelsLogic Levels

Bipolar– 74 - the "standard TTL" logic family had no letters

between the "74" and the specific part number.

74L L ( d h i i l TTL l i– 74L - Low power (compared to the original TTL logic family), very slow

– H - High speed (still produced but generally superseded g p ( p g y pby the S-series, used in 1970s era computers)

– S - Schottky (obsolete)

– LS - Low Power Schottky

– AS - Advanced Schottky

ALS Ad d L P S h k– ALS - Advanced Low Power Schottky

– F - Fast (faster than normal Schottky, similar to AS)

CMOSCMOS– C - CMOS 4–15 V operation similar to buffered 4000 (4000B) series

– HC - High speed CMOS, similar performance to LS, 12 nS

– HCT - High speed, compatible logic levels to bipolar parts

– AC - Advanced CMOS, performance generally between S and F

– AHC - Advanced High-Speed CMOS, three times as fast as HC

– ALVC - Low voltage - 1.65 to 3.3 V, Time Propagation Delay (TPD) 2 nS[7]

– AUC - Low voltage - 0.8 to 2.7 V, TPD < 1.9 nS@1.8 V[7]

– FC - Fast CMOS, performance similar to F

– LCX - CMOS with 3 V supply and 5 V tolerant inputs

– LVC - Low voltage – 1.65 to 3.3 V and 5 V tolerant inputs, tpd < 5.5 nS@3.3 V, tpd < 9 nS@2.5 V[7]

– LVQ - Low voltage - 3.3 V

– LVX - Low voltage - 3.3 V with 5 V tolerant inputs

– VHC - Very High Speed CMOS - 'S' performance in CMOS technology and power

BIMOSBIMOS

– BCT - BiCMOS, TTL-compatible input thresholds, used for buffers

ABT Ad d BiCMOS TTL ibl– ABT - Advanced BiCMOS, TTL-compatible input thresholds, faster than ACT and BCT

Digital Devices

Sequential Devices

Microprocessors

Combinational Devices

Microcontrollers

SPLD CPLD FPGA

PLCs PLA

GAL MPLD Pasic

Programmable Logic DevicesProgrammable Logic Devices

Short for programmable logic device, a generic term for an integrated circuit that can be programmed in a laboratory to perform complex functions. A PLD consists of arrays p g p pof AND and OR gates. A system designer implements a logic design with a device programmer that blows fuses on the PLD to control gate operation.

System designers can use development software that converts basic code into instructions d i d i l d ia device programmer needs to implement a design.

PLD types can classified into the following groups � PROMs (Programmable Read Only Memory) - offer high speed and low cost for

relatively small designsrelatively small designs � PLAs (Programmable Logic Array) - offer flexible features for more complex

designs � PAL/GALs (Programmable Array Logic/Generic Array Logic) - offer good� PAL/GALs (Programmable Array Logic/Generic Array Logic) offer good

flexibility and are faster and less expensive than PLAs

PLD – PLA ArchitecturePLD PLA Architecture

PLD – PAL ArchitecturePLD PAL Architecture

PLD – CPLD ArchitecturePLD CPLD Architecture

• A complex programmable logic device (CPLD) contains many SPLD-like

(PAL lik ) d i i t t d i bl it h t i Th(PAL-like) devices interconnected via a programmable switch matrix. The

SPLD-like devices were called logic-blocks, which contain many SPLD-like

macrocells. Some PLD-vendors developed their own logic-block or switch-p g

matrix architecture and gave them vendor-specific names.

• CPLD (Complex Programmable Logic Device)

• EPLD (Electrical Programmable Logic Device)

• EEPLD (Electrically-Erasable Programmable Logic Device)

• SPLD (Segmented Programmable Logic Device)

• XPLD (eXpanded Programmable Logic Device)

PLD – CPLD ArchitecturePLD CPLD Architecture

PLD – FPGA ArchitecturePLD FPGA Architecture

• The FPGA architecture consists of many logic modules which are placed in• The FPGA-architecture consists of many logic-modules, which are placed in an array-structure. The channels between the logic-modules are used for routing. The array of logic-modules is surrounded by programmable I/O-modules and connected via programmable interconnects. This freedom ofmodules and connected via programmable interconnects. This freedom of routing allows every logic-module to reach every other logic-module or I/O-module. The worldwide first PLD with FPGA-architecture was developed by Xilinx in 1984.

There are two FPGA architecture subclasses, depending on the granularity of the logic-modules.– Coarse-grained FPGAs– Fine-grained FPGAs.

The coarse-grained FPGAs have very large logic-modules with sometimes t r m r q nti l l i l m nt nd th fin r in d h r impltwo or more sequential logic elements, and the fine-grained have very simple logic-modules. The FPGA-architecture offers the highest programmable logic capacity.

– FPGA (Field Programmable Gate Array)

– LCA (Logic Cell Array)

– pASIC (programmable ASIC)

– SPGA (System Programmable Gate Array)

– XPGA (eXpanded Programmable Gate Array)( p g y)

HDL LanguagesHDL Languages

• Verilog

• VHDL

• Abel

• System-C

• National Semiconductor Labview

• Handel – C

R b• Ruby

ReferencesReferences

• http://www.fpga-guide.com/architecture_frame.html

• www.eecg.toronto.edu/~jayar/pubs/brown/survey.pdf

• www.cpu-turkey.com/downloads/file.aspx?id=87

• www elabsp com• www.elabsp.com

• en.wikipedia.org/wiki/Programmable_Array_Logic

• http://en.wikipedia.org/wiki/Hardware_description_language

Microcontroller ArchitectureMicrocontroller Architecture

Processor A hit tArchitecture

Harvard Von NeumannNeumann

Historical Back GroundHistorical Back Ground

Analog ComputingAnalog Computing

ENIAC – First General Purpose ComputerENIAC First General Purpose Computer

El i N i l I A d C h fi l• Electronic Numerical Integrator And Computer was the first general-purpose electronic computer. It was a Turing-complete digital computer capable of being reprogrammed to solve a full range of computing problems.

• The construction contract was signed on June 5, 1943, and work on the computer began in secret by the University of Pennsylvania's Moore School

f El i l E i i i h f ll i h d h dof Electrical Engineering starting the following month under the code name "Project PX". The completed machine was announced to the public the evening of February 14, 1946.

• ENIAC was designed to calculate artillery firing tables for the United States Army's Ballistic Research Laboratory.

ENIAC – First General Purpose ComputerENIAC First General Purpose Computer

Von Neumann Vs Harvard ArchitectureVon Neumann Vs Harvard Architecture

Von Neumann ArchitectureVon Neumann Architecture

Harvard ArchitectureHarvard Architecture

Assignment # 2Assignment # 2

• Read the Research paper related to PLDs designRead the Research paper related to PLDs design

• Find out the architecture of the following microcontrollers

– PIC micro Series

– 8051/ 8052

A l AVR i– Atmel AVR series

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