© 2011 IBM Corporation Placement: Hot or Not Chuck Alpert Design Productivity Group Austin Research...

© 2011 IBM Corporation

Placement: Hot or Not

Chuck AlpertDesign Productivity GroupAustin Research Laboratory

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

The State of Placement

Placement is an old problem

Rajeev: Today, the EDA academic community is not producing a lot of new ideas. Yes, at one time they did, but not today.

“Lou Scheffer” : place-and-route is in reasonable shape

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Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Placement Trends (my guess, not scientific)

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Chip gate count: 21 MLargest Block: 1.5 M

Chip gate count: 76 MLargest Block: 3.7 M

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Placement is Hot

Design sizes are exploding

Designers are embracing automation like never before

Secondary factors (power, area) become differentiating

Wirelength is no longer primary

– Congestion

– Timing

– Power

– Clock-friendly

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Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Generic Design Flow

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From Cadence

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation6

Vt Optimization?

Swap to lower vt

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation7

Gate Sizing or Repowering

b f

eca d

b f

eca d

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation8

Buffering and Layer Assignment

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation9

Inverter Absorption / Decomposition

b f

eca d

bf

ea g

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation10

Composition / Decomposition

nd2 A

nd2 C

nd2 B

D

Outx

y

z

w

nd2 C

D

y

z

x

w

Out

AOI

Courtesy: Louise Trevillian, founder of Logic Synthesis

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Example Timing Closure “Optimization”

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While 500 most critical nets still optimizable

Gate sizing and vt Optimization

Buffering on sub-tree

Buffering on entire tree

Congestion-aware layer assignment

Suite of logic transforms

For remaining critical nets

Gate sizing and vt Optimization

Buffering, layer assignment on sub-tree

Critical Path Optimization

Compression Optimization

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

What Timing-Driven Placement Means

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Weight all nets? If not, what percent?

What weight range?

What netlist state for

timing-driven placement?

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation13

Over Weight Can Destroy CongestionInitial After Timing-driven

Placement Optimization Placement

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Don’t Put Timing into Placement!

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Timing

PlacementTiming-driven

Placement Flow

Placement

Constraint Generation

Timing

Incremental Placement

Easy Constraints

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Example Incremental Timing-Driven Placement

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Initial

Final

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Techniques Required for Timing-Driven Placement

Identification of “easy” constraints

Incremental Placement

– Shorten critical paths without hurting other paths

– Fast, incremental wirelength recovery

– Congestion-preserving detailed placement (don’t pack!)

– Getting pipeline latches right

Meaningful timing model

Interleave optimization (e.g., layer assignment)

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Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation17

Pipeline Latch Placement

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation18

Pipeline Latch Placement

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© 2011 IBM Corporation19

Interference From Other Logic

Logic

Logic

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Power-Aware Placement

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Switching Factor

#nets

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Congestion Still Huge Problem

Contests focus on congestion-driven placement

Also need for incremental congestion repair

Fast, accurate congestion modeling is key

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Placement A Placement B

Router 1

Placement A Placement B

Router 2

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Placement Density Reasonable First Order

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Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation23

Local Congestion Effects (Pin Density)

Before Spreading After Spreading

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© 2011 IBM Corporation24

Handling Movebounds

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Move Bound Challenges

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Don’t increase runtime

High density / low density

Inclusive or exclusive

OverlappingSoft or absolute

Different shapes

Support high quantity

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Datapath Placement

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LEGAL HPWL = 2385800 LEGAL HPWL = 2513500 LEGAL HPWL = 2461745Base Run Soft Alignment Forced Alignment

net1net1

Courtesy: Sam Ward

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation28 July 26, 2012

Latch Huddling: Good For Clock Skew and Power

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Why Huddling is Good for Clocks

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More Clock Wire Less Clock Wire

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© 2011 IBM Corporation30

All Object Movement (Before and After Huddling)

Global Huddling Placement Incremental Huddling Placement

movement(in tracks)

1-5050-100

100-200200-500

500+

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Global Clock Trees

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Challenge, can we separate three trees to prevent routing overlap?

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Proposed Placement Framework

Keep placement as a stand alone optimization

Enrich it to handle constraints

Add constraint generation step to guide placement

– Move bounds

– Power Switching factors

– Tightness of latch huddles

– Clock domain separation

– Use of hierarchical name space

– Alignment of datapath

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Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Proposed Placement Flow

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Placement (Global or Incremental)

Constraint Generation

Timing Analysis

Power Analysis

Congestion Analysis

Clock Analysis

Pre-Placement Constraints

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Do We Need to Write a Placer from Scratch?

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Clustering

Clustered Global

Flat Global

Density Spreading

Congestion Mitigation

Fast Congestion Analysis

Congestion-aware Detailed Placement

Pin-Density Spreading

Power Reduction

Design Productivity Group, Austin Research Laboratory

© 2011 IBM Corporation

Chasing the Hot Topics

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Instead of trying to predict the next important problem

Just ask (a designer)