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VLSI IMPLEMENTATION OF OFDM

Vlsi implementation ofdm

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Vlsi implementation of ofdm along with its complete description of transmitter and reciever parts.

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Page 1: Vlsi implementation ofdm

VLSI IMPLEMENTATION OF OFDM

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Orthogonal Frequency Division Multiplexing or OFDM is a modulationformat that is being used for many of the latest wireless andtelecommunications standards.

OFDM has been adopted in the Wi-Fi arena where the standards like802.11a, 802.11n, 802.11ac and more. It has also been chosen for thecellular telecommunications standard LTE / LTE-A, and in addition tothis it has been adopted by other standards such as WiMAX and manymore.

Orthogonal frequency division multiplexing has also been adopted for anumber of broadcast standards from DAB Digital Radio to the DigitalVideo Broadcast standards, DVB.

Although OFDM, orthogonal frequency division multiplexing is morecomplicated than earlier forms of signal format, it provides somedistinct advantages in terms of data transmission, especially where highdata rates are needed along with relatively wide bandwidths.

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WHAT IS OFDM? An OFDM signal consists of a number of closely spaced modulated carriers.When modulation of any form - voice, data, etc. is applied to a carrier, thensidebands spread out either side.

It is necessary for a receiver to be able to receive the whole signal to be ableto successfully demodulate the data. As a result when signals aretransmitted close to one another they must be spaced so that the receivercan separate them using a filter and there must be a guard band betweenthem.

This is not the case with OFDM. Although the sidebands from each carrieroverlap, they can still be received without the interference that might beexpected because they are orthogonal to each another. This is achieved byhaving the carrier spacing equal to the reciprocal of the symbol period.

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Traditional View Of Receiving Signals

Carrying Modulation

To see how OFDM works, it is necessary to look at the receiver. This actsas a bank of demodulators, translating each carrier down to DC. Theresulting signal is integrated over the symbol period to regenerate thedata from that carrier. The same demodulator also demodulates the othercarriers. As the carrier spacing equal to the reciprocal of the symbolperiod means that they will have a whole number of cycles in the symbolperiod and their contribution will sum to zero - in other words there is nointerference contribution.

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One requirement of the OFDM transmitting and receiving systems is thatthey must be linear. Any non-linearity will cause interference between thecarriers as a result of inter-modulation distortion. This will introduceunwanted signals that would cause interference and impair theorthogonality of the transmission.

OFDM Spectrum

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DATA ON OFDMThe data to be transmitted on an OFDM signal is spread across the carriers of thesignal, each carrier taking part of the payload. This reduces the data rate taken byeach carrier. The lower data rate has the advantage that interference fromreflections is much less critical. This is achieved by adding a guard band time orguard interval into the system. This ensures that the data is only sampled when thesignal is stable and no new delayed signals arrive that would alter the timing andphase of the signal.

The distribution of the data across a large number of carriers in the OFDM signal hassome further advantages. By using error-coding techniques, which does meanadding further data to the transmitted signal, it enables many or all of the corrupteddata to be reconstructed within the receiver.

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BASIC PRINCIPLE OF OFDMProduct modulator

Sub-carrier

Sub-carrier

Sub-carrier

Separate local oscillators to generate each individual sub-carrier

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OFDM SYSTEMCORRELATION RECEIVER

8

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OFDM ADVANTAGES OFDM can easily adapt to severe channel conditions without the need for

complex channel equalisation algorithms being employed

It is robust when combatting narrow-band co-channel interference. Asonly some of the channels will be affected, not all data is lost and errorcoding can combat this.

Intersymbol interference, ISI is less of a problem with OFDM because lowdata rates are carried by each carrier.

Provides high levels of spectral efficiency.

Relatively insensitive to timing errors

Allows single frequency networks to be used - particularly important forbroadcasters where this facility gives a significant improvement in spectralusage.

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OFDM DISADVANTAGES

High peak-to average-power ratio (PAPR) This put high demand on linearity in amplifiers.

Phase noise error cause degradation to OFDM system

Very sensitive time frequency synchronization

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Coding

IFFT (Tx)

De-interleaving

QPSKDemapping

Parallel To Serial

Serial ToParallel

Remove Cyclic

Extension

Decoding

Interleaving

QPSKMapping

Serial toparallel

Parallel to serial

Add cyclic Extension and

windowing

Output Of Transmitter

Input to Receiver

FFT(Rx)

Data input to Transmitter

Data received

Scrambler

Synchronization

Channel Estimate

Equalizer

DeScrambler

OFDM TRANSCEIVER AND IMPLEMENTATION

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SCRAMBLER(RANDOMIZER)

In the proposed design, a standard 7 bit scrambler has been used torandomize the incoming bits.

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INTERLEAVER

Two memory elements (usually RAMs) are used. In the first RAM the incoming blockof bits is stored in sequential order. This data from the first RAM is read outrandomly (using an algorithm) so that the bits are re-arranged and stored in thesecond RAM and then read out.

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The three building blocks of the interleaver are:• Block Memory• Controller• Address ROM

The job of the controller is to guide the incoming block of data to thecorrect memory blocks, to switch the RAMs between reading and writingmodes, and to switch between the two RAMs for 16 alternate bits inwriting mode. This is done by using counters.

The address ROM is basically a 64x6 ROM that stores read addresses forthe RAMs.

Counter C is a 3-bit counter that controls switching between either RAM1A and RAM 2A or RAM 1B and RAM 2B depending upon which RAMsare in write mode. Counter1 and Counter2 are 5-bit counters afterevery 8th count control switches to either Counter1 or Counter2; thisis controlled by Counter C.

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CONSTELLATION MAPPER

Signal constellation of QPSK

* * * *

* * * *

-3m/8 -m/8 m/8 3m/8

* * * *

* * * *

In QPSK two bits make up one symbol.

Mapping of bits to constellation points

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A ROM is used to store the constellation points. Each constellation point is

represented by 48 bits in binary. In these 48 bits, the most significant 24 bits

represent the real part and the least significant 24 bits represent the

imaginary part.

In both the real and imaginary parts the most significant 8 bits are the integer

part and the least significant 16 bits represent the fractional part. 2’s

complement notation has been used to represent negative numbers.

The size of ROM is 4x48. The incoming input bits (2 bits) act as address for the

ROM. Each ROM values in the ROM is a constellation point corresponding to

the data bits which here act as addresses for the ROM.

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SERIAL TO PARALLEL MODULE

The data comes serially from the input port SERIN. The parallel data is output

from DOUT port. Output port DRDY is asserted ‘1’ when the start bit, 8 bit data

and the parity bit is received. Output port PERRn is asserted ‘0’ when the parity

bit received is different from the parity generated inside the serial to parallel

circuit. When parity error is detected, the serial to parallel circuit would be reset

before its normal operation can be performed.17

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IFFT DESIGN64-point Radix-2^2 fixed-point DIT FFT

Since in the proposed design there are 64 sub-carriers so the input to FFT wouldbe 64 complex numbers, hence a 64 point FFT would be required.

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PARALLEL TO SERIAL MODULE

A parallel to serial converter is a special function of shift register. The data is

parallel loaded to the shift register and then shift out bit by bit also is bounded

by a start bit and stop bit.

Data to be transmit is first parallel loaded then transmitted bit by bit by a start

bit of value ‘1’. This is followed by the 8-bit data with the left bit most bit first.

The converter holds the output low when the transmission is completed.

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CYCLIC PREFIX ADDER

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Causes intercarrierinterference (ICI)

If multipath delay is less than the cyclic prefix no intersymbol or intercarrier interference

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RECEIVER DESIGN AND IMPLEMENTATION The receiver follows an exact reverse procedure of which was followed in the transmitter. It receives the complex (modulated) output points and performs demodulation and recovers the original bits sent to the transmitter.

CYCLIC PREFIX REMOVER

The cyclic prefix was added at the transmitting end in order to avoidinter-symbol interference, therefore during reception it must be eliminatedfor any further processing of the received signal. This is done by simplyskipping the first eight sub-carriers in the received OFDM symbol. Inhardware this is implemented in the control unit. The control unit onlyenables the next block (FFT) when the first eight bits of the received OFDMsymbols have been skipped .

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FAST FOURIER TRANSFORMIn order to implement FFT in hardware the algorithm is same, only the

difference is that the divider is removed and the real and imaginary parts at the

input are swapped i.e. real becomes imaginary and imaginary becomes real.

Same goes for the output i.e. real and imaginary parts at the output are

swapped as well.

CONSTELLATION DE-MAPPER

Therefore, basically the incoming constellation points are mapped onto the datapoints as shown in Table. Can be implemented by direct coding.

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DE-INTERLEAVER

De-interleaving performs the inverse task. It re-arranges the interleaved bits into their

original order. De-interleaving is done the same way as Interleaving, the difference being

that the number of rows and the number of columns for de-interleaving are

interchanged. Hence the only difference in the hardware architectures of interleaver and

de-interleaver is the contents of the address ROM, which actually provides the read

addresses to the RAM that stores the data to be de-interleaved.

DESCRAMBLER

The above setup simply descrambles the scrambled data

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VITERBI DECODERThe Viterbi Decoder decodes Convolutional codes. Altera’s Viterbi IP core is a

parameterized IP core that is synthesizable and allows for parallel as well as

hybrid implementation of the Viterbi decoder.

BMUBranch metrics computation unit calculates the hamming distances for theincoming pair of codes from four possible codes.

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ACSAdd, compare and select unit is used to update the path metric for all the 64 statesand select the predecessor. For each of the 64 states, it adds current path metricand branch metric for both the predecessor states and selects the lower of the twoas the new path metric and the predecessor information is passed on to the SMUunit.

The width of the Path metric register and the ACS adders and subtractor willchange based on whether a soft-decision or a hard-decision viterbi is ued. It alsodepends on the maximum metrics accumulated by metrics registers before anormalization is done.

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VLSI IMPLEMENTATION

Lower gate count compared to DSP+RAM+ROM, hence lower cost.

Low power consumption

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DESIGN METHODOLOGYEarly in the development cycle,different communication andsignal processing algorithms areevaluated for their performanceunder different conditions likenoise, multipath channel andradio non-linearity. Since most ofthese algorithms are coded in "C"or tools like MATLAB, it isimportant to have a verificationmechanism which ensures thatthe hardware implementation(RTL) is same as the "C"implementation of the algorithm.The flow is shown in the Figure.

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SPECIFICATIONS OF THE OFDM TRANSCEIVER

Area - Smaller the die size lesser the chip cost

Power - Low power crucial for battery operated mobile devices

Ease of implementation - Easy to debug and maintain

Customizability - Should be customizable to future standards with variations in OFDM parameters

Data rates to be supported

Range and multipath tolerance

Indoor/Outdoor applications

Multi-mode: 802.11a only or 802.11a+HiperLAN/2

DESIGN TRADE-OFF

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ALGORITHM SURVEY & SIMULATION

The simulation at algorithmic level is to determine performance of algorithmsfor various non-linearity’s and imperfections. The algorithms are tweaked andfine tuned to get the required performance. The followingalgorithms/parameters are verified

• Channel estimation and compensation for different channel models (Rayleigh,Rician, JTC, Two ray) for different delay spreads

• Correlated performance for different delay spreads and different SNR

• Frequency estimation algorithm for different SNR and frequency offsets

• Compensation for Phase noise and error in Frequency offset estimation

• System tolerance for I/Q phase and amplitude imbalance

• FFT simulation to determine the optimum fixed-point widths

• Wave shaping filter to get the desired spectrum mask

• Determine clipping levels for efficient PA use

• Effect of ADC/DAC width on the EVM and optimum ADC/DAC width

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FIXED POINT SIMULATION• One of the decisions to be taken early in the design cycle is the format or

representation of data. Floating point implementation results in higher hardwarecosts and additional circuits related with normalizing of numbers. Floating pointrepresentation is useful when dealing with data of different ranges. But thishowever is not true as the Baseband circuits have a fair idea of the range of valuesthey will work on. So a fixed-point representation will be more efficient. Further infixed point a choice can be made between signed and 2's complementrepresentation.

• The width of representation need not be constant throughout the Baseband and itdepends on the accuracy needed at different points in transmit or receive path. Asmall change in the number of bits in the representation could result in a significantchange in the size of arithmetic circuits especially multipliers.

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SIMULATION SETUP

• The algorithms could be simulated in a variety of tools/languageslike SPW, MATLAB, “C” or a mix of these.

• SPW has an exhaustive floating point and fixed-point library. SPWalso provides feature to plug-in RTL modules and do a co-simulation of SPW system and Verilog. This helps in verifying theRTL implementation of algorithms against the SPW/Cimplementation.

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HARDWARE DESIGNBaseband interfaces with two external modules: MAC and Radio.

INTERFACE TO MACBaseband should support the following for MAC Should support transfer of data at different rates Transmit and receive control Register programming for power and frequency control

Following options are available for MAC interface:

Serial data interface – Clock provided along with data. Clock speed changes fordifferent data rates

Varying data width, single speed clock – The number of data lines vary according tothe data rate. The clock remains same for all rates.

Single clock, Parallel data with ready indication – Clock speed and data width is samefor all data rates. Ready signal used to indicate valid data

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INTERFACE TO RADIOTwo kinds of radio interfaces are described below

I/Q interfaceOn the transmit side, the complex Baseband signal is sent to the radio unit thatfirst does a Quadrature modulation followed by up-conversion at 5 GHz. On thereceive side, following the down-conversion to IF, Quadrature demodulation isdone and complex I/Q signal is sent to Baseband. Shown below is the interface.

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IF interfaceThe Baseband does the Quadrature modulation and demodulation digitally.

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CLOCKING STRATEGY

The 802.11a supports different data rates from 6 Mbps to 54 Mbps. The clock scheme chosen for the Baseband should be able to support all rates and also result in low power consumption. We know from our Basic ASIC design guidelines that most circuits should run at the lowest clock.

Two options are shown below:

Above scheme requires different clock sources or a very high clock rate from which all these clocks could be generated.

The modules must work for the highest frequency of 54 MHz.

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Shown in the figure is a simpler clocking scheme with only one clock speed for all data rates

Varying duty cycles for different data rates is provided by the data enable signal

All the circuits in the transmit and receive chain work on parallel data (4 bits)

Overhead is the Data enable logic in all the modules

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Optimize Usage Of Hardware Resources By Reusing Different Blocks

Hardware resources can be reused considering the fact that 802.11a system is a half-duplex system. The following blocks are re-used:

• FFT/IFFT

• Interleaver/De-interleaver

• Scrambler/Descrambler

• Intermediate data buffers

Since Adders and Multipliers are costly resources, special attention should be given toreuse them. An example shown below where an Adder/Multiplier pool is created anddifferent blocks are connected to this.

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Identify the blocks that are used at several places (several instances of the same unit)and optimize them. Optimization can be done for power and area. Some of thecircuits that can be optimized are:

Multipliers

• They are the most widely used circuits. Synthesis tools usually provide highlyoptimized circuits for multipliers and adders.

• In case optimized multipliers are not available, multipliers could be designed usingdifferent techniques.

ACS unit

• There are 64 instantiations of ACS unit in the Viterbi decoder. Optimization of ACSunit results in significant savings.

• Custom cell design (using foundry information) for adders and comparators couldbe considered.

Optimize the widely used circuits

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THANK YOU