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Xeon+FPGA: Better Together An Overview of Architecture and Practices Elijah Charles, Gaurav Kaul Intel Corporation

Using Xeon + FPGA for Accelerating HPC Workloads

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Xeon+FPGA: Better Together An Overview of Architecture and Practices

Elijah Charles, Gaurav Kaul

Intel Corporation

Legal Notices and Disclaimers

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Tests document performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit http://www.intel.com/performance.

Cost reduction scenarios described are intended as examples of how a given Intel-based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction.

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The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Currentcharacterized errata are available on request.

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*Other names and brands may be claimed as the property of others.

OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.

© 2015 Intel Corporation.

Risk Factors

3

The above statements and any others in this document that refer to plans and expectations for the second quarter, the year and the future are forward-looking statements that involve a number of risks and uncertainties. Words such as "anticipates," "expects," "intends," "plans," "believes," "seeks," "estimates," "may," "will," "should" and their variations identify forward-looking statements. Statements that refer to or are based on projections, uncertain events or assumptions also identify forward-looking statements. Many factors could affect Intel's actual results, and variances from Intel's current expectations regarding such factors could cause actual results to differ materially from those expressed in these forward-looking statements. Intel presently considers the following to be important factors that could cause actual results to differ materially from the company's expectations. Demand for Intel's products is highly variable and could differ from expectations due to factors including changes in business and economic conditions; consumer confidence or income levels; the introduction, availability and market acceptance of Intel's products, products used together with Intel products and competitors' products; competitive and pricing pressures, including actions taken by competitors; supply constraints and other disruptions affecting customers; changes in customer order patterns including order cancellations; and changes in the level of inventory at customers. Intel's gross margin percentage could vary significantly from expectations based on capacity utilization; variations in inventory valuation, including variations related to the timing of qualifying products for sale; changes in revenue levels; segment product mix; the timing and execution of the manufacturing ramp and associated costs; excess or obsolete inventory; changes in unit costs; defects or disruptions in the supply of materials or resources; and product manufacturing quality/yields. Variations in gross margin may also be caused by the timing of Intel product introductions and related expenses, including marketing expenses, and Intel's ability to respond quickly to technological developments and to introduce new products or incorporate new features into existing products, which may result in restructuring and asset impairment charges. Intel's results could be affected by adverse economic, social, political and physical/infrastructure conditions in countries where Intel, its customers or its suppliers operate, including military conflict and other security risks, natural disasters, infrastructure disruptions, health concerns and fluctuations in currency exchange rates. Results may also be affected by the formal or informal imposition by countries of new or revised export and/or import and doing-business regulations, which could be changed without prior notice. Intel operates in highly competitive industries and its operations have high costs that are either fixed or difficult to reduce in the short term. The amount, timing and execution of Intel's stock repurchase program could be affected by changes in Intel's priorities for the use of cash, such as operational spending, capital spending, acquisitions, and as a result of changes to Intel's cash flows or changes in tax laws. Product defects or errata (deviations from published specifications) may adversely impact our expenses, revenues and reputation. Intel's results could be affected by litigation or regulatory matters involving intellectual property, stockholder, consumer, antitrust, disclosure and other issues. An unfavorable ruling could include monetary damages or an injunction prohibiting Intel from manufacturing or selling one or more products, precluding particular business practices, impacting Intel's ability to design its products, or requiring other remedies such as compulsory licensing of intellectual property. Intel's results may be affected by the timing of closing of acquisitions, divestitures and other significant transactions. A detailed discussion of these and other factors that could affect Intel's results is included in Intel's SEC filings, including the company's most recent reports on Form 10-Q, Form 10-K and earnings release.

Rev. 4/14/15

Agenda

4

• Accelerators: Motivation and Use Cases

• Using Field Programmable Gate Array (FPGA) as an Accelerator

• Intel® Xeon® Processor + FPGA Accelerator Platform

• Hardware and Software Programming Interfaces

• Example Applications

50¹ BillionDEVICES

Build out of the CLOUD

$120B³New

SERVICES$450B²

1: Sources: AMS Research, Gartner, IDC, McKinsey Global Institute, and various others industry analysts and commentators

2: Source IDC, 2013. 2016 calculated base don reported CAGR ‘13-’17

4 3: Source: iDATA /Digiworld,2013

Digital Services Economy…

…Fueling Cloud Computing Growth

6

Cloud Economics

Amazon’s TCO Analysis¹

VMs per System

Web Transactions / Sec

Storage Capacity

Hadoop Queries

Workload Performance Metrics

1: Source: James Hamilton, Amazon* http://perspectives.mvdirona.com/2010/09/overall-data-center-costs/

Performance / TCO is the key metric

7

Diverse Data Center Demands

Accelerators can increase Performance at lower TCO for targeted workloads

8 Intel estimates; bubble size is relative CPU intensity

Agenda

9

• Accelerators: Motivation and Use Cases

• Using Field Programmable Gate Array (FPGA) as an Accelerator

• Intel® Xeon® Processor + FPGA Accelerator Platform

• Hardware and Software Programming Interfaces

• Example Applications

Accelerator Architecture Landscape

Application Flexibility

Ease of Programming/Development

Fixed Function Accelerator

10

ReconfigurableAccelerator

CPU

Benefits of Reconfigurable Accelerators:Savings in Area /Power

• Can be configured to implement different functions efficiently

- Meeting performance goals for segment

- Saving area and power compared to multiple Fixed Functions

Fixed FunctionsCost

Programmable Accelerator

Software

Performance

10

Benefits of Reconfigurable Accelerators:Meeting Customer Needs for Differentiation

Workload O ptimized

Silicon

12

Pervasive Analytics &

Insights

Intelligent Resource

O rchestration

DynamicResourcePooling

Driving the Digital ServiceEconomy

What is a Field Programmable Gate Array (FPGA)?

FPGAs (Field Programmable Gate Arrays) are semiconductor devices that can be programmed

13

• Desired functionality of the FPGA can be (re-) programmed by downloading a configuration into the device

FPGAs offer several advantages over potentialalternatives:

• Lower one-time development cost, and faster time to market compared to custom designed chips (ASICs)

• Ability to implement customer-specific functionality beyondwhat is available from standard products (ASSPs)

• Customizable and reprogrammable after the device has been deployed to the field compared to both ASIC and A S S P

Logic Blocks

Interconnect Resources

I/O Cells

A Complete Solutions Portfolio

CPLDs

Lowest Cost,

Lowest Power

PowerSoCs

High-efficiency

Power Management

FPGAs

Cost/Power Balance

DesignSoftware

Development Kits

Embedded Soft andHard Processors

FPGAs

Mid-range FPGAs

P O W E R I N G Y O U R I N N O V A T I O N

SoC & Transceivers SoC & Transceivers

R E S O U R C E S

FPGAs

Optimized for

High Bandwidth

Intellectual Property (IP)

Industrial

Computing

Enterprise

14

Efficiency via Specialization

ASICsFPGAs

Source: Bob Broderson, Berkeley Wireless group

GPUs

OpenCL and FPGAs Address These Challenges

Power efficient acceleration

– Typically 1/5 power of GPU and orders of magnitude more performance per watt of CPU

FPGA lifecycle over 15 years

– GPUs lifespan is short

Require re-optimization testing between generations

– FPGA OpenCL code retargeted to future devices without modification

Our OpenCL flow abstracts away FPGA hardware flow

– Puts FPGA into software engineers hands

Our OpenCL SDK allows for streaming IO channels and kernel

channels

– Data movement without host involvement

– Low latency data transmissions to accelerator

Shared virtual memory

– IBM CAPI and Intel QPI16

More SW Engineering Resources than HW?

1000:1 software engineers to FPGA designers

Software engineers are not used to long compile

17

times OpenCL Solves This!

Our OpenCL flow abstracts away FPGA hardware flow

bringing the FPGA to low level software programmers Software developers write, optimize and debug in their software familiar

environment

Quartus is run behind the scenes

Emulator and profiler are software development tools

Pushing long compile times to end

OpenCL optimization doesn’t require a board Allowing SW to drive board requirements (.xml file)

Application Development Paradigm

ASIC

FPGAProgrammers

Parallel

Programmers

Standard CPU Programmers

OpenCL expands

The number of

application developers

18

Agenda

19

• Accelerators: Motivation and Use Cases

• Using Field Programmable Gate Array (FPGA) as an Accelerator

• Intel® Xeon® Processor + FPGA Accelerator Platform

• Hardware and Software Programming Interfaces

• Example Applications

Intel® Xeon® E5 + Field Programmable Gate Array Software Development Platform (SDP) Shipping Today

Intel QPI

DDR3

DDR3

DDR3

DDR3

DDR3

PC

Ie 3

.0x8

DM

I2

PC

Ie 3

.0x8

PC

Ie3

.0x8

PC

Ie 3

.0x8

PC

Ie 3

.0x8

PC

Ie 3

.0x8

DDR3

Intel Xeon Processor E5

Product FamilyFPGA

Processor Intel Xeon Processor E5

FPGA Module Altera* Stratix* V

QPI Speed 6.4 GT/s fullwidth(target 8.0 GT/s at full width)

Memory to FPGA Module

2 channels of DDR3 (up to 64 GB)

Expansionconnectorto FPGA Module

PCI Express® (PCIe) 3.0 x8 lanes - maybe used for direct I/O e.g. Ethernet

Features

Configuration Agent, Caching Agent, (optional) Memory Controller

Software

Accelerator Abstraction Layer(AAL) runtime, drivers, sampleapplications

Software Development for Accelerating Workloads using Intel® Xeon® processors and coherently attached FPGA in-socket

20

Intel® QuickPath Interconnect (Intel® QPI)

System Logical View

• AFUs can access coherent cache on FPGA

• AFUs can “not” implement a second level cache

• Intel® Quick Path Interconnect (Intel® QPI) IP participates in cache coherencywith Processors

A F U sQ P I

D R A MD R A M

D D R

D R A M

P r o c e s s o r

C o re s L L C

F P G A

C C I

M u l t i - p r o c e s so r C o h e r e n c e D o m a i n C a c h e a c c e s s D o m a i n

C

a

c

h

e

21

In te l

Q P I

I P

Intel® Xeon® + Field Programmable Gate Array SDP: Intel® Quick Path Interconnect 1.1 RTL Microarchitecture

• PHY – Implements the Intel QPI PHY 1.1 (Analog/Digital)

• Intel QPI Link layer- provides flow controland reliable communication

• Intel QPI Protocol – implements Intel QPI Cache Agent + Configuration Agent

• Cache Controller – Cache hit/miss determination and generates Intel QPI protocol requests.

• Cache Tag – Tracks state of cacheline (MESI + internal states for tracking outstanding requests)

• Coherency Table – Programmable table that implements coherency protocol rules

• System Protocol Layer (SPL2) – Implements Address translation functionality. Can provide up to 2GB device virtual address space to AFU. SPL2 cannot handle page faults.

• AFU – User designed Accelerator Function Unit

Q P I L i n k / P r o t o c o l C o n t r o l

Q P I P H YR x A l i g n T x A l i g n

R x C o n t r o l T x C o n t r o l

C a c h e c o n t r o l l e r

C a c h e

D a t a

C a c h e T a g

C a c h e T a b l e

R x

T x

S P L 2

C C I- E

R x

T x

C C I- S

In te l Q P I F P G A IP

6 4 0 b i t s6 4 0 b i t s

A d d r e s s t rans la t ion

U s e r :A cce le ra to r F u n c t i o n Un i t ( A F U )

Intel® QuickPath Interconnect (Intel® QPI) Q P I i n t e r f a c e t o p i n s22

Agenda

23

• Accelerators: Motivation and Use Cases

• Using Field Programmable Gate Array (FPGA) as an Accelerator

• Intel® Xeon® Processor + FPGA Accelerator Platform

• Hardware and Software Programming Interfaces

• Example Applications

Intel® Xeon® Processor + Field Programmable Gate Array Tool Flow

C HDL

SWCompiler

S yn. PAR

exebit-

stream

Intel® Xeon®

AAL

FPGAShell

Host Kernels

SWCompiler

OpenCL Compiler

exebit-

stream

HDL Programming OpenCL™ Programming

Intel Xeon

AAL

FPGAShell

Accelerator Abstraction Layer Field Programmable Gate Array (FPGA)24

Programming Interfaces

Host Application

Virtual Memory API

Intel QPI/KTI Link,Protocol, & PHY

CPU

Accelerator FunctionUnits (AFU)

CCI1

extendedAddr Translation

CCI1

standard

Service API

Physical Memory API

Interfaces

Accelerator Abstraction

Layer

Field Programmable Gate Array

25 Intel® QuickPath Interconnect (Intel® QPI) 2. Software Development Platform 4. Register Transfer Level

Intel QPI

Standard Programming Interfaces : AAL and CCIProgramming interfaces will be forward compatible from SDP2 to future MCP3 solutions

Simulation Environment available for development of SW and RTL4

1. Coherent Cache Interface 3. Multi-chip package

Programming Interfaces: OpenCL™

OpenCL Application

Virtual Memory API VirtMem

CPU

OpenCL Kernels

CCIExtended

CCIStandard

Service API

Physical Memory API

Accelerator Abstraction

Layer

CFG

Physical Memory API

OpenCL RunTime

OpenCL™Host Code

OpenCL Kernel Code

Field Programmable Gate Array

Intel QPI/PCI Express®

System Memory

Unified application code abstracted from the hardware environment Portable across generations and families of CPUs and FPGAs

20 Intel® QuickPath Interconnect (Intel® QPI)

Agenda

21

• Accelerators: Motivation and Use Cases

• Using Field Programmable Gate Array (FPGA) as an Accelerator

• Intel® Xeon® Processor + FPGA Accelerator Platform

• Hardware and Software Programming Interfaces

• Example Applications

Example Usage:Deep Learning Framework for Visual Understanding

clu

ster

no

de

dev

ice

pri

mit

ives

DMA

Wei

ghts

Inp

uts

Ou

tpu

ts

Processing Tile ‘n’

Processing Tile 1

Processing Tile 0

PE PE PE

Read Write RegAccess

Control State

Machine

IPRegisters

CCI Interface

SRAM Controller

CNN (Convolutional Neural Network) function accelerated on FPGA: Power-performance of CNN classification boosted up to 2.2X†

22 microbenchmark. In order to sustain ~2400 img/s we need a I/O bandwidth of ~500 MB/s, which can be supported by a 10GigE link and software stack

†Source: Intel Measured (Intel® Xeon® processor E5-2699v3 results; Altera Estimated (4x Arria-10 results)2S Intel( Xeon E5-2699v3 + 4x GX1150 PCI Express® cards. Most computations executed on Arria-10 FPGA's, 2S Intel Xeon E5-2699v3 host assumed to be near idle, doing misc. networking/housekeeping functions.

Arria-10 results estimated by Altera with Altera custom classification network. 2x Intel Xeon E5-2699v3 power estimated @ 139W while doing "housekeeping" for GX1150 cards based on Intel measured

Example Usage:

HaplotypeCaller (PairHMM

Genomics Analysis ToolkitBWA mem (Smith-Waterman

PairHMM function accelerated on FPGA:Power-performance of pHMM boosted up to 3.8X†

23 essentially idle when work load is offloaded to the FPGA)

†pHMM Algorithm performance is measured in terms of Millions Cell Updates per seconds (CUPS).Performance projections: CPU Performance: includes: 1 core Intel® Xeon® processor E5-2680v2 @ 2.8GHz delivers 2101.1 MCUP/s measured; estimated value assumes linear scaling to 10 Cores on Xeon ES2680v2 @

2.8 GHz & 115W TDP; FPGA Performance includes: 1 FPGA PE (Processing Engine) delivers 408.9 MCUP/s @ 200 MHz measured; estimated value assumes linear scaling to 32 PEs and 9 0 % frequency scaling on Stratix-V A7 400 MHz based on RTL Synthesis results (35W TDP). Intel estimated based on 1S Xeon E5-2680v2 + 1 Stratix-V A7 with QPI 1.1 @ 6.4 GT/s full width using Intel® QuickAssist FPGA System Release 3.3, ICC (CPU is

Intel® Xeon® + FPGA1 in the Cloud Vision

Workload

Static/dynamic FPGA programming

Placeworkload

Intel® Xeon®+FPGA

Orchestration Software

Intel Developed IP

3rd party Developed IP

Resource Pool

Storage Network Compute

Software Defined Infrastructure

FPGA Vendor Developed IP

Cloud Users

IP Library

End UserDeveloped IP

Launch workload

1: Field Programmable GateArray (FPGA)30

Workloadaccelerators

“Programmer Friendly” Acceleration

Software Programmers

• Need Logic and Data Management– By writing lines of code

OpenCL™ Compiler Benefits

• Ease of use

• Scalable

• Heterogeneous

• Leverage existing libraries

• Vendor choice w/open standards

• Foundation for OpenMP (80% reuse)

Channels/Pipe Extension

• Kernel Kernel

• External IO Kernel

• Mix ‘n Match HDL & Kernels

I/O I/OKernel Kernel Kernel

DDRx Global MemoryBuffer

Context

Compile code Create data& arguments

Execute

CPU FPGA

© 2015 Altera Corporation–Public 31

Spectrum of Workload Acceleration

Software Library

39

Processor Instruction

Discrete Accelerator

Integrated Accelerator

Example: Data PlaneDevelopment Kit

Example: FieldProgrammableGate Array

Quick AssistTechnology

Example: Intel® Iris™ Pro Graphics

Example: Intel® Advanced Vector Extensions

Workload Acceleration Beyond CPU

Intel® SiliconPhotonics

Intel® Omni-Path Fabric

3D XPoint™Technology

49

Intel Architecture Vision for Software:Code Once – Run Anywhere

SoftwareLibrary

34

ProcessorInstruction

DiscreteAccelerator

IntegratedAccelerator

Consistent programing modelfor all accelerators

Additional Sources of Information

35

• A PDF of this presentation is available from our Technical Session Catalog: www.intel.com/idfsessionsSF.

• Intel® Xeon Phi™ coprocessor resources: software.intel.com/mic-developer

• Network Compression resources: intel.com/quickassist

• Media Transcoding resources: software.intel.com/intel-media-server-studio

• Storage Cryptography resources: software.intel.com/storage

• FPGA: Please see demo in Altera* booth in the demo showcase