Embed Size (px)
DESCRIPTION
Citation preview
Minimisation of crosstalk in VLSI
ROUTING
Chandrajit Pal
University of Calcutta
SPRING 2010
1
Dedicated to my Sir
Dr. Amlan Chakrabarti
2
Index
• ROUTING
• CROSSTALK OVERVIEW
• EFFECTS OF CROSSTALK
• APPROACHES TO AVOID CROSSTALK
• METHODS TO MINIMISE CROSSTALK
• CONCLUSION
• REFERENCES
3
Routing
• Problem Given a placement, and a fixed number of metal layers, find a valid pattern of horizontal and vertical wires that connect the terminals of the nets Levels of abstraction: Global routing Detailed routing • Objectives Cost components: 1. Area (channel width) – min congestion 2. Wire delays – timing minimization in previous levels 3. Number of layers (fewer layers less expensive) 4. Additional cost components: number of bends, vias 5. Minimisation of crosstalk
4
Fig: shows top view ,3D view and conceptual layout
5
Global vs. Detailed Routing
• Global routing
Input: detailed placement, with exact
terminal locations
Determine “channel” (routing region)
for each net
Objective: minimize area (congestion),
and timing (approximate)
• Detailed routing
Input: channels and approximate
routing from the global routing phase
Determine the exact route and layers
for each net
Objective: valid routing, minimize area
(congestion), meet timing constraints
Additional objectives: min via, power
6
7
Multiple Terminal nets:Steiner Tree
Steiner tree(aka Rectilinear Steiner tree- RST): A tree connecting multiple terminals. Original points:”Demand points”- set D. Added points:”Steiner points”- set S. Edges horizontal or vertical only. Steiner Minimum Tree (SMT) Similar to minimum spanning tree (MST)
– But finding SMT is NP-complete
Many good heuristics introduced to find SMT Algorithm 1 . Find MST 2 . Pass horizontal and vertical lines from each terminal to get the Hannan grid (optimal solution is on this grid) 3. Convert each edge of the MST to an L-shaped route on Hannan grid (add a Steiner point at the corner of L)
8
9
10
VLSI trends:
– Device size is decreasing.
– Increase the no of transistors, interconnection wires
– Size of the channel is decreased.
Effects:
Increasing coupling effect (inductive & capacitive) between
interconnection wires
Result:
crosstalk
11
Topic
A BRIEF DISCUSSION ON CROSSTALK IN VLSI CIRCUITS.
12
Mutual Inductance and Capacitance
Crosstalk is the coupling of energy from one line to another via :
Mutual inductance(magnetic field)
Mutual capacitance(electric field)
13
Mutual Inductance and Capacitance
Mechanism of coupling
the circuit element representing this transfer of energy are the familiar
equations:
Δ IB= -Cm d(VB - VA) and Δ VB= -Lm dIA
dt dt
Mutual inductance will induce current on the victim line opposite of the driving
current(Lenz’s Law).
14
Crosstalk induced noise
The near and far end victim line currents sum to produce the near
and far end crosstalk noise.
Coupled currents:
I near=Icm + I lm I far=Icm - I lm
• Current induced by capacitive coupling goes to both directions • Current induced by inductive coupling goes opposite to the drive current
15
Crosstalk induced noise “Voltage profile of coupled noise”
• Near end crosstalk is always positive
• currents from Lm and Cm always add and flow into the node.
• For PCB’s far end crosstalk is “usually” negative
• current due to Lm larger than current due to Cm.
• Note that far end crosstalk can be positive.
16
Noise: A Key Stopper in Mixed Signal Systems
Skin effect. Dielectric absorption
17
Major effects of crosstalk
1. Signal Integrity illustration
18
Effects of crosstalk (contd…) 2. Noise-on-delay effect:Crosstalk
19
Effects of crosstalk (contd…)
3.Crosstalk can lead to :
- logic faults(especially in dynamic circuits).
- Voltage overshoot(stress,forward biased PN junctions)
4. When noise acts against a normally static signal, it can destroy the
local information carried by the static node in the circuit and
ultimately result in incorrect machine-state stored in a latch.
5.Timing noise
skew(DC component of timing noise).
jitter(AC component of timing noise).
6. EMI and violation of EMC requirements.
20
Basic Approaches in Crosstalk Avoidance
Segregation Spacing
Segregation / Spacing / Ground Shielding (1)
21
Segregation / Spacing / Ground Shielding (2)
• Segregation : Dividing many (noisy) and less(quiet) signal transition wire and merging group by group.(use with shielding)
• Spacing : the method that signal wire to shun each other, when signal net is close to each other (routing channel is not wide)
• Shielding : blocking signal line with ground line to minimize signal interference to the other wire.(ground bounce occurs and must broaden the ground line)
22
Net Ordering
Net ordering is used for minimize crosstalk-critical region between each lines.
When, long line and long line is close together, crosstalk between them is more
larger than long line and short line. So, we must change the permutation of track
for minimizing crosstalk.
• Left : Unordered
track permutation
• Right : Ordered
track permutation
for minimizing
crosstalk
23
Layer Assignment
When using more than 3 layer in channel routing, adjacent signal
wire in same layer results crosstalk. For example, left figure makes
more crosstalk than right.
Layer assignment problem is solved by integer linear programming
or dynamic programming method.
24
Various Techniques To Reduce Crosstalk
The following PCB design techniques can significantly reduce crosstalk in micro-strip or strip-line layouts: SOME TECHNIQUES ARE A RULE OF THUMB.
25
1. Widen spacing S between the signallines as much as routing restrictions will allow. 2. Design the transmission line so that the conductor is as close to the ground plane as
possible. This couples the transmission line tightly to the ground plane and helps decouple it from adjacent signals.
3. Use differential routing techniques where possible, especially for critical nets. 4. Route signals on different layers orthogonal to each other, if there is significant coupling. 5. Minimize parallel run lengths between signals, routing with short parallel sections and minimize long coupled sections between nets.
26
CROSSTALK ESTIMATION
Crosstalk-estimation:
Bounded partitioning: partitions the X-talk bound of each net into the regions its go
through
Net ordering:
orders the net in each regions to require as few spare track as possible
27
Crosstalk Constraints Global Routing (CCGR)
• NP-hard problem
• Two stage heuristic approach – New Steiner tree formulation to minimize the total X-talk.
– X-talk on each net is estimated.
– nets having X-talk violation is then ripped up and re-routed
28
6.Minimum X-talk Steiner tree
Routing graph G={V,E}
Minimized X-talk Extended Global Routing solution for nets 1…. M-1 is given
Place Mth net such that routing topologies for 1 ………. M-1 are kept and total X-talk is minimized
Rip-Up & Rerouting
If solution violates crosstalk constraints Rip-up them Re-route them one net at a time in the order of decreasing violation
29
EXAMPLE
Nets 1,2,3,4, are routed and net 5 is {p1 & p2} c1=2,c2=3,c3=30, c4=36,c5=35
Shortest path root (not feasible): r1=12,r2=20,r3=4, r4=0,r5=32
30
Examples Continues…..
Minimum X-talk root (not feasible): r1=11,r2=2,r3=4, r4=0,r5=13
Optimal Solution: r1=0,r2=2,r3=19, r4=15,r5=32
31
Crosstalk reduction techniques(contd…)
7. Overcome the impedance mismatch by different termination schemes.
A simple parallel termination scheme is shown below.
32
Crosstalk reduction techniques(contd…)
8. A structure for reducing crosstalk in VLSI circuits : the empty areas(3) are filled with ground connections(7 & 11) fig2 below
33
Conclusion
NP-hard problem.
Many others approaches are available.
Some GA based approaches are very successfully implemented
Optimal Solution are taken because some other constraints are there like wire length and congestion .
Also add routing of virtex 5 diagonal from whitepaper
34
References
35
1. “Global Routing with Crosstalk Constraints”
Haj Zhou and D.F. Wong Department of Computer Science, University of Texas
2. VLSI Design Shaahin Hessabi Department of Computer Engineering,
Sharif University of Technology.
3. VLSI Design Automation I – © Kia Bazargan
4. J. J. Xiong and L. He. IEEE Trans on CAD, 2008
5. ALTERA WHITE PAPER,basic principles of signal integrity.
6. Crosstalk-ConstrainedMaze Routing Based on Lagrangian Relaxation
Hai Zhou and D.F. Wong Department of Computer Sciences University of Texas at Austin Austin, TX 78712-1188
7. US PATIENT ,PATIENT NO:US 6,218,631 B1
8. WIRES AS INTERCONNECTS
Li-Rong Zheng and Hannu Tenhunen
Royal Institute of Technology (KTH), Stockholm, Sweden
