Hush…tell you something novel about flash memory

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    24-Jun-2015

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This slides presents a excellent work on flash memory from Non-Volatile Systems Laboratory, University of California, San Diego.

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  • 1. Hushtell you something novelabout flash memory ! Zhichao Liangfrankey0207@gmail.com

2. Outline Background Some tests Possible applications Some extensions 3. Outline Background Some tests Possible applications Some extensions 4. Background Flash manufacturers provide conservative andoften vague guidelines about performance,energy consumption and reliability. The lack of detail complicates the design ofsystems which fully exploit flash memoryscapabilities. 5. Outline Background Some tests Possible applications Some extensions 6. Test subjectsCharacterizing Flash Memory: Anomalies, Observations, andApplications by Laura M. Grupp, Adrian M. Caulfield, Joel Coburnetc.(MIRCO09) 7. The testsQuantify known and unknown idiosyncrasies Performance Energy Efficiency Reliability 8. Read Latency The read latency varies little by manufacturer or chip, and arein good agreement with values from publicly availabledatasheets. 9. Erase Latency Erase latency exhibits a smaller gap, but manufacturer Benjoys an advantage for SLC and E for MLC. 10. Program Latency MLC chips have, on average, longer and enormously variableprogram latencies. 11. Program Speed Anomaly Programming speed varies dramatically between pages inMLC devices in a predictable pattern. 12. Performance Increase Anomaly Performance varies predictably as the devices begin to wearout. 13. Power The table presents peak power, average power, idle power,and per-operation energy for each operation. 14. Program Energy Fast and slow pages show a disparity similar to the one weobserved for program time. 15. Reliability Flash memory can corrupt data in three mainways: wear-out, program disturb and readdisturb. 10 erase-program-read cycles + 990 erase-program. 1 million erases for SLC and 100,000 erases forMLC. 16. Error Rates The difference between SLC and MLC is stark. 17. Disparity in MLC MLC chips show large variation in error rates among pages ina single block. 18. Program Disturb Erase a block and repeatedly program half of one page to 0. 19. Read Disturb Write a test pattern to several blocks on the flash chip andrepeatedly read the pattern back. 20. Summary Fast pages and slow pages in MLC High energy-consumption pages and lowenergy-consumption pages in MLC Better program performance as wear out forSLC and MLC High error-rate pages and low error-rate pagesin MLC Program disturb and read disturb 21. Outline Background Some tests Possible applications Some extensions 22. A variation-aware FTL Mango adds a priority to incoming IO request and itwill do its best to use fast pages for the high-prioritywrites. This variation-aware FTL is evaluated in twoscenarios: Swap&Netbook. For Swap, it can significantly increase responsivenessfor swap requests. For Netbook, it can slightly reduce the energy drainon the battery. 23. Flash-aware data encoding Womcode is a codingtechniques makesrewriting wompossible! Effective lifetime:- SLC: 2*(2/3) = 33% increase- MLC: (2*(2/3) + 1)*(1/2) = 17% increase 24. Outline Background Some tests Possible applications Some extensions 25. Gordon A system architecture for data-centricapplications that combines low-powerprocessors, flash memory, and data-centricprogramming. Performance & Reduced Power ConsumptionGordon: Using Flash Memory to Build Fast, Power-efficient Clusters for Data-intensive Applications by Adrian M. Caufield Laura M. Grupp and Steven Swanson(ASPLOS09) 26. Gordon Node 256GB flash storage, a flash storage controller, 2GB of ECCDDR2 SDRAM, a 1.9Ghz Intel Atom processor and othersupporting circuitry. 27. Gordon Enclosure A enclosure holds 16 nodes(4TB storage) and provides14.4GB/s of aggregate IO bandwidth. 28. Q&A

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