Wishbone tutorials

  • View
    441

  • Download
    2

Embed Size (px)

DESCRIPTION

Verilog code for WISHBONE modules

Transcript

  • 1. WWiisshhbboonnee TTuuttoorriiaallssGGooookkyyii DDeennnniiss AA.. NN..SSooCC DDeessiiggnn LLaabb..October.17.2014

2. CCoonntteenntt Round-Robin Arbiter Module2 3. RRoouunndd--RRoobbiinn AArrbbiitteerr In a shared bus, the arbiter determines whichmaster can use the bus The bus is granted on a rotary basis much like thefour position rotary switch shown below: When a master relinquishes the bus, the switch isturned to the next position and the bus is grantedto the master on the level In this way all masters are granted the bus on anequal basis3MASTER #0MASTER #3MASTER #2MASTER #1 4. RRoouunndd--RRoobbiinn AArrbbiitteerr Arbiter general topology:4LASMASSTATEMACHINEREGISTERCOMCYCLOGICENCODERLOGICARBITRATIONLOGICGNT3 GNT3GNT2GNT1GNT0GNT2GNT1GNT0GNT(1..0)CLKCLKCLKLMAS1LMAS0RSTCYC3CYC2CYC1CYC0RST_ICOMCYCLASMASCE 5. RRoouunndd--RRoobbiinn AArrbbiitteerr Bus requests arrive at inputs [ CYC0] to [CYC3] If bus is free, one of the 4 grant lines ([GNT0] to[GNT1]) is asserted which corresponds to therequest signals5 6. Round-RRoobbiinn AArrbbiitteerr:: CCOOMMCCYYCC The [COMCYC] indicates whether the bus is free orbusy It is asserted whenever a master has both requestedthe bus and has been granted the bus by the arbiter6 7. Round-RRoobbiinn AArrbbiitteerr:: CCOOMMCCYYCC Inputs and outputs: COMCYC logic diagram:GNT_3COMCYC = (CYC3 & GNT3)||(CYC2 & GNT2)|| (CYC1 & GNT1)||(CYC0 & GNT0);7Inputs OutputCYC_3, CYC_2, CYC_1, CYC_0GNT_3, GNT_2, GNT_1, GNT_0COMCYCCYC_3CYC_2GNT_2CYC_1GNT_1CYC_0GNT_0COMCYC 8. Round-Robin AArrbbiitteerr:: EEnnccooddeerr LLooggiicc Grant line [GNT0] to [GNT3] are encoded as[GNT(1..0)] This is used with the [COMCYC] signal to indicatewhich master has been granted the bus When [COMCYC] is asserted, the master located on[GNT(1..0)] is granted the bus8 9. Round-Robin AArrbbiitteerr:: EEnnccooddeerr LLooggiicc Inputs and outputs: Encoder logic diagram:9Inputs OutputsGNT_3, GNT_2, GNT_1, GNT_0 GNT[1], GNT[0]GNT_3GNT_1GNT[1] = GNT_2 || GNT_3GNT[0] = GNT3 || GNT1GNT_200000GNT_3 GNT_2 GNT_1 GNT_0 GNT[1] GNT[0]0 0 0 1 0 00 0 1 0 0 10 1 0 0 1 01 0 0 0 1 1 10. Round-RRoobbiinn AArrbbiitteerr:: LLAASSMMAASS Round-robin arbiters keep track of the level of theprevious master The level is saved in a register that latches thestate of grant signals [GNT(1..0)] The register latches the grant signal whenindicated by the LASMAS state machine10CE 11. Round-RRoobbiinn AArrbbiitteerr:: LLAASSMMAASS LASMAS state machine: state diagramState = {EDG,LASMAS} Input logic:Input = BEGBEG= (CYC0 || CYC1 || CYC2 || CYC3) & (~COMCYC); From the state diagram:EDG= ( BEG & ~EDG & LASMAS) || ( BEG & EDG & ~LASMAS );LASMAS = ( BEG & ~EDG & ~LASMAS ); 11CYC0CYC1CYC2CYC3COMCYCBEG 12. Round-Robin AArrbbiitteerr:: BBuuss TTooppoollooggyy The arbitration logic is as below:12MASTER #0MASTER #3MASTER #2MASTER #1 13. Round-Robin AArrbbiitteerr:: BBuuss TTooppoollooggyy The arbitration logic is as below:GNT0 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & ~CYC3 & ~CYC2 & ~CYC1 & CYC0 )|| ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC0 )|| ( ~RST & COMCYC & GNT0 );GNT1 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC1 )|| ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC1 & ~CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC1 & ~CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC1 ~CYC0 )|| ( ~RST & COMCYC & GNT1 );GNT2 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 CYC2 & ~CYC1 )|| ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 CYC2 )|| ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC2 & ~CYC1 & ~CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & LMAS0 CYC2 & ~CYC1 & ~CYC0 )|| ( ~RST & COMCYC & GNT2 );GNT3 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC3 & ~CYC2 & ~CYC1 )|| ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & CYC3 & ~CYC2 )|| ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & CYC3 )|| ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC3 & ~CYC2 & ~CYC1 & ~CYC0 )13MASTER #0MASTER #3MASTER #2MASTER #1 14. Round-Robin AArrbbiitteerr:: BBuuss TTooppoollooggyy The arbitration logic is as below:GNT0 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & ~CYC3 & ~CYC2 & ~CYC1 & CYC0 )|| ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC0 )|| ( ~RST & COMCYC & GNT0 );GNT1 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC1 )|| ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC1 & ~CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC1 & ~CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC1 ~CYC0 )|| ( ~RST & COMCYC & GNT1 );GNT2 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 CYC2 & ~CYC1 )|| ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 CYC2 )|| ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC2 & ~CYC1 & ~CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & LMAS0 CYC2 & ~CYC1 & ~CYC0 )|| ( ~RST & COMCYC & GNT2 );GNT3 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC3 & ~CYC2 & ~CYC1 )|| ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & CYC3 & ~CYC2 )|| ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & CYC3 )|| ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC3 & ~CYC2 & ~CYC1 & ~CYC0 )14MASTER #0MASTER #3MASTER #2MASTER #1 15. Round-Robin AArrbbiitteerr:: BBuuss TTooppoollooggyy The arbitration logic is as below:GNT0 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & ~CYC3 & ~CYC2 & ~CYC1 & CYC0 )|| ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC0 )|| ( ~RST & COMCYC & GNT0 );GNT1 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC1 )|| ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & ~CYC3 & ~CYC2 & CYC1 & ~CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC1 & ~CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC1 ~CYC0 )|| ( ~RST & COMCYC & GNT1 );GNT2 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 CYC2 & ~CYC1 )|| ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 CYC2 )|| ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & ~CYC3 & CYC2 & ~CYC1 & ~CYC0 )|| ( ~RST & ~COMCYC & LMAS1 & LMAS0 CYC2 & ~CYC1 & ~CYC0 )|| ( ~RST & COMCYC & GNT2 );GNT3 = ( ~RST & ~COMCYC & ~LMAS1 & ~LMAS0 & CYC3 & ~CYC2 & ~CYC1 )|| ( ~RST & ~COMCYC & ~LMAS1 & LMAS0 & CYC3 & ~CYC2 )|| ( ~RST & ~COMCYC & LMAS1 & ~LMAS0 & CYC3 )|| ( ~RST & ~COMCYC & LMAS1 & LMAS0 & CYC3 & ~CYC2 & ~CYC1 & ~CYC0 )15MASTER #0MASTER #3MASTER #2MASTER #1 16. RRoouunndd--RRoobbiinn AArrbbiitteerr Code16 17. RRoouunndd--RRoobbiinn AArrbbiitteerr Code:17 18. RRoouunndd--RRoobbiinn AArrbbiitteerr RTL schematic18 19. RRoouunndd--RRoobbiinn AArrbbiitteerr Testbench19 20. Round-RRoobbiinn AArrbbiitteerr:: wwaavveeffoorrmm Cyc0 request and is granted the bus20cyc0 is granted thebus 21. Round-RRoobbiinn AArrbbiitteerr:: wwaavveeffoorrmm Cyc1 and cyc2 both request the bus at the same time21comcyc is negated toindicate that the busis free 22. Round-RRoobbiinn AArrbbiitteerr:: wwaavveeffoorrmm Bus granted to cyc122Bus granted to cyc1because it is next in line 23. Round-RRoobbiinn AArrbbiitteerr:: wwaavveeffoorrmm Cyc3 request for bus and is granted23Bus granted to cyc3