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VLSi design

VLSi designA complete vision of vlsi design styles

Surya Teja Swamy, Vijay VemuriII/IV - B. Tech , ECE,KL University, Guntur.

What is vlsi ?VLSI refers V:VeryL:LargeS:ScaleI:Integrated Circuits

ContVLSI is a process of creating an integrated circuit (IC) by combining thousands of transistors into a single Silicon Chip.Before VLSI there are other design processSSI-10-100MSI-100-1000LSI-1000-20000ULSI-1000000-100lakhsGSI->100lakhs

Examples:SSI = logic gates & FFsMSI = counters,mux,addersLSI = 8-bit micro processors, ROM, RAMVLSI =16 bit & 32 bit micro processorsULSI = special processors, virtual reality machines, GSI = smart sensors3

Moores lawRegarding this IC technology introduced a lawFor every 18 months transistors are doubled.

Moores lawRegarding this IC technology GORDON MOORE introduced a lawFor every 18 months transistors are doubled.

Transistors per Chip


VLSI DesignIn present days all the Electronic Devices are made of using these VLSI CHIPS.These VLSI are designed by CMOS.In Earlier they used several types of active devices.

Active devices : vacuum tubes;diodes;tx(BJT,JFET,MOSFET,CMOS,BICMOS)7

Comparison of available technology

VLSI Design using cmosCMOS ---- C M O S

VLSI Design using cmosCMOS ---- Complementary Metal Oxide Semiconductor

VLSI Design using cmosCMOS ---- Complementary Metal Oxide SemiconductorCombination of PMOS and NMOSThe output of the CMOS is Complement.For getting true value we need to take a Invertor at the output.


CMOS P-well FabricationSteps 1-4

Cont..CMOS P-well inverter showing VDD and VSS Substrate connections

Formation of n-well regionsDefine nMOS and pMOS active areas

Field and Gate Oxidations (thinox)

Form and Pattern Polysilicon

p+ diffusion

n+ diffusion

Contact cuts

Deposit and pattern metallization

Over glass with cuts for bonding pads

Main step in a typical n-well process

Drawbacks of N-well &p-wellIn both N-WELL and P-WELL we may got come across two problems.Body Effect &Latch Up problemTo over come this drawback, we are going for Twin Tub.

BODY EFFECT : increase in Substrate vlge the depletion layer increases twrds substrate. And 4 ltl vgs curr vl b mre at drain.LatchUp : formation of ions b/w well n sub.16

Twin-tub ProcessIt is made with both n-well and p-well region.Epitaxial layer: High purity silicon grown with accurately determined dopant concentrations

CONTAt present the CMOS technologists are using TWIN TUB process.As It is giving effective result.Also it is more efficient.

Drawbacks of cmosCMOS is quite good for all the ELECTRONIC Gadgets.As they required 0-5V voltage.But coming to the ANALOG Equipment's CMOS is poor to use.For that problem we are going to use BICMOS technology.

ANALOG Equipment's loud speakers19

Comparison between CMOS and Bipolar technologies CMOSLow static power dissipationHigh input impedanceHigh noise marginHigh packing densityHigh delay sensitivity to loadLow output drive currentLow gmBidirectional capabilityA near ideal switching deviceScalable threshold voltage

Bipolar technologiesHigh power dissipationLow input impedanceLow voltage swing logicLow packing densityLow delay sensitivity to loadHigh output drive current High gmEssentially unidirectional


BICMOSBICMOS BJT + CMOSAs the drawback of CMOS is output load.At the output of the circuits we use BJT.Entire circuit is designed with CMOS.

Cross sectional viewBi-CMOS(n-p-n Transistor (orbit 2 um CMOS)

n-well BiCMOS fabrication process stepsBICMOSFABRICATIONPROCESS