An assignment on

Design Analog & Mixedmode VLSI Circuits

(EEC 7209)

Analog to Digital Converter

SUBMITTED BY SUBMITTED TO

Anil Kumar Yadav Dr. T. Shanmuganantham

M.Tech(Electronics) Assistance Professor

Department Of Electronics Engineering School Of Engineering and Technology

Pondicherry University

Table of content

Content

Page No

1. Introduction 1

2. Adc Types of adc

1.1 Ramp or stair case or Counter type A/D converter

1.2 Tracking A/D converter

1.3 Successive Approximation A/D Converter

1.4 Flash A/D Converter

1.5 Delta-Sigma A/D Converter

1.6 Dual Slope or integrating type A/D Converter

3

5

6

7

11

15

3. ADC Parameter Specification

3.1 Span (or Range)

3.2 Step Size (or Resolution)

3.3 Resolution

3.4 Quantization Error and Quantization Noise

3.5 Dynamic range

3.6 Signal-to-noise-and-distortion ratio ( SNDR)

3.7 Spurious-free dynamic range (SFDR)

3.8 Total Harmonic Distortion

3.9 Aperture delay

3.10 Transient Response

3.11 Overvoltage Recovery

3.12 Aperture jitter

3.13 Accuracy

3.14 Offset Error

3.15Gain Error

18

19

19

20

21

21

21

21

22

22

22

22

22

22

23

24

3.16Differential Nonlinearity

3.17 Integral Nonlinearity

3 .18 Missing Codes:

25

25

25

4. References

26

ANALOG - DIGITAL CONVERSION

1. INTRODUCTION

An electronic integrated circuit which transforms a signal from analog (continuous) to digital (discrete)

form.The basic principle of operation is to use the comparator principle to determine whether or not to

turn on a particular bit of the binary number output.

The conversion involves quantization of the input, so it necessarily introduces a small amount of error.

Instead of doing a single conversion, an ADC often performs the conversions ("samples" the input)

periodically. The result is a sequence of digital values that have converted a continuous-time and

continuous-amplitude analog signal to a discrete-time and discrete-amplitude digital signal.

ADC are used virtually everywhere where an analog signal has to be processed, stored, or transported in

digital form.

• Some examples of ADC usage are digital volt meters, cell phone, thermocouples, and digital

oscilloscope.

• Microcontrollers commonly use 8, 10, 12, or 16 bit ADCs, our micro controller uses an 8 or 10 bit

ADC.

It is two steps process:

1.Sampling and Holding (S/H)

2.Quantizing and Encoding (Q/E

Sampling and Holding

• The behavior of S/H is analogous to that of camera. its main function is “to capture picture” of

the analog signal and hold its value until the adc can process the information.

• Holding signal benefits the accuracy of the A/D Conversion

• Minimum sampling rate should be at least twice the highest data frequency of the analog signal.

Quantizing:

Partitioning the reference signal range into a number of discrete quanta, then matching the input signal to

the correct quantum.

Encoding:

Assigning a unique digital code to each quantum, then allocating the digital code to the input signal.

Speed: Rate of conversion of a single digital input to its analog equivalent.

Conversion Rate

Depends on clock speed of input signal

Depends on settling time of converter

Types of A/D Converters

1. Ramp or stair case or counter type A/D converter

2. Tracking A/D converter

3. Successive Approximation A/D Converter

4. Flash A/D Converter

5. Delta-Sigma A/D Converter

6. Dual Slope or integrating type A/D Converter

2.1 Counter type

One of the simplest types of analog to digital converter is counter type ADC. The basic idea is to connect

the output of a free-running binary counter to the input of a DAC, then compare the analog output of the

DAC with the analog input signal to be digitized and use the comparator’s output to tell the counter when

to stop counting and reset. Thefollowing schematic shows the basic idea:

Counter type contains the following elements:

Digital to analog converter

Some type of counting mechanism

Comparator

clock

The input signal of ADC is connected to the signal input of its internal comparator.

The ADC then systematically increases the voltage of the reference input of the comparator until

the reference becomes larger than the signal.

And the comparator output goes to 0

Block diagram:

Operation :

consider an input signal is 4.78 volts. The initial comparator’s input would be 2.5 volts

The comparator compares the two value then the result this is less than 4.78 then the next higher

voltage (5.00 volts) is applied

The comparator compares the two value and says this is greater than 4.78 and switches 0

The digital output of the ADC is the number of times the ADC increase the voltage after starting

at the initial 2.5 volts

This scheme is relatively simple , but as the number of ADC increases the time it takes to scan

through all possible values lower than input will grow quickly

The conversion time on the counter type is NOT fixed but depends on the actual value of the

analogue input expressed as a fraction of the full scale.

This can be expressed as :-

Where N is the number of bits and T is the time period of the clock pulse .

Example: 1 A counter type ADC has the following parameters, N=8, Vref=5.1V and

clock=1MHz. Find the digital word for an Vin of 4.36V and the conversion time taken to reach

this value?

Solution:

Step size = 5.1v / 2^N = 5.1V / 256 = 0.0199=0.02

The number of steps = 4.36 / 0.02 = 218.1=219

(219)10 = 110110112

Conversion time = 219 x 1/1MHz = 219 x 1uS = 219 uS

Features of counter type:

Use a clock to index the counter

Use DAC to generate analog signal to compare against input

Comparator is used to compare VIN and VDAC where VIN is the signal to be digitized

The input to the DAC is from the counter

2.2 Tracking ADC

Tracking ADC - similar to the counter type except it uses an up/down counter and can track a varying

signal more quickly.

Track A/D Converter

2.3 Flash A/D Converter

Flash adc is fastest in all adc because flash type adc is uses combinational logic (not sequential logic ).

Therefore, clock is not required, in case of flash type adc.

If propagation delay time of combinational circuit is zero, then ideal conversion time of adc is

zero. But practical conversion time is sum of all propagation delay of combinational circuit

involve in flash type ADC.

Uses the 2^n resistors to form a ladder voltage divider, which divides the reference voltage into

2^n equal intervals.

Uses the 2^n-1 comparators to determine in which of these 2^n voltage intervals the input voltage

Vin lies.

The Combinational logic then translates the information provided by the output of the

comparators

This ADC does not require a clock so the conversion time is essentially set by the settling time of

the comparators and the propagation time of the combinational logic.

Fundamental Components (For n bit Flash A/D)

a) 2^n-1 Comparators

b) 2^n Resistors

c) Control Logic

Block diagram:

Operation:

1. A resistive voltage divider (see figure) can provide all the digital reference states required. There

are eight reference values for the 3-bit converter.

2. The analog signal is compared concurrently with each reference state; therefore a separate

comparator is required for each comparison.

3. Digital logic then combines the several comparator outputs to determine the appropriate binary

code to present.

4. The reference voltages are set to 0.5, 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 volts respectively. The

comparator outputs are labeled correspondingly as 1, 2, 3, 4, 5, 6, and 7 respectively.

Advantage

i. Very Fast (Fastest)

ii. Very simple operational theory

iii. Speed is only limited by gate and comparator propagation delay

Disadvantage

i. Expensive

ii. Prone to produce glitches in the output

iii. Each additional bit of resolution requires twice the comparators

2.4 Delta-Sigma (∆Σ) ADC

One of the more advanced ADC technologies is the so-called delta-sigma, or ∆Σ (using the

proper Greek letter notation). In mathematics and physics, the capital Greek letter delta (∆)

represents difference or change, while the capital letter sigma (Σ) represents summation: the

adding of multiple terms together. Sometimes this converter is referred to by the same Greek

letters in reverse order: sigma-delta, or Σ∆.

In a ∆Σ converter, the analog input voltage signal is connected to the input of an integrator,

producing a voltage rate-of-change, or slope, at the output corresponding to input magnitude.

This ramping voltage is then compared against ground potential (0 volts) by a comparator. The

comparator acts as a sort of 1-bit ADC, producing 1 bit of output (”high” or ”low”) depending on

whether the integrator output is positive or negative. The comparator’s output is then latched

through a D-type flip-flop clocked at a high frequency, and fed back to another input channel

on the integrator, to drive the integrator in the direction of a 0 volt output. The basic circuit

is shown in B/D:

Block Diagram:

The leftmost op-amp is the (summing) integrator. The next op-amp the integrator feeds into

is the comparator, or 1-bit ADC. Next comes the D-type flip-flop, which latches the comparator’s

output at every clock pulse, sending either a ”high” or ”low” signal to the next comparator at the top

of the circuit. This final comparator is necessary to convert the single-polarity 0V / 5V logic level

output voltage of the flip-flop into a +V / -V voltage signal to be fed back to the integrator.

If the integrator output is positive, the first comparator will output a ”high” signal to the

D input of the flip-flop. At the next clock pulse, this ”high” signal will be output from the Q

line into the noninverting input of the last comparator. This last comparator, seeing an input

voltage greater than the threshold voltage of 1/2 +V, saturates in a positive direction, sending a full

+V signal to the other input of the integrator. This +V feedback signal tends to drive

the integrator output in a negative direction. If that output voltage ever becomes negative, the

feedback loop will send a corrective signal (-V) back around to the top input of the integrator to drive

it in a positive direction. This is the delta-sigma concept in action: the first comparator senses a

difference (∆) between the integrator output and zero volts. The integrator sums (Σ) the comparator’s

output with the analog input signal.

Functionally, this results in a serial stream of bits output by the flip-flop. If the analog input

is zero volts, the integrator will have no tendency to ramp either positive or negative, except in

response to the feedback voltage. In this scenario, the flip-flop output will continually oscillate

between ”high” and ”low,” as the feedback system ”hunts” back and forth, trying to maintain the

integrator output at zero volts:

If, however, we apply a negative analog input voltage, the integrator will have a tendency

to ramp its output in a positive direction. Feedback can only add to the integrator’s ramping

by a fixed voltage over a fixed time, and so the bit stream output by the flip-flop will not be

quite the same:

By applying a larger (negative) analog input signal to the integrator, we force its output to

ramp more steeply in the positive direction. Thus, the feedback system has to output more 1’s

than before to bring the integrator output back to zero volts:

\

As the analog input signal increases in magnitude, so does the occurrence of 1’s in the

digital output of the flip-flop:

A parallel binary number output is obtained from this circuit by averaging the serial stream of bits

together. For example, a counter circuit could be designed to collect the total number of 1’s output

by the flip-flop in a given number of clock pulses. This count would then be indicative of the

analog input voltage.

Variations on this theme exist, employing multiple integrator stages and/or comparator

circuits outputting more than 1 bit, but one concept common to all ∆Σ converters is that of

oversampling. Oversampling is when multiple samples of an analog signal are taken by an ADC

(in this case, a 1-bit ADC), and those digitized samples are averaged. The end result is an

effective increase in the number of bits resolved from the signal. In other words, an oversampled

1-bit ADC can do the same job as an 8-bit ADC with one-time sampling, albeit at a slower rate.

Advantage

High Resolution

No need for precision Components

Disadvantage

Slow due to oversampling

Only good for low bandwidth

2.5 Successive Approximation ADC Circuit

One method of addressing the digital ramp ADC's shortcomings is the so-called successive-

approximation ADC. The only change in this design is a very special counter circuit known as

a successive-approximation register. Instead of counting up in binary sequence, this register counts by

trying all values of bits starting with the most-significant bit and finishing at the least-significant bit.

Throughout the count process, the register monitors the comparator's output to see if the binary count is

less than or greater than the analog signal input, adjusting the bit values accordingly. The way the register

counts is identical to the "trial-and-fit" method of decimal-to-binary conversion, whereby different values

of bits are tried from MSB to LSB to get a binary number that equals the original decimal number. The

advantage to this counting strategy is much faster results: the DAC output converges on the analog signal

input in much larger steps than with the 0-to-full count sequence of a regular counter.

Uses a n-bit DAC to compare DAC and original analog results.

Uses Successive Approximation Register (SAR) supplies an approximate digital code to DAC of

Vin.

Comparison changes digital output to bring it closer to the input value.

Uses Closed-Loop Feedback Conversion

Block diagram:

Process

1. MSB initialized as 1

2. Convert digital value to analog using DAC

3. Compares guess to analog input

4. Is Vin>VDAC

• Set bit 1

• If no, bit is 0 and test next bit

Advantage

Capable of high speed and reliable

Medium accuracy compared to other ADC

Good tradeoff between speed and cost

Capable of outputting the binary number in serial (one bit at a time) format.

Disadvantage

Higher resolution

slower

Speed limited to ~5Msps

Example: 1 In 10 bit ADC,Vin= 0.6 volts (from analog device),Vref=1 volts .Find the digital value of

Vin?

Solution

• N=2^n =1024

• Vmax-Vmin/N = 1 Volt/1024 =0.0009765625V of Vref (resolution)

MSB (bit 9)

Divided Vref by 2

Compare Vref /2 with Vin

If Vin >Vref /2 , turn MSB on (1)

If Vin < Vref /2 , turn MSB off (0)

Vin =0.6V and V=0.5

Since Vin>V, MSB = 1 (on)

Next Calculate MSB-1 (bit 8)

Compare Vin=0.6 V to V=Vref/2 + Vref/4= 0.5+0.25 =0.75V

Since 0.6<0.75, MSB is turned off.

Calculate MSB-2 (bit 7)

Go back to the last voltage that caused it to be turned on (Bit 9) and add it to Vref/8, and

compare with Vin.

Compare Vin with (0.5+Vref/8)=0.625

Since 0.6<0.625, MSB is turned off

Calculate the state of MSB-3 (bit 6)

Go to the last bit that caused it to be turned on (in this case MSB-1) and add it to Vref/16, and compare

it to Vin.

Compare Vin to V= 0.5 + Vref/16= 0.5625

Since 0.6>0.5625, MSB-3=1 (turned on)

This process continues for all the remaining bits.

2.6 Dual Slope A/D Converter

A popular method for converting an analog voltage into a digital value is the dualslope

method. Figure shows a block diagram of the basic dual-slope converter.

The analog voltage to be converted is applied through an electronic switch to an integrator

or ramp-generator circuit (essentially a constant current charging a capacitor

to produce a linear ramp voltage). The digital output is obtained from a counter operated

during both positive and negative slope intervals of the integrator.

Fundamental components

1. integrator

2. Electronically Controlled Switches

3. Counter

4. Clock

5. Control Logic

6. Comparator

Block Diagram:

The method of conversion proceeds as follows. For a fixed time interval (usually the full count range of

the counter), the analog voltage connected to the integrator raises the voltage at the comparator input to

some positive level. Figure shows that at the end of the fixed time interval the voltage from the integrator

is greater for the larger input voltage. At the end of the fixed count interval, the count is set to zero and

the electronic switch connects the integrator to a reference or fixed input voltage.

The integrator output (or capacitor input) then decreases at a fixed rate. The counter advances during this

time, while the integrator’s output decreases at a fixed rate until it drops below the comparator reference

voltage, at which time the control logic receives a signal (the comparator output) to stop the count. The

digital value stored in the counter is then the digital output of the converter.

Using the same clock and integrator to perform the conversion during positive and negative slope

intervals tends to compensate for clock frequency drift and integrator accuracy limitations. Setting the

reference input value and clock rate can scale the counter output as desired. The counter can be a binary,

BCD, or other form of digital counter, if desired.

Advantage

• Conversion result is insensitive to errors in the component values.

• Fewer adverse affects from “noise”

• High Accuracy

Disadvantages

• Slow

• Accuracy is dependent on the use of precision external components

• Cost

Example 1

• A 10-bit digital slope integrating A/D converter has a full-scale input of 10V. If the clock period

is 15 μS, how long will it take to convert an input of 4V? How long for an input of 10V?

Solution:

10 bits means 210 =1024 levels.

Full scale input of 10V means each level is 10V/1024=9.77mV

4V corresponds to 4/9.7710-3=409.6 - round up to 410

A clock period of 15μs mean 4V will take 15μs410 =6.15ms

10V will take 15μs1024=15.36ms

Example 2

• A 10-bit digital slope integrating A/D converter has a full-scale input of 10V. If the clock period

is 15 μS, how long will it take to convert an input of 4V? How long for an input of 10V?

Solution:

10V will take 15μs1024=15.36ms

Example 3:

What increase in speed can be gained by using a 12-bit successive approximation converter instead of the

digital slope converter, assuming a full-scale input voltage.?

Solution:

• A 12-bit SA converter will take 12 clock cycles = 180 μs, regardless of the input voltage

• so for 10V full scale input, the speed increase is 15.36ms/180 μs =85.3 times.

• So the SA converter is both faster and more accurate (12 bits gives 4096 levels, compared to

1024 levels for 10 bit)

3. ADC Parameter Specification

3.1 Span (or Range): difference between maximum and minimum analog values.

Span= maximum value – minimum value

Some common spans:

range of 0 V to 5 V: span = 5 V

range of –12 V to 12 V: span = 24 V

range of 4 mA to 20 mA: span = 16 mA

Offset: minimum analog value

Bit Weight: analog value corresponding to a bit in the digital number

3.2 Step Size (or Resolution): smallest analog change resulting from changing one bit in the digital

number, or the analog difference between two consecutive digital numbers.

Let AV be Analog Value; DN be Digital Number:

AV = DN × Step Size + Offset = (DN / 2n )× Span + Offset

DN = (AV - Offset) / Step Size = (AV - Offset) × 2n / Span

3.3 Resolution:

The smallest change in analog signal that will result in change in digital output .

Where V=reference voltage range

N= Number of bits in digital output.

2^N= Number of states.

ΔV=resolution.

Example 1

o Full scale measurement range = 0 to 10 volts

o ADC resolution is 12 bits = 4096 quantization levels (codes)

o ADC voltage resolution is =(10V - 0V) / 4096 codes = 10V /4096 codes

=0.00244 volts/code = 2.44 mV/code

• Example 2

o Full scale measurement range = -10 to +10 volts

o ADC resolution is 14 bits: =16384 quantization levels (codes)

o ADC voltage resolution is: =(10V - (-10V)) / 16384 codes

=20V / 16384 codes=0.00122 volts/code

= 1.22 mV/code

3.4 Quantization Error and Quantization Noise :

Quantization error occur due to the finite resolution N of the A/D converter limits the signal-to-noise

ratio.

All inputs within ±1/2 LSB of a code center resolve to that digital code. Thus, there will be a small

difference between the code center and the actual input voltage due to this quantization.

Mathematically,

Qe=Vin-Vstaircase, where Vstaircase=D*VQ ,VQ => Quantam volatge level

If assume that this error voltage is uncorrelated and distributed uniformly, we can calculate the expected

rms value of this quantization noise.“

Quantum voltage level=

Expectation value of the error voltage =

The rms value of a full-scale peak-to-peak amplitude VF is:

thus the signal-to-noise ratio is =

SNR= 6.02N + 1.76 dB

3.5 Dynamic range :

is the ratio of the smallest possible output (the least significant bit or quantum voltage) to

the largest possible output (full-scale voltage).

`Mathematically : DR =20 log10 2^N = 6N.

3.6 Signal-to-noise-and-distortion ratio ( SNDR) : is the ratio of the input signal amplitude to the

rms sum of all other spectral components.

SNDR =S/N+D

3.7 Spurious-free dynamic range (SFDR): is the ratio of the input signal to the peak spurious or

peak harmonic component.

Spurs can be created at harmonics of the input frequency due to nonlinear- ties in the A/D converter, or at

sub harmonics of the sampling frequency due to mismatch or clock coupling in the circuit.

The SFDR of an A/D converter can be larger than the SNDR.

3.8 Total Harmonic Distortion:

Total harmonic distortion (THD) is the ratio of the rms sum of the first 5 harmonic components to

the input signal.

where V1 is the amplitude of the fundamental, and Vn is the amplitude of the n-th harmonic.

3.9 Aperture delay :

Aperture delay is the delay from when the A/D converter is triggered (perhaps the rising edge of

the sampling clock) to when it actually converts the input voltage into the appropriate digital code.

Aperture delay is also sometimes called aperture time.

3.10 Transient Response:

Transient response is the settling time for the A/D converter to full accuracy (to within ±1/2 LSB)

after a step in input voltage from zero to full scale.

3.11 Overvoltage Recovery:

Overvoltage recovery is the settling time for the A/D converter to full accuracy after a step in

input voltage from outside the full scale voltage (for example, from 1:5VF to 0:5VF )

3.12 Aperture jitter:

Aperture jitter is the sample-to-sample variation in the aperture delay. The rms voltage error

caused by rms aperture jitter decreases the overall signal-to-noise ratio, and is a significant

limiting factor in the performance of high-speed A/D converters.

If we assume that the input waveform is a sinusoid ,then , VIN = VFS sin ᾡt

then the maximum slope of the input waveform is:

which occurs at the zero crossings.

If there is an rms error in the time at which we sample (aperture jitter, ta) during this maximum

slope.

then ,there will be an rms voltage error of

Since the aperture time variations are random these voltage errors will behave like a random

Noise source.

Thus the signal-to-jitter-noise ratio :

3.12 Accuracy

Accuracy is the total error with which the A/D converter can convert a known voltage, including

the effects of quantization error, gain error, offset error, and nonlinearities.

There are two ways to best improve the accuracy of A/D conversion:

• increasing the resolution which improves the accuracy in measuring the amplitude of the analog

signal.

• increasing the sampling rate which increases the maximum frequency that can be measured.

3.13 Offset Error

Offset error is the deviation in the A/D converter's behavior at zero. The first transition voltage

should be 1/2 LSB above analog ground. Offset error is the deviation of the actual transition

voltage from the ideal 1/2 LSB.

Offset error is easily trimmed by calibration. Compare the location of the first transitions in

Figures 1 and 2.

3.14 Gain Error

Gain error is the deviation in the slope of the line through the A/D converter's end points at zero

and full scale from the ideal slope of 2^N/VFS codes-per-volt. Like offset error, gain error is

easily corrected by calibration. Compare the slope of the dashed lines in Figures 1 and 2.

3.15 Differential Nonlinearity

Differential nonlinearity (DNL) is the deviation of the code transition widths from the ideal width

of 1 LSB i.e. difference b/w the actual code width of nonideal converter and the ideal case.

Mathematically, DNL=actual step width - ideal step width

ideal step width=Vref/8=.625V=1 LSB

All code widths in the ideal A/D converter are 1 LSB wide, so the DNL would be zero

everywhere.

3.16 Integral Nonlinearity

Integral nonlinearity (INL) is the distance of the code centers in the A/D converter characteristic

from the ideal line.

If all code centers land on the ideal line, the INL is zero everywhere.

See the deviations of the code centers from the ideal line in Figure .

3.18 Missing Codes: Missing codes are output digital codes that are not produced for any

input voltage, usually due to large DNL.

In some converters, missing codes can be caused by non-monotonicity of the internal D/A.

The large DNL in Figure 3 causes code 100 to be “crowded out.”

3. References

• C-mos Circuit Design, layout and simulation- By R.Jacob baker, chapter no. 28,29.

• Fundamentals of Digital Circuits By - A. Anand Kumar

• LINEAR INTEGRATED CIRCUIT By: D. ROY CHOUDHARY

• http://elearning.vtu.ac.in

• http://web.mit.edu/klund/www/papers/

• http://www.freescale.com/files/microcontrollers/doc/app_note/AN2438.pdf