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NEXGEN TECHNOLOGY
www.nexgenproject.com
VLSI PROJECTS 2015- 2016Sno. CODE Topic YEAR
1. VLSI2016_01A Low-Cost Low-Power All-Digital Spread-Spectrum
Clock Generator2015-2016
2. VLSI2016_02A Combined SDC-SDF Architecture for Normal I/O
Pipelined Radix-2 FFT2015-2016
3. VLSI2016_03A Class of SEC-DED-DAEC Codes Derived From
Orthogonal Latin Square Codes2015-2016
4. VLSI2016_04Design of Efficient Content Addressable Memories in
High-Performance FinFET Technology2015-2016
5. VLSI2016_05
A New Efficiency-Improvement Low-RippleCharge-Pump Boost Converter Using Adaptive
Slope Generator With Hysteresis VoltageComparison Techniques
2015-2016
6. VLSI2016_06A 0.25-V 28-nW 58-dB Dynamic RangeAsynchronous Delta Sigma Modulator
in 130-nm Digital CMOS Process2015-2016
7. VLSI2016_07Range Unlimited Delay-Interleaving and -Recycling
Clock Skew Compensation and Duty-CycleCorrection Circuit
2015-2016
8. VLSI2016_08Obfuscating DSP Circuits via High-Level
Transformations2015-2016
9. VLSI2016_09Accelerating Scalar Conversion for Koblitz Curve
Cryptoprocessors on Hardware Platforms2015-2016
10. VLSI2016_10Design of Self-Timed Reconfigurable Controllers
for Parallel Synchronization via Wagging2015-2016
11. VLSI2016_11Level-Converting Retention Flip-Flop for Reducing
Standby Power in ZigBee SoCs2015-2016
12. VLSI2016_12All Digital Energy Sensing for
Minimum Energy Tracking2015-2016
13. VLSI2016_13Recursive Approach to the Design of a
Parallel Self-Timed Adder2015-2016
14. VLSI2016_14Novel Reconfigurable Hardware Architecture for
Polynomial Matrix Multiplications2015-2016
15. VLSI2016_15Implementation of Subthreshold Adiabatic
Logic for Ultralow-Power Application2015-2016
16. VLSI2016_16FPGA-Based Bit Error Rate Performance
Measurement of Wireless Systems2015-2016
No: 66,4th cross, Venkata nagar, Near SBI ATM, Pondicherry. Email Id: [email protected]
Mobile: 9751442511, 9791938249, Telephone: 0413-2211159
NEXGEN TECHNOLOGY
www.nexgenproject.com
17. VLSI2016_17Algorithm and Architecture Design of the
H.265/HEVC Intra Encoder2015-2016
18. VLSI2016_18Pre-Encoded Multipliers
Based on Non-Redundant Radix-4Signed-Digit Encoding
2015-2016
19. VLSI2016_19A High-Performance FIR Filter Architecture for
Fixed and Reconfigurable Applications2015-2016
20. VLSI2016_20A Novel Photosensitive Tunneling Transistor
for Near-Infrared Sensing Applications:Design, Modeling, and Simulation
2015-2016
21. VLSI2016_21High-Throughput LDPC-Decoder Architecture
Using Efficient Comparison Techniques & DynamicMulti-Frame Processing Schedule
2015-2016
22. VLSI2016_22A New Parallel VLSI Architecture for Real-time
Electrical Capacitance Tomography2015-2016
23. VLSI2016_23Graph-Based Transistor Network Generation
Method for Supergate Design2015-2016
24. VLSI2016_24A Relative Imaging CMOS Image Sensor for High
Dynamic Range and High Frame-Rate MachineVision Imaging Applications
2015-2016
25. VLSI2016_25Low-Cost High-Performance VLSI Architecture for
Montgomery Modular Multiplication2015-2016
26. VLSI2016_26Fully Pipelined Low-Cost and High-Quality ColorDemosaicking VLSI Design for Real-Time Video
Applications2015-2016
27. VLSI2016_27A Novel Area-Efficient VLSI Architecture for
Recursion Computation in LTE Turbo Decoders2015-2016
28. VLSI2016_28
Comparative Performance Analysis ofthe Dielectrically Modulated FullGate and Short-Gate
TunnelFET-Based Biosensors
2015-2016
29. VLSI2016_29
An Efficient Constant Multiplier ArchitectureBased on Vertical-Horizontal Binary Common
Sub-expression Elimination Algorithm forReconfigurable FIR Filter Synthesis
2015-2016
30. VLSI2016_30VLSI-Assisted Nonrigid Registration Using
Modified Demons Algorithm2015-2016
31. VLSI2016_31 Fine-Grained Access Management inReconfigurable Scan Networks
2015-2016
No: 66,4th cross, Venkata nagar, Near SBI ATM, Pondicherry. Email Id: [email protected]
Mobile: 9751442511, 9791938249, Telephone: 0413-2211159
NEXGEN TECHNOLOGY
www.nexgenproject.com
32. VLSI2016_32A High-Throughput VLSI Architecture for Hard and
Soft SC-FDMA MIMO Detectors2015-2016
33. VLSI2016_33Partially Parallel Encoder Architecture
for Long Polar Codes2015-2016
34. VLSI2016_34Novel Block-Formulation and Area-Delay-EfficientReconfigurable Interpolation Filter Architecture for
Multi-Standard SDR Applications2015-2016
35. VLSI2016_35One Minimum Only Trellis Decoder for Non-Binary
Low-Density Parity-Check Codes2015-2016
36. VLSI2016_36A Low-Cost Hardware Architecture for Illumination
Adjustment in Real-Time Applications2015-2016
37. VLSI2016_37A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data
RecoveryCircuit With 4× Oversampling
2015-2016
38. VLSI2016_38Aging-Aware Reliable Multiplier Design With
Adaptive Hold Logic2015-2016
39. VLSI2016_39Reverse Converter Design via Parallel-Prefix Adders:
Novel Components,Methodology, and Implementations
2015-2016
40. VLSI2016_40Fully Reused VLSI Architecture of
FM0/Manchester Encoding Using SOLSTechnique for DSRC Applications
2015-2016
41 VLSI2016_41A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the
Successive-Approximation Register2015-2016
42 VLSI2016_42A Fully Digital Front-End Architecture for ECG
Acquisition System With 0.5 V Supply2015-2016
43 VLSI2016_43A Low-Power Robust Easily CascadedPentaMTJ-
Based Combinational and Sequential Circuits2015-2016
44 VLSI2016_44A Mixed-Decimation MDF Architecture for Radix-
2k Parallel FFT2015-2016
45 VLSI2016_45A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-Mw
Current-Steering DAC in 0.038 mm22015-2016
46 VLSI2016_46Argo: A Real-Time Network-on-Chip Architecture
With an Efficient GALS Implementation2015-2016
47 VLSI2016_47Design and Low-Complexity Implementation of
Matrix–Vector Multiplier for Iterative Methods in Communication Systems
2015-2016
48 VLSI2016_48 Energy and Area Efficient Three-Input XOR/XN 2015-2016
No: 66,4th cross, Venkata nagar, Near SBI ATM, Pondicherry. Email Id: [email protected]
Mobile: 9751442511, 9791938249, Telephone: 0413-2211159
NEXGEN TECHNOLOGY
www.nexgenproject.com
ORs With Systematic Cell Design Methodology
49 VLSI2016_49Fault Tolerant Parallel FFTs Using Error Correction
Codes and Parseval Checks2015-2016
50 VLSI2016_50Graph-Based Transistor Network Generation Method
for Supergate Design2015-2016
51 VLSI2016_51High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage
Levels2015-2016
52 VLSI2016_52High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC
Video Encoding2015-2016
53 VLSI2016_53A Spread Spectrum Clock Generator Using a
Programmable Linear Frequency Modulator for Multipurpose Electronic Devices
2015-2016
54 VLSI2016_54Floating-Point Butterfly Architecture Based on Binary
Signed-Digit Representation2015-2016
55 VLSI2016_55 Further Desensitized FIR Halfband Filters 2015-2016
56 VLSI2016_56A Modified Partial Product Generator for Redundant
Binary Multipliers2015-2016
57 VLSI2016_57Implementation of Arithmetic Operations with Time-
free Spiking Neural P Systems2015-2016
58 VLSI2016_58A Clock and Data Recovery Circuit With
Programmable Multi-Level Phase Detector Characteristics and a Built-in Jitter Monitor
2015-2016
59 VLSI2016_59Unfaithful Glitch Propagation in Existing Binary
Circuit Models2015-2016
60 VLSI2016_60Early Skip Mode Decision for HEVC Encoder With
Emphasis on Coding Quality2015-2016
61 VLSI2016_61Two-Step Optimization Approach for the Design of
Multiplierless Linear-Phase FIR Filters2015-2016
62 VLSI2016_62 Energy Consumption of VLSI Decoders 2015-2016
63 VLSI2016_63Timing Error Tolerance in Small Core Designs for SoC
Applications2015-2016
64 VLSI2016_6440-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with
Transformer-Coupled Technique for SerDes Interface2015-2016
65 VLSI2016_65 Design and Analysis of Inexact Floating-Point Adders 2015-2016
66 VLSI2016_66In-Field Test for Permanent Faults in FIFO Buffers of
NoC Routers 2015-2016
67 VLSI2016_67 Low-Cost High-Performance VLSI Architecture for 2015-2016
No: 66,4th cross, Venkata nagar, Near SBI ATM, Pondicherry. Email Id: [email protected]
Mobile: 9751442511, 9791938249, Telephone: 0413-2211159
NEXGEN TECHNOLOGY
www.nexgenproject.com
Montgomery ModularMultiplication
68 VLSI2016_68High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage
Levels2015-2016
69 VLSI2016_69Dual-Phase Tapped-Delay-Line Time-to-Digital
Converter With On-the-Fly Calibration Implemented in 40 nm FPGA
2015-2016
70 VLSI2016_70A Low Power and High Sensing Margin Non-Volatile
Full Adder Using Racetrack Memory2015-2016
71 VLSI2016_71Signal Design for Multiple Antenna Systems With Spatial Multiplexing and Noncoherent Reception
2015-2016
72 VLSI2016_72Synthesis of Genetic Clock with Combinational
Biologic Circuits2015-2016
73 VLSI2016_73Aging-Aware Reliable Multiplier Design With
Adaptive Hold Logic2015-2016
74 VLSI2016_74Fault Tolerant Parallel Filters Based on Error
Correction Codes2015-2016
75 VLSI2016_75Design and Analysis of Approximate Compressors for
Multiplication2015-2016
76 VLSI2016_76Novel Design Algorithm for Low Complexity
Programmable FIR Filters Based on Extended Double Base Number Systems
2015-2016
77 VLSI2016_77An Accuracy-Adjustment Fixed-Width Booth
Multiplier Based on Multilevel Conditional Probability2015-2016
78 VLSI2016_78Floating-Point Butterfly Architecture Based on Binary
Signed-Digit Representation2015-2016
79 VLSI2016_79Implementation of Subthreshold Adiabatic Logic for
Ultralow-Power Application2015-2016
80 VLSI2016_80Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for
Multi-Standard SDR Applications2015-2016
81 VLSI2016_81A High-Performance FIR Filter Architecture for Fixed
and Reconfigurable Applications2015-2016
82 VLSI2016_82High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage
Levels2015-2016
83 VLSI2016_83Low-Power and Area-Efficient Shift Register Using
Pulsed Latches2015-2016
84 VLSI2016_84 Array-Based Approximate Arithmetic Computing: A 2015-2016
No: 66,4th cross, Venkata nagar, Near SBI ATM, Pondicherry. Email Id: [email protected]
Mobile: 9751442511, 9791938249, Telephone: 0413-2211159
NEXGEN TECHNOLOGY
www.nexgenproject.com
General Model and Applications to Multiplier and Squarer Design
85 VLSI2016_85Recursive Approach to the Design of a Parallel Self-
Timed Adder 2015-2016
86 VLSI2016_86 Further Desensitized FIR Half band Filters 2015-201687 VLSI2016_87 Design and Analysis of Inexact Floating-Point Adder 2015-2016
88 VLSI2016_88Scalable Verification of a Generic End-Around-Carry
Adder for Floating-Point Units by Coq2015-2016
89 VLSI2016_89
An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter
Synthesis
2015-2016
90 VLSI2016_90A Generalized Algorithm and Reconfigurable
Architecture for Efficient and Scalable Orthogonal Approximation of DCT
2015-2016
No: 66,4th cross, Venkata nagar, Near SBI ATM, Pondicherry. Email Id: [email protected]
Mobile: 9751442511, 9791938249, Telephone: 0413-2211159
