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Logic Design - Chapter 6: Flip Flops

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Text of Logic Design - Chapter 6: Flip Flops

  • 1. Sequential Logic and Flip-Flops

2. SEQUENTIAL CIRCUITS AND FEEDBACK 3. SET- RESET (S-R) LATCHES : Cross- NOR S-R latch ( active high ) Cross- NAND S-R latch ( active low ) 4. Cross-NOR S-R latch ( active high ) 5. truth table of the NOR gate AB(A + B)001010100110if any of the inputs of the NOR gate is high (logic 1), the output is low (logic 0) 6. No-Change condition in S-R latch 7. Forbidden condition in S-R latch 8. function table of the NOR S-R latch RSQQComments00QQ0110No change ( hold ) condition Set1001Reset1100Forbidden, Not used , race 9. the race situation If we go from SR = 11 to SR = 00, then we may have two cases. Case 1: R changes first: SR = 10 then SR = 00 Case 2: S changes first: SR = 01 then SR = 001 1 0 10. Cross- NAND S-R latch ( active low ) S-R The truth table of NAND gate 11. Functions table of the NAND latch . 12. S R Timing Analysis 13. EXAMPLE If the S and R waveforms shown in Fig (11.a) are applied to the inputs of the NOR latch, determine the waveform that will be applied on the Q output. Assume that Q is initially low. 14. Switch Debouncing Circuits Switch bounce occurs as a mechanical switch lever snaps to a new position. After reaching the new contact point, the pole bounces on a micrometer scale of millisecond duration (Fig (12)). Bounce can cause problems in circuits that are expecting an input to stabilize without oscillating, such as counters. 15. Debouncing using S-R latch When the switch is neither connected to the lower pin nor to the upper pin, both S and R equal + 5v ( Logic 1 ) and the latch is in the no change state . 16. Debouncing using S-R latch (cont.) 17. Clocked SR latches ( flip flops ) 18. clocked (gated) latch using cross NAND gates 19. Function table of gated S-R flip flop 20. EXAMPLE Determine the Q output waveform if the inputs shown in Fig (17-a) are applied to a clocked (gated) S-R latch that is initially RESET. 21. GATED D- latch 22. EXAMPLE Sketch the output waveform at Q for the inputs at D and G of the gated D latch in Fig (20). 23. EXAMPLE Construct a D flip-flop using NOR and AND gates. 24. JK FLIP FLOPS 25. JK FLIP FLOPS 26. T. (TOGGLE) FLIPFLOP 27. Race problem in level-clocked J-K flip-flop 28. Clock edge and level edge triggered FFs Master slave FFs . 29. MASTER SLAVE FLIP-FLOPS 30. Timing diagram of a master-slave FF 31. EDGE TRIGGERED J K FFS+ve edge triggered-ve edge triggered 32. EXAMPLE Determine the Q output waveform if the inputs shown in Fig (32) are applied to a clocked S-R flip-flop that is initially RESET. The flip-flop is triggered at the positive edge. 33. MASTER-SLAVE FLIP-FLOP AND 1S CATCHING 34. DIRECT ( ASYNCHRONOUS ) INPUTS 35. FLIP- FLOP OPERATING CHARACTERISTICS Propagation Delay times: SET-UP TIME HOLD TIME 36. Propagation Delay times: 37. Propagation Delay times: 38. SET-UP TIME 39. HOLD TIME

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