Easy Learn to Verilog HDL

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Verilog Course Book

Text of Easy Learn to Verilog HDL

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2. VLSI DESIGN Reference MaterialBy Verilog Course Team Where Technology and Creativity Meet 3. Contact UsVERILOG COURSE TEAMEmail:info@verilogcourseteam.comBlog: www.vlsiprojects.blogspot.comWeb: www.verilogcourseteam.comPhone: +91 98942 20795Revision: 1For hardcopies drop a mail or contact us.Disclaimer:Due care and diligence has been taken while editing of this material. VerilogCourse Team does not warrant or assume any legal liability or responsibilityfor the accuracy, completeness, or usefulness of any information, apparatus,product, or process disclosed. No warranty of any kind, implied, expressed orstatutory, including to fitness for a particular purpose and freedom fromcomputer virus, is given with respect to the contents of this material or itshyperlinks to other Internet resources. The material acts as just a reference tomove forward and understand the concept. Reference in this material to anyspecific commercial products, processes, or services, or the use of any trade,firm or corporation name is for the information, and does not constituteendorsement, recommendation, or favoring. 4. About Verilog Course TeamVerilog Course Team is a Electronic Design Services (EDS) for VLSI /EMBEDDED and MATLAB, delivering a wide variety of end-to-end services ,including design , development, & testing for customers around the world .Withproven expertise across multiple domains such as Consumer Electronics Market,Infotainment, Office Automation, Mobility and Equipment Controls. Verilog CourseTeam is managed by Engineers / Professionals possessing significant industrialexperience across various application domains and engineering horizontals . Ourengineers have expertise across a wide range of technologies, to the efforts ofengineering our clients. Leveraging standards based components and investments indedicated test lab infrastructure; we offer innovative, flexible and cost-effectiveServices and solutions.Our MissionOur mission is to provide cost effective, technology independent, good qualityreusable Intellectual Property cores with quality and cost factor are ourimportant constraints so as to satisfy our customers ultimately. We develop andcontinuously evaluate systems so as to pursue quality in all our deliverables. At ourteam, we are completely dedicated to customers requirements. Our products aredesigned and devoted to empower their competitive edge and help them succeed.Visit www.verilogcourseteam.com for more details. 5. PrefaceThe India Semiconductor Association (ISA), an Indian semiconductorindustry organization, has briefed growth, trends and forecasts for the Indiansemiconductor market in collaboration with a U.S. consulting company Frost& Sullivan.The report titled as "ISA-Frost & Sullivan 2007/2008 Indian SemiconductorMarket Update."According to the report, total semiconductor consumption in India (total valueof semiconductors used for devices marketed in India) was $2.69 billion(USD) in 2006. The $2.69 billion represents 1.09% of the globalsemiconductor market. Of the total semiconductor consumption in India,consumption by local Indian set manufacturers accounted for $1.26 billion.The overall Indian semiconductor consumption will grow at an average rate of26.7% per year in 2006 through 2009. Based on the actual consumption in2006, the overall Indian semiconductor consumption is forecast to be $5.49billion in 2009. This represents 1.62% of the global semiconductor market in2009.Semiconductor consumption by local Indian set manufacturers is predicted toincrease at 35.8% per year in 2006 through 2009 and amount to $3.18 billionin 2009.This material is the result of the Verilog Course Teams practical experienceboth in Design/Verification and Training. Many of the examples illustratedthroughout the material are real designs models. With Verilog Course Teamstraining experience has led to step by step presentation, which addressescommon mistakes and hard-to-understand concepts in a way that easeslearning.Verilog Course Team invites suggestion and feedbacks from both students andfaculty community to improve the quality, content and presentation of thematerial. 6. VLSI DESIGNUNIT-I CMOS TECHNOLOGY1. An overview of silicon semiconductor technology 11.1 The Fabrication of a Semiconductor Device11.1.2 Wafer Fabrication21.1.3 Assembly 61.2 Basic CMOS Technology81.2.1 A Basic n-well CMOS Process91.2.2 A Basic p-well CMOS Process131.2.3 Twin-Tub (Twin-Well) CMOS Process131.2.4 Silicon On Insulator (SOI) Process 141.3 INTERCONNECT 181.3.1 Metal Interconnect 181.3.2 Polysilicon/Refractory Metal Interconnect191.3.3 Local Interconnect 201.4 CIRCUIT ELEMENTS 211.4.1 Resistors211.4.2 Capacitors 211.4.3 Electrically Alterable ROMs231.4.4 Bipolar Transistors241.4.5 LatchUp261.4.5.1 The Physical Origin of Latchup Latchup Triggering 281.4.6 Latchup Prevention 291.5. LAYOUT DESIGN RULES 301.5.1 Layer Representations311.5.2 CMOS n-well Rules321.5.3 Scribe Line34Verilog Course Teamwww.verilogcourseteam.comDream IT, We make U to Deliver 7. VLSI DESIGN1.5.4 SOI Rules341.5.5 Layer Assignments351.6 PHYSICAL DEISGN351.6.1 Basic Concept351.6.2 CAD Tools sets 371.6.3 Physical Design-The Inverter 381.6.4 Physical Design-The NOR381.6.5 Physical Design-The NAND 391.7 DESIGN STRATEGIES391.7.1 Structured Design Strategies 401.7.2 Hierarchy40UNIT 2 MOS TRANSISTOR THEORY2 .1 NMOS ENHANCEMENT TRANSISTOR 412.2 PMOS ENHANCEMENT TRANSISTOR452.3 THRESHOLD VOLTAGE452 . 3 . 1 Threshold Voltage Equations462.4 BODY EFFECT482.5 MOS Device Design Equations482.5.1 Basic DC Equations 482.5.2 Second Order Effects 502.5.2.1 Threshold Voltage-Body Effect512.5.2.2 Subthreshold Region512.5.2.3 Channel-length Modulation522.5.2.4 Mobility Variation 522.6 MOS MODELS 532.7 SMALL SIGNAL AC CHARACTERISTICS54Verilog Course Teamwww.verilogcourseteam.comDream IT, We make U to Deliver 8. VLSI DESIGN2.8THE COMPLEMENTARY CMOS INVERTER DC CHARACTERISTICS552.8.1 n/p ratio612.8.2 Noise Margin 622.9 THE TRANSMISSION GATE642.10 THE TRISTATE INVERTER 68UNIT 3 SPECIFIFCATION OF VERILOG HDL3. HISTORY OF VERILOG693.1 BASIC CONCEPTS 693.1.1 Hardware Description Language693.1.2 VERILOG Introduction 693.1.3 VERILOG Features 703.1.4 Design Flow703.1.5 Design Hierarchies 733.1.5.1 Bottom up Design 733.1.5.2 Top-Down Design743.1.6 Lexical Conventions743.1.6.1 Whitespace 753.1.6.2 Comments 753.1.6.3 Identifiers and Keywords 763.1.6.4 Escaped Identifiers763.1.7 Numbers in Verilog 763.1.7.1 Integer Numbers773.1.7.2 Real Numbers 773.1.7.3 Signed and Unsigned Numbers773.1.8 Strings783.1.9 Data types 79Verilog Course Teamwww.verilogcourseteam.comDream IT, We make U to Deliver 9. VLSI DESIGN3.1.9.1 Data Types Value set 793.1.9.2 Nets 793.1.9.3 Vectors803.1.9.4 Integer, Real and Time Register Data Types 803.1.9.5 Arrays 813.1.9.6 Memories 823.1.9.7 Parameters 823.1.9.8 Strings823.2 MODULES833.2.1 Instances843.3 PORTS843.3.1 Port Declaration 853.3.2 Port Connection Rules853.3.3 Ports Connection to External Signals 863.4 GATE DELAYS873.4.1 Rise, Fall, and Turn-off Delays873.4.2 Min/Typ/Max Values 883.5 MODELING CONCEPTS893.6 SWITCH LEVEL MODELING903.6.1 Switch level primitives913.6.2 MOS switches 923.6.3 CMOS Switches933.6.4 Bidirectional Switches 943.6.5Power and Ground953.6.6 Resistive Switches 953.8 Delay Specification on Switches963.8.1 MOS and CMOS switches963.8.2 Bidirectional pass switches97Verilog Course Teamwww.verilogcourseteam.comDream IT, We make U to Deliver 10. VLSI DESIGN3.9 GATE LEVEL MODELING1013.9.1 Gate Types 1013.10 BEHAVIORAL AND RTL MODELING 1083.10.1 Operators 1083.10.1.1 Arithmetic Operators1083.10.1.2 Relational Operators1093.10.1.3 Bit-wise Operators1103.10.1.4 Logical Operators 1123.10.1.5 Reduction Operators 1133.10.1.6 Shift Operators 1143.10.1.7 Concatenation Operator1153.10.1.8 Replication Operator1163.10.1.9 Conditional Operator1163.10.1.10 Equality Operators 1173.10.2 Operator Precedence 1193.10.3 Timing controls 1193.10.3.1 Delay-based timing control1193.10.3.2 Event based timing control1223.10.3.3 Level-Sensitive Timing Control1243.10.4 Procedural Blocks 1243.10.5 Procedural Assignment Statements1253.10.6 Procedural Assignment Groups1263.10.7 Sequential Statement Groups 1283.10.8 Parallel Statement Groups 1283.10.9 Blocking and Nonblocking assignment 1293.10.10 assign and deassign1303.10.11 force and release1313.10.12 Conditional Statements 131Verilog Course Teamwww.verilogcourseteam.comDream IT, We make U to Deliver 11. VLSI DESIGN3.10.12.1 The Conditional Statement if-else1313.10.12.2 The Case Statement 1323.10.12.3 The casez and casex statement1343.10.13 Looping Statements 1363.10.13.1 The forever statement1363.10.13.2 The repeat statement 1363.10.13.3 The while loop statement 1373.10.13.4 The for loop statement 1383.11 DATA FLOW MODELING AND RTL1393.11.1 Continuous Assignment Statements1393.11.2 Propagation Delay 1413.12 STRUCTURAL GATE LEVEL DESCRIPTION 1413.12.1 2 to 4 Decoder1413.12.2 Comparator1423.12.3 Priority Encoder1443.12.4 D-latch 1443.12.5 D Flip Flop 1453.12.6 Half adder1453.12.7 Full adder1463.12.8 Ripple Carry Adder146UNIT 4 CMOS CHIP DESIGN4.1 INTRODUCTION TO CMOS 1484.2 LOGIC DESIGN WITH CMOS 1494.2.1 COMBITIONAL LOGIC1494.2.2 INVERTER 1504.2.3 The NAND Gate1514.2.4 The NOR Gate152Verilog Course Teamwww.verilogcourseteam.comDream IT, We make U to Deliver 12. VLSI DESIGN4.3 TRANSMISSION GATES 1534.3.1Multiplexers1534.3.2 Lathes 1534.4 CMOS CHIP DESIGN OPTIONS 1544.4.1 ASIC 1544.4.2 Uses of ASICs1554.4.3 Full Custom ASICs1554.4.5 Semi-Custom ASICs1564.4.6 Standard- Cell-Based ASIC1564.4.7 Gate Array Asic1574.4.8 Channeled Gate Array 1584.4.9 Channelless Gate Array 1584.4.10 Structured Gate Array 1594.5 PROGRAMMABLE LOGIC 1594.5.1 Programmable Logic Structures1604.5.2 Programmable of PALs 1614.5.3 Fusible Links1614.5.4 UV-erasable EPROM1614.5.5 EEPROM 1614.5.6 Programmable Interconnect1624.6 ASIC DESIGN FLOW 163UNIT-5 CMOS TEST METHODS5.1 THE NEED FOR TESTING 1655.1.1 Functionality Tests1665