Counter And Sequencer Design- Student

Counter and Sequencer Design

Digital Logic and

Software Principles

© University of Wales Newport 2009 This work is licensed under a Creative Commons Attribution 2.0 License.

The following presentation is a part of the level 4 module -- Digital Logic and Signal Principles. This resources is a part of the 2009/2010 Engineering (foundation degree, BEng and HN) courses from University of Wales Newport (course codes H101, H691, H620, HH37 and 001H). This resource is a part of the core modules for the full time 1st year undergraduate programme.

The BEng & Foundation Degrees and HNC/D in Engineering are designed to meet the needs of employers by placing the emphasis on the theoretical, practical and vocational aspects of engineering within the workplace and beyond. Engineering is becoming more high profile, and therefore more in demand as a skill set, in today’s high-tech world. This course has been designed to provide you with knowledge, skills and practical experience encountered in everyday engineering environments.

Contents Counters Asynchronous Design Decade Counter Synchronous Design Design sequence Logic Diagram for the Counter Design a counter which counts from 1 to 5 then back to 1 The State Diagram Design a sequencer with the following sequence built in: The State Diagram There are two possible solutions: Credits

In addition to the resource below, there are supporting documents which should be used in combination with this resource. Please see: Holdsworth B, Digital Logic Design, Newnes 2002 Crisp J, Introduction to Digital Systems, Newnes 2001

Counter & Sequence Design

Counters

There are two design methodologies, these being:

Asynchronous Design

Synchronous Design

The choice of method will depend upon a number of factors including:

Speed at which the counter is to operate

Ease of design

We will look at both methods.


Asynchronous Design

If we have a JK bistable and the J and K inputs are set at logic 1 then it will act as a toggle bistable. If we have a number of these in a line then we will have the following:

J

K

Q

Q

Ck

J

K

Q

Q

Ck

J

K

Q

Q

Ck

1

111

11

Clock

QA QB QC

We will assume the bistables are falling edge triggered.

The timing diagram on the next slide shows how the Q outputs vary as the clock is pulsed.

clock

QA

QB

QC

1

0

1

*

Note that this acts as a counter – after the 5th pulse on the clock the outputs read 1 0 1 (QC, QB, QA).

This type of counter can suffer from a delay in the reading being correct – let us look in detail at the change marked with an asterisk.

clock

QA

QB

QC

The timing diagram shows an expanded version of the previous diagram around the moment marked with an asterisk.

t

t

t

t is the delay through a single JK bistable.

In total we have a possible delay of 3t

With an “n” bit counter we could have a maximum delay before the count is correct of nt.

This may be a problem with fast counters.

Assuming that the delay is not a problem we can simply extend the number of bits in the counter by adding more JK bistables.

To count up to 15 we would need 4 bistables




If the count needs to stop at a certain value and return to zero (e.g. a decade counter … 0 9 then back to 0) then this can achieved by recognising the next number and immediately resetting the bistables to 0.


Decade Counter.

QD

Clock

QA

J

K

Q

Q

Ck

1

1Cl

Pr

1 QB

J

K

Q

Q

Ck

1

1Cl

Pr

1 QC

J

K

Q

Q

Ck

1

1Cl

Pr

1

J

K

Q

Q

Ck

1

1Cl

Pr

1

1 1 1 1

The normal 4 bit counter is converted in the following way The NAND recognises 1010 (10) and

resets

It is possible to have quite complex count sequences:

QD

Clock

QA

J

K

Q

Q

Ck

1

1Cl

Pr

QB

J

K

Q

Q

Ck

1

1Cl

Pr

QC

J

K

Q

Q

Ck

1

1Cl

Pr J

K

Q

Q

Ck

1

1Cl

Pr

1

11 1


The count sequence is as follows:

Assume count starts at 0000

Count rises until we hit 0111 (7) – the right NAND recognises this.

QA and QC are reset and QD is set – 1010 (10)

Count now continues until we hit 1101 (13) – the left NAND recognises this.

QC and QD are reset – 0001 (1)

The sequence is therefore:

0 – 1 – 2 – 4 – 5 – 6 – 10 – 11 – 12 – 1 – 2 – 3 - etc


The design of asynchronous sequencers is not ideal as we must momentarily hit the number that will trigger the jump. This means that for a short time a number appears on the outputs which should not be there – in our previous example 0111 (7) and 1101 (13).

This may lead to false triggering of other parts of the logic circuit.

Synchronous design does away with this problem as the sequence is designed into the circuit. It also does away with the problem of delays as all bistable change at the same moment in time.


Synchronous Design

Before we look at the design methodology, we need to look back at the operation of the JK bistable.

J K Qn+1

0 0 Qn

0 1 0

1 0 1

1 1 Qn

If we know the current state of the bistables output and we know what we wish it to be after the clock, we can use the table to determine what J and K need to equal.

There are four possible “before and after the clock” conditions.


Consider the situation where Qn = 0 and after the clock pulse we want it to stay at 0 i.e. Qn+1 = 0

What must J and K equal for this to be the situation?

Either of these would give the desired effect.

Combining these we can say:

As long as

What about the rest?Counter & Sequence Design

Consider the situation where Qn = 0 and after the clock pulse we want it to change to 1 i.e. Qn+1 = 1


As long as

Consider the situation where Qn = 1 and after the clock pulse we want it to change to 0 i.e. Qn+1 = 0


As long asCounter & Sequence Design

Consider the situation where Qn = 1 and after the clock pulse we want it to stay at 1 i.e. Qn+1 = 1


As long as

Summarising this gives us:

Qn Qn+1 J K

0 0

0 1

1 0

1 1

We can now use this to design a synchronous counter or sequencer.


Present State Next State A B C

A B C A B C J K J K J K

Design sequence – fill in the table - 3 bit binary counter


We must now find an expression for each of the JK inputs in terms of the Present State A, B and C values.

Note

1. We cannot use next state value of A, B and C as they do not yet exist.

2. The not values of A, B and C are available to us.

3. We can have logic 1 as an expression if appropriate.

4. If it is difficult to recognise an expression use a Karnaugh Map.


CK – This can be realised using

CJ - This can be realised using

BK - This can be realised using

BJ - This can be realised using

AK - This can be realised using

AJ - This can be realised usingA

C B00

01

11

10

0

1

AC B

00

01

11

10

0

1


We can now construct the logic diagram for the counter. Note the clock goes to each bistable. The Cl and Pr are not required but must be connected to logic 1.

Clock

C

J

K

Q

Q

Ck

B

J

K

Q

Q

Ck

A

J

K

Q

Q

Ck

This counter is more complex to design but the correct count number is reached in 1t – this is true for any number of JK bistables in the counter

Design a counter which counts from 1 to 5 then back to 1

i.e. 001 010 011 100 101 001 010 etcPresent State Next State A B C



AC B

00

01

11

10

0

1






AJ - This can be realised using

If there are spaces in the Karnaugh map fill them with X’s


Clock

C

J

K

Q

Q

Ck

B

J

K

Q

Q

Ck

A

J

K

Q

Q

Ck

You will note that only five out of the possible eight combinations of QA, QB and QC have been used. It is important to know what happens if the system starts in one of the three which are unused.


Present State A B C

NextState

A B C J K J K J K A B C

We can see that000 (0) goes to110 (6) goes to111 (7) goes to


We can now draw the State Diagram


Design a sequencer with the following sequence built in.

i.e. 011 111 010 101 000 011 111 etcPresent State Next State A B C








AJ - This can be realised usingWe have a number of options as to what to use for the J and K inputs – we will select the first one in each line.

Once again we only use five out of the possible eight combinations of QA, QB and QC. It is good practice to check the solution. Counter & Sequence Design

Present State A B C

NextState


We can see that001 (1) goes to 100 (4) goes to 110 (6) goes to




There are two possible solutions:

1. Recognise the problem state and move the system into a new state.

C

B

A

Q

Q

Q ClA PrB, PrC

If state 100 (4) occurs it is “kicked” into state 011 (3).

This effectively corrects a bad design

2. Redesign using one of the possible options for J and K.

Select not C for CJ


Present State A B C

NextState


We can see that001 (1) goes to100 (4) goes to 110 (6) goes to

New combination is fine.Counter & Sequence Design


Now we can look at the logic diagram.


Clock

C

J

K

Q

Q

Ck

B

J

K

Q

Q

Ck

A

J

K

Q

Q

Ck

Design a sequencer which will follow the sequence of a set of UK traffic lights.



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© 2009 University of Wales Newport

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