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Chapter 1 UEEA2223/UEEG4223

Integrated Circuit Design

VLSI: An Introduction

Prepared by Dr. Lim Soo King 02 Jan 2011.

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Chapter 1 VLSI Design: An Introduction ........................................ 1 1.0 Introduction ................................................................................................ 1

1.0.1 Early Computing Machine .................................................................................. 1 1.0.2 Invention of Transistor and Integration Circuit ............................................... 2

1.1 General Trend ............................................................................................ 2 1.2 Device Scale Down...................................................................................... 6 1.3 Frequency Improvement ........................................................................... 7 1.4 Layers .......................................................................................................... 8 1.5 Density ....................................................................................................... 10 1.6 Design Trends ........................................................................................... 12 1.7 High Dielectric Constant Materials ........................................................ 12 1.8 Metallization ............................................................................................. 13 1.9 Cost of an Integrated Circuit .................................................................. 14 1.10 Die Yield and Defect Density ................................................................. 15 Exercises .......................................................................................................... 15 Bibliography ................................................................................................... 16

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Figure 1.1: Photograph illustrating the internal parts of a hand phone ................................ 3 Figure 1.2: Typical structure of an integrated circuit mounted on a ball grid array............. 4 Figure 1.3: Patterns representative of each scale decade from 10cm-size instrument to

10nm-size oxide layer ........................................................................................ 4 Figure 1.4: Intel microprocessors compared with Moore’s Law ......................................... 5 Figure 1.5: Evolution of dynamic RAM and flash semiconductor memories ...................... 6 Figure 1.6: Evolution of lithography .................................................................................... 7 Figure 1.7: Increased operating frequency of microprocessors and micro-controllers ........ 8 Figure 1.8: Evolution of key parameters with the technology scale down .......................... 8 Figure 1.9: Cross-section of the 0.35µm CMOS .................................................................. 9 Figure 1.10: 2D view of the 0.12µm process ....................................................................... 10 Figure 1.11: Relative dimension comparison of an NAND gate designed with various

technologies ..................................................................................................... 11 Figure 1.12: The silicon wafer used for patterning the integrated circuits ........................... 11 Figure 1.13: Evolution of integrated circuit design techniques, from layout level to system

level .................................................................................................................. 12 Figure 1.14: High dielectric constant material ..................................................................... 13

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Chapter 1

VLSI Design: An Introduction _____________________________________________ 1.0 Introduction The advancement in integrated circuit technology has changed the concept of digital data manipulation, which in turn has dramatically impacted our society. It evolved from the earlier days of mainframe computer to minicomputer, personal computer, and laptop computer. More significantly, the use of integrated circuits for designing digital solution is continuous in all areas of electronics, such as in instrumentations, and conversion of telecommunications and consumer electronic into digital format. In this chapter, student will be giving a briefing pertaining to the historical perspective of the VLSI system right from early computing machine to the invention of first transistor in 1947 and integrated circuit in 1958. Information illustrating technology trend, scale down, frequency improvement, design trend, design technology such as interconnect materials, dielectric material, software used etc, and CMOS technology are presented. At the end of this chapter, packaging of integrated circuit is introduced. 1.0.1 Early Computing Machine

The first implementation of computational engine was way back in early 19th century, which was the Babbage’s difference engine. Although this was a decimal engine, nevertheless the underlying concept of computing was the same as the modern binary system. The analytical engine developed in 1934 was perceived as a general purpose machine, which had feature closed modern computer.

Early digital electronics systems were designed based on magnetically

control switches or relays. They were used mainly in the implementation of very simple logic networks. Such system is still used in the train safety system today. The age of digital computing began with vacuum tube. The vacuum tube digital design culminated with the design of Electronic Numerical Integrator and Computer ENIAC intended for computing artillery firing tables and Universal Automatic Computer I UNIVAC I, which is the first successful commercial computer. The ENIAC was 80 feet long, 8.5 feet high, and several feet wide. It has 18,000 vacuum tubes. It was rapidly become clear that vacuum tube

1 VLSI Design: An Introduction

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technology had reached its design limit. Reliability problem and excessive power consumption had made the implementation of larger engine economically and practically infeasible.

1.0.2 Invention of Transistor and Integration Circuit

Since the invention of transistor in 1947 at Bell laboratory and followed by the induction of the bipolar junction transistor by William Shockley in 1949, the evolution of integrated circuit IC fabrication techniques is a unique fact in the history of modern industry. There have been steady improvements in terms of speed, density, and cost for more than 50 years.

In 1956, the first bipolar digital logic gate made of discrete components was introduced by Harris Semiconductor. In 1958, Jack Kilby at Texas Instruments conceived the integrated circuit, in which all components including passive and active types are integrated on a single semiconductor substrate. This invention led to the introduction of the first set of integrated circuit commercial logic gate called the Fairchild Micrologic Family. In 1962, the first true successfully IC logic family, the transistor-transistor logic TTL was born. Other digital family was devised from TTL such as the emitter-coupled logic ECL was designed in 1974.

Eventually bipolar junction transistor digital logic lost the battle for hegemony in digital design to the low power bipolar families such as integrated injection logic I2L and metal oxide semiconductor field effect transistor MOSFET integrated circuit. MOSFET became dominated not only due low power consumption but able to make into miniature form and millions of them can be integrated in a single semiconductor substrate.

1.1 General Trend Inside a general purpose electronics system such as personal computer, hand phone, or an instrument, there are numerous integrated circuits IC placed together with discrete components on the printed circuit board PCB. Figure 1.1 illustrates an example, the hand phone PCB.


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Figure 1.1: Photograph illustrating the internal parts of a hand phone The integrated circuits appearing in this example have various sizes and complexities. The main core of the circuits consists of a microprocessor and a digital signal processor DSP considered as the heart of the system. Each has several millions of transistors on a single chip. The push for smaller size, reduced power supply consumption, and enhancement of services, has resulted in continuous technological advances, with the possibility of ever higher integration.

The integrated circuit consists of a silicon die, with a size of usually around 2.0cm x 2.0cm for the case of microprocessors and memories. The integrated circuit is normally mounted on a package as shown in Fig 1.2, which is placed on a printed circuit board. The active part of the integrated circuit is only a very thin portion of the silicon die. At the border of the chip, small solder bumps serve as electrical connections between the integrated circuit and the package. The package itself is a sandwich of metal and insulator materials that conveys the electrical signals to large solder bumps, which interface with the printed circuit board.


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Figure 1.2: Typical structure of an integrated circuit mounted on a ball grid array

Inside the electronic equipment, one may see the integrated circuits in package form and passive elements are mounted on the same printed circuit board in 1.0cm scale. Inside the package, wire connecting between the package and the integrated circuit is in 1.0mm scale, whilst input/output structures of the integrated circuit are in 100µm scale. The integrated circuit layout is in 10µm dimension. A vertical cross-section of the process reveals a complex stack of layers and insulators in 1.0µm scale, and the active device itself the MOS transistor 100nm thick. Figure 1.3 illustrates the patterns representing a 10cm size instrument to the oxide thickness of 10nm thickness.

Figure 1.3: Patterns representative of each scale decade from 10cm-size instrument to

10nm-size oxide layer

In 1960, Gordon Moore, a co-founder of Intel predicted that the number of transistors that could be manufactured on a chip would grow exponentially for memory device and speed of the device. This prediction is known as Moore’s Law, was remarkable prescient. He then ultimately predicted that the transistor


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count would double every 18 months. Moore’s Law has held up to the Itanium® 2 processor, which has around 400 million transistors.

Figure 1.4 describes the evolution of the complexity of Intel microprocessors in terms of number of devices on the chip compared with Moore’s Law prediction. The Pentium IV processor produced in 2003 had about 50,000,000 MOS transistor devices integrated on a single piece of silicon not larger than 2.0cm x 2.0cm.

Since the 1kb memory produced by Intel in 1971, semiconductor memories have improved both in density and performances, with the production of 256Mb dynamic memories DRAM in 2000, and 1Gb memories in 2004. In other words, within around 50 years, the number of memory cells integrated on a single die has been multiplied by 1,000,000. Another type of memory chip called Flash memory has become very popular, due to its capabilities to retain the information without supply voltage. Figure 1.5 shows the evolution of dynamic RAM and flash semiconductor memories from the 80’ to 00’.

Figure 1.4: Intel microprocessors compared with Moore’s Law


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Figure 1.5: Evolution of dynamic RAM and flash semiconductor memories

1.2 Device Scale Down There are four main generations of integrated circuit technologies: micron, submicron, deep submicron, and ultra deep submicron technology, as illustrated in Fig. 1.6. The submicron era started in 1990 with 0.8µm technology. The deep submicron technology started in 1995 with the introduction of lithography thinner than 0.3µm. Ultra deep submicron technology concerns with lithography below 0.1µm. Figure 1.6 shows that research has always kept around five years ahead of mass production. It can also be seen that the trend towards smaller dimension has accelerated since 1996. In 2007, the lithography was decreased to 65nm. The lithography expressed in µm corresponds to the smallest patterns that can be implemented on the surface of the integrated circuit.


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Figure 1.6: Evolution of lithography

1.3 Frequency Improvement Figure 1.7 illustrates that the clock frequency increases for high-performance microprocessors and industrial micro-controllers with the technology scale down. The microprocessor roadmap is based on Intel microprocessors used for personal computers, while the micro-controller roadmap is based on Freescale micro-controllers used for high performance automotive industry applications. The personal computer industry requires microprocessors running at the highest frequencies, which entails very high power consumption like 30 watts for the Pentium IV generation. The automotive industry requires embedded controllers with more and more sophisticated on-chip functionalities, larger embedded memories, and interfacing protocols. The operating frequency follows a similar trend to that of personal computer processors but with a significant shift toward right.


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Figure 1.7: Increased operating frequency of microprocessors and micro-controllers

1.4 Layers Figure 1.8 lists a set of key parameters, and their evolutions with the technology. Special attention is paid to the increased number of metal interconnects, the reduction of the power supply VDD and the reduction of the gate oxide down to atomic scale values. Notice also the increase in the size of the die and the increasing number of input/output pads available on a single die.

Lithography Year No of Metal Layer

Core Supply

(V)

Core Oxide (nm)

Chip Size (mm)

Input/Output Pads

1.2µm 1986 2 5.0 25 5x5 250 0.7µm 1988 2 5.0 20 7x7 350 0.5µm 1992 3 3.3 12 10x10 600 0.35µm 1994 5 3.3 7 15x15 800 0.25µm 1996 6 2.5 5 17x17 1,000 0.18µm 1998 6 1.8 3 20x20 1,500 0.12µm 2001 6-8 1.2 2 22x20 1,800 90nm 2003 6-10 1.0 1.8 25x20 2,000 65nm 2005 6-12 0.8 1.6 25x20 3,000

Figure 1.8: Evolution of key parameters with the technology scale down


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The 1.2µm CMOS process features n and p-MOS devices with a channel length of 1.2µm. The two-layer metal interconnects are 2µm wide. The MOS diffusion is around 1.0µm deep.

The 0.35µm CMOS technology is a five-metal layer process with a minimal MOS device length of 0.35µm. The MOS device includes lateral drain diffusion, with shallow trench oxide isolations. Metal interconnects are less than 1µm wide. The MOS diffusion is less than 0.5µm deep. The two-dimensional aspect of this technology is shown in Fig. 1.9.

Figure 1.9: Cross-section of the 0.35µm CMOS

The CMOS 0.12µm six-metal layer process with a minimal MOS device length of 0.12µm is shown in Fig. 1.10. The metal interconnects are very narrow, around 0.2µm, separated by 0.2µm. The MOS device appears very small, below the stacked layers of metal sandwiched between oxides.


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Figure 1.10: 2D view of the 0.12µm process

1.5 Density The improvement of lithography enables implementing an identical function in an ever smaller silicon area. Consequently, more functions can be integrated in the same space. Moreover, the number of metal layers used for interconnects has been continuously increasing in the course of past ten years. More layers for routing means a more efficient use of the silicon surface, as for printed circuit boards. Active areas, i.e. MOS devices, can be placed closer to each other if many routing layers are provided. The increased density provides two significant improvements. Firstly, the reduction of the silicon area goes together with a decrease in the parasitic capacitance of junctions and interconnects. Thus, it increases the switching speed of device. Secondly, shorter dimension of the device itself speeds up switching, which leads to further operating clock improvements. Figure 1.11 shows the relative dimension comparison of an NAND gate designed with 1.2µm, 0.35µm, 0.12µm, and 90nm technologies. Note that the cross sectional area is significantly reduced from 1.2µm technology design to 90nm technology design.


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Figure 1.11: Relative dimension comparison of an NAND gate designed with various

technologies

The silicon wafer, on which the chips are fabricated, has constantly increased in size with technological advances. A larger diameter means more chips can be fabricated at the same time but it requires ultra-high cost equipment that is able to manipulate and process these wafers with an atomic-scale precision. This trend is illustrated in Figure 1.12. The wafer diameter for 0.12µm technology is 8in or 20cm. Twelve inch wafers have been introduced for 90nm technology generation. The thickness of the wafer varies from 300 to 600µm.

Figure 1.12: The silicon wafer used for patterning the integrated circuits


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1.6 Design Trends Originally, integrated circuits were designed at the layout level with the help of logic design tools so that it can achieve design complexities of around 10,000 transistors. The layout tool works at the lowest level of design, while some operate at the logic level. The introduction of high level description languages such as VHDL and Verilog have made it possible to design a complete system on a chip SoC with complexities ranging from 1 million to 10 million transistors as shown in Fig. 1.13. Recently, languages for specifying circuit behavior such as SystemC language have been available, which can be used to design chip with complexity between 100 and 1,000 million transistors. Notice that the technology has always been ahead of design capabilities.

Figure 1.13: Evolution of integrated circuit design techniques, from layout level to system level

1.7 High Dielectric Constant Materials Reducing the thickness of conventional oxides such as silicon dioxide SiO2 will cause in reliability degradation and unacceptable current leakage. New dielectric materials shown in Fig. 1.14 with high dielectric constant k are needed to replace SiO2 for both for the MOS device and the embedded capacitors. High-capacitance passive devices known as metal-insulator-metal MIM capacitor are needed for various purposes including on-chip power supply decoupling, analog filtering for wireless applications and high-quality resonators for radio-frequency circuits. These capacitors feature high reliability, low current leakage, low series resistance and low dielectric loss. They are fully compatible with the standard CMOS processes.


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Material Dielectric Constant Remarks

Fluor-oxide HfO2 20 It is proposed for 45nm gate oxide

Tantalum pentoxide Ta2O5

25 High crystallization temperature. Reliability issue

Niobium tantalum pentoxide NixTa2O5

28 Good for MIM capacitor

Silicon dioxide nitride SiOxNy

5-7 For 65nm gate oxide

Silicon dioxide SiO2 3.9 Important ultra-thin film leakage

Figure 1.14: High dielectric constant material

Both MOS devices and passive components may benefit from high k insulators. Concerning MOS devices, high k dielectric layer can be made thicker than SiO2 to obtain the same equivalent channel effect, thereby reducing leakage. Concerning passive component, larger permittivity means larger charge that can be stored in the memory capacitor, thus resulting in higher capacitance values. Alternatively, the same capacitance may require less silicon area with high k insulators than with conventional silicon dioxide SiO2. Typical values for the capacitance range from 2 to 20fF/µm2. 1.8 Metallization Metallization process is carried out in order to form interconnect layers. Aluminum with resistivity of 2.7µΩ-cm, is widely used as metal. In the case of scaled down CMOS, electro-migration EM and stress migration SM become serious problems. In order to prevent these problems, Al-Cu typically 0.5 wt % Cu is used. In addition, ultra-shallow junction as the result of scaling down sometimes needs barrier metal such as TiN, between the metal and silicon, in order to prevent junction leakage current.

The RC delay of aluminum metal interconnects increases because decreasing of the feature size of the device. This increase is more significant than the reduction RC due to shrinking of device. Consequently, the total delay time for device scaled down to 250nm increases. To overcome the problem, high conductivity metal such as copper and low dielectric (low k) insulators such as organic polyimide or inorganic fluorine-doped oxide materials are used. The resistivity of copper is 1.7µΩ-cm, which better than aluminum of 2.7µΩ-cm. This is better in terms of resistance. Copper is also 10-100 times better


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resistant to electro-migration. Low k material such as polyimide has a lower capacitance since capacitance is a function of dielectric constant. Thus, polyimide and copper have shown a significant decrease in RC time constant compared with that of aluminum and silicon dioxide. The combination of material is ideal for multi-level interconnection for deep-submicron technology. 1.9 Cost of an Integrated Circuit

The total cost of integrated circuit can be separated into two components, which are the recurring cost or the variable cost and the non-recurring costs or fixed cost.

The fixed cost is independent of the sales volume, the number of products sold. An important component of the fixed cost of an integrated circuit is the design cost. The design cost is strongly dependent on the complexity of the design, the stringent requirements of the specifications, and the productivity of the designer. With the advanced design methodologies that forms a part of automatic design process help to reduce the fixed cost. Beside this cost, the fixed cost is the company overheads, which includes the company’s research and development R&D, manufacturing equipment, marketing, sales, and building infrastructure etc.

Variable cost accounts for the cost that is directly attributable to a

manufactured product, which is proportional to the volume of product. The variable costs include the costs of the parts used in the product, assembly cost, testing cost, and operator cost. The total cost of an integrated circuit can then be calculated using equation (1.1).

Cost of IC = Variable cost of die + Volume

tcosFixed (1.1)

Owing to the maturity of the fabrication and assemble processes, over the year the cost of the integrated circuit has been dropped exponentially. The equation to calculate variable cost still remains, which is shown on equation (1.2).

Variable cost = yiedtestFinal

packageoftcostestassemblyoftcosied of Cost

/ ++

(1.2)


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The cost of the die depends upon the number of good die - functional working integrated circuit on a wafer after probe test. Thus, the cost of the die can be calculated using equation (1.3).

Cost of die = per wafer Die x yield Die

waferof Cost (1.3)

1.10 Die Yield and Defect Density Upon completion of the fabrication, the wafer is chopped into die, which is an individual integrated circuit. This die is then individually packaged in assembly and tested using automatic test equipment ATE and automatic test handler ATH.

The number of dice per wafer is essentially the area of the wafer divided by the area of a die. The actual situation is somewhat more complicated as wafer is round and die is square. Die around the perimeter of the wafer are therefore lost. Equation (1.4) is used to calculate the yield of the die.

Yield of die = α−

α+ area die x areaunit per Defect

1 (1.4)

α depends on the complexity of the manufacturing process, which is number of mask dependent. For today complexity of integrated circuit manufacturing, α can be taken as equal to 3. From equation (1.4), one can see that the larger the die area, the lower will be the yield of die.

Defect density per unit area describes point defect on the wafer surface and is significant because a single defect can ruin the circuitry on the die. Typical value of defect density is less than one defect per cm2 area. Indeed the defect can be from the random imperfection of silicon crystal that cannot be eliminated or from process imperfection such as misalignment of mask, residue of photoresist material, dirt and etc.

Exercises 1.1. Plot the frequency improvement versus the technology for the CMOS

technology family. Predict the frequency of 35nm technology. You may use the data in Fig. 1.6 and Fig. 1.7 to help you.


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1.2. With the technology scale down, the silicon area decreases for the same device (Fig. 1.6), but the chip size increases (Fig. 1.7). Can you explain this contradiction?

1.3. State Moore’s Law. 1.4. State the reason why it is necessary to replace SiO2 with high dielectric

constant material as the dielectric material for 45nm ultra deep submicron device fabrication.

1.5. A wafer has 12 inch diameter. Dice of size 2.5cm2 are fabricated on it

with 1 defects/cm2, and α = 3. Determine the die per wafer and die yield of this wafer.

1.6. If the cost of wafer is 2,000 dollars, using the results of question 1.5,

calculate the die cost.

1.7. State one reason why the defect density of the fabricated wafer will increase as the dimension of transistor becomes smaller.

Bibliography 1. Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic, “Digital

Integrated Circuits: A Design Persperctive”, second edition, Pearson Education International, 2003.

2. Etienne Sicard and Sonia Delmas Bendhia, “Basics of CMOS Cell Design”, McGraw Hill, 2007.

3. Etienne Sicard and Sonia Delmas Bendhia, “Advanced CMOS Cell Design”, McGraw Hill, 2007.

4. John P. Uyemura, “Introduction to VLSI Circuits and Systems”, John Wiley & Sons, Inc. 2002.

5. Stephen A. Campbell, "The Science and Engineering of Microelectric Fabrication", second edition, Oxford University Press, Inc. 2001.