PROGRAMMABLE LOGIC DEVICES, THRESHOLD LOGIC

Unit-4

TOPICS:

Basic PLD’s- ROM, PROM, PLA and PLD Realization of Switching Functions using

PLD’s Threshold Logic: Capabilities of Threshold

gate Synthesis of threshold functions Multi gate Synthesis

INTRODUCTION

A programmable Logic Device is an integrated

circuit with internal logic gates that are

connected through electronic fuses.

Programming the device involves the blowing of

fuses along the paths that must be disconnected

so as to obtain a particular configuration.

The word programming here refers to a

hardware procedure that specifies the internal

configuration of the device.

INTRODUCTION

The gates in a PLD are divided into an AND

array and an OR array that are connected

together to provide an AND-OR sum of

product implementation.

The initial state of a PLD has all the fuses

intact.

Programming the device involves the blowing

of internal fuses to achieve a desired logic

function.

ROM VS. PLA/PAL

(a) Programmable read-only memory (PROM)

InputsFixed

AND array(decoder)

ProgrammableOR array

OutputsProgrammableConnections

(b) Programmable array logic (PAL) device

Inputs ProgrammableAND array

FixedOR array

OutputsProgrammableConnections

(c) Programmable logic array (PLA) device

Inputs ProgrammableOR array

OutputsProgrammableConnections

ProgrammableConnections

ProgrammableAND array

READ-ONLY MEMORYROM

7

ROM

A ‘B’C’D’ A ‘B’C’D A ‘B’CD’A ‘B’CD A ‘BC’D’ A ‘BC’D A ‘BCD’ A ‘ BCD A B’C’D’ A B’C’D A B’CD’ A B’CD

A B C’D’A B C’D A B C D’ A B C D

F 1

F 3

F 2

A

B

C

D

S2

S1

S0

S3

0 1 2 3 4 5 6 7 8 9

10 1 1 12 13 14 15

4:16 dec

Enb

• Decoder Produces minterms

• ORs Produce SOP’s

ROM

D7D6D5D4D3D2D1D0

A2

A1A0

A

B

C

F0F1F2F3

X XX

XX

X

XX

XX

• ROM A decoder A set of programmable

OR’s

EXAMPLEFind a ROM-based circuit implementation for:f(a,b,c) = a’b’ + abcg(a,b,c) = a’b’c’ + ab + bch(a,b,c) = a’b’ + c

Solution:Express f(), g(), and h() in m()

format (use truth tables)Program the ROM based on the 3

m()’s

EXAMPLE There are 3 inputs and 3 outputs, thus we need a

8x3 ROM block. f = m(0, 1, 7) g = m(0, 3, 6, 7) h = m(0, 1, 3, 5, 7)

3-to-8decoder

01234567

a

b

c

f g h

ROM AS A MEMORY Read Only Memories (ROM) or Programmable

Read Only Memories (PROM) have: N input lines, M output lines, and

2N decoded minterms. Can be viewed as a memory with the inputs

as addresses of data.

(MEMORIES)Volatile:

Random Access Memory (RAM): SRAM "static" DRAM "dynamic"

Non-Volatile: Read Only Memory (ROM):

Mask ROM "mask programmable" EPROM "electrically programmable" EEPROM “electrically erasable electrically

programmable" FLASH memory - similar to EEPROM with

programmer integrated on chip

ROM AS MEMORY

0 1 1 0 1

1 0 0 0 0

2 1 0 0 1

3 0 0 1 0

4 0 0 0 0

5 1 0 0 0

6 0 0 1 1

7 0 1 0 0

Address

3 4

8x4 ROM

D0D1D2D3D4D5D6D7

A2

A1A0

A2

A1

A0

F3F2F1F0

X XX

XX

X

XX

XX

Example: For input (A2,A1,A0) = 011, output is (F0,F1,F2,F3 ) = 0010.•What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)?

A[2:0] F[3:0]

PROGRAMMABLE LOGICPAL, PLA

16

PLASProgrammable Logic Array

Pre-fabricated building block of many AND/OR gates (or NOR, NAND) "Personalized" by making/ breaking connections among the gates.

General purpose logic building blocks.

17

PLA

Inputs

Dense array of AND gates Product

terms

Dense array of OR gates

Outputs

18

PLA

19

PLA

• A 3×2 PLA with 4 product terms.

20

DESIGN FOR PLA:EXAMPLE

Implement the following functions using PLAF0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + A

Personality Matrix

1 = asserted in term0 = negated in term- = does not participate

Input Side:

1 = term connected to output0 = no connection to output

Output Side:Outputs Inputs Product

t erm

Reuse of

t erms

A 1 - 1 - 1

B 1 0 - 0 -

C - 1 0 0 -

F 0 0 0 0 1 1

F 1 1 0 1 0 0

F 2 1 0 0 1 0

F 3 0 1 0 0 1

A B B C A C B C A

21

EXAMPLE: CONTINUED

F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + A

Personality Matrix

Outputs Inputs Product t erm

Reuse of

t erms

A 1 - 1 - 1

B 1 0 - 0 -

C - 1 0 0 -

F 0 0 0 0 1 1

F 1 1 0 1 0 0

F 2 1 0 0 1 0

F 3 0 1 0 0 1

A B B C A C B C A

A B C

F0 F1 F2 F3

AB

B’C

AC’

B’C’

A

CONSTANTS

Sometimes a PLA output must be programmed to be a constant 1 or a constant 0. P1 is always 1 because

its product line is connected to no inputs and is therefore always pulled HIGH;

this constant-1 term drives the O1 output.

No product term drives the O2 output, which is therefore always 0.

Another method of obtaining a constant-0 output is shown for O3.

PALS Programmable Array Logic

a fixed OR array.

Inputs

Dense array of AND gates Product

terms

Dense array of OR gates

Outputs

PALinputs

1st output section

2nd output section

3rd output section

4th output section

Only functions withat most four products can be implemented

PAL

W = ABC + CDX = ABC + ACD + ACD + BCD Y = ACD + ACD + ABD

x

x

x

END of Unit-4 (Part-1)

THRESHOLD

LOGICSHOLD LOGICUNIT-4(PART-2)

(STLD AUTONOMOUS)

Logic design of sw functions constructed of electronic gates different type of switching element : threshold element.

Threshold element can be considered as a generalization of the conventional gates.

A large class of sw fn. can be realized by a single threshold element through lots of combinations of weights and threshold.

Threshold function : A fn f(x1, x2, ••• , xn) is defined as a threshold fn iff there exists a set of weights {w1, w2, ••• , wn} and a threshold T such that

f(x1, x2, ••• , xn) = 1, iff

f(x1, x2, ••• , xn) = 0, iff

,where T and weights wi’s are real number, xi’s are binary inputs, and each weight wi is associated

with a particular input var xi.

A straightforward approach to identify a threshold fn is to derive from the truth table, a set of 2n linear simultaneous inequalities and to solve them.

w1 ••• wi ••• wn

Tx1 ••• xi ••• xn

f

<Threshold element>

n

iii Txw

1

,

n

iii Txw

1

.

Eg) f(x1, x2, x3) = (0,1,3)

0 T w3 T w2 < T w2+w3 T

w1 < T w1+w3 < T w1+w2 < T

w1+w2+w3 < T

11010000

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

Inequality( )fx1 x2 x3

3

1iii Txw

w3>w2

w3>w1

w3>w1+w3 w1<0

To find more effective methods, we will study the properties of a Threshold fn.

Capabilities and limitation (A two input NOR gate)

-1

-1-½x1

x2

f 0 0 1 0 1 0 1 0 0 1 1 0

x1 x2 f<NOR gate>

Since a NOR gate is strongly logically complete, any combinational sw. fn can be realized by threshold elements alone. Because of huge possible combinations of weights and threshold, lots of sw. fn can be realized by only one threshold element threshold fn

Is every sw. fn a threshold fn? No.

Problem 1: Given a sw. fn f(x1, x2, ••• , xn), determine whether or not it is a threshold fn. and if it is, find weights and a threshold.

Problem 2: If the given sw. fn is not a threshold fn, how many threshold elements are required to realized the given sw. fn.

Properties: A fn f(x1, x2, ••• , xn) is positive in a var xi iff

f(x1, x2, ••• , xi-1, 1, xi+1, ••• , xn) f(x1, x2, ••• , xi-1, 0, xi+1, ••• , xn)

A fn f(x1, x2, ••• , xn) is negative in a var xi iff

f(x1, x2, ••• , xi-1, 0, xi+1, ••• , xn) < f(x1, x2, ••• , xi-1, 1, xi+1, ••• , xn)

A fn which is positive or negative in every var is called unate.

positive unate : positive in every var negative unate : negative in every var

A completely specified fn is unate iff any minimal S. of P. representation of the fn uses either literal xi or literal xi’ but not both for 1 i n.

Eg) f(x1, x2, x3) = (0,1,3) = x1’x2’+x1’x3’(unate), x1’x2+x1x2’(not unate)

11

110

10110100 x1x2 x3

Theorem: all threshold functions are unate.

Proof: let f(x1, x2, ••• , xn) be a non unate fn. Suppose it is a threshold fn then there should be some xi such that f is neither positive or negative in xi. Since f ins non unate, there

exist some input combination, say (a1, a2, ••• , an) such that

f(a1, a2, ••• , ai-1, 0, ai+1, ••• , an) = 1

f(a1, a2, ••• , ai-1, 1, ai+1, ••• , an) = 0

and some input combination say (b1, b2, ••• , bn) such that

f(b1, b2, ••• , bi-1, 0, bi+1, ••• , bn) = 0

f(b1, b2, ••• , bi-1, 1, bi+1, ••• , bn) = 1

Wi<0

n

ikkikk

n

ikk

biikk

n

kkk

n

ikkkk

n

ikk

biikk

n

kkk

TwbwbwbwTbw

TbwbwbwTbw

i

i

,1,1

1

1

,1,1

0

1 Wi>0

n

ikkikk

n

ikk

aiikk

n

kkk

n

ikkkk

n

ikk

aiikk

n

kkk

TwawawawTaw

TawawawTaw

i

i

,1,1

1

1

,1,1

0

1

contradiction

Theorem: Not all unate function are a threshold fn.

Proof) We need to give one example, consider f(x1, x2, x3, x4) = (3,7,11,12,13,14,15) = x1x2+x3x4 unate fn

f(1,1,0,0)=1 w1+w2 T

f(1,0,1,0)=0 w1+w3 < T

f(0,0,1,1)=1 w3+w4 T

f(0,1,0,1)=0 w2+w4 < T

contradiction!! The given fn is not a threshold fn.

Consider that fn f(x1, x2, ••• , xn) is realized by V1= {w1, w2, ••• , wn; T} whose inputs are x1, x2, ••• , xn. If one of input, say xj, is complemented, the function can be realizable by a single threshold element having a weight-threshold vector.

V2= {w1, w2, •••, -wj, ••• , wn; T-wj} whose inputs are x1, x2, •••, -xj, ••• , xn.

01

00

10110100 x1x2 x3x4

1

1

1

1111

10

11

w1+w2>w1+w3 w2>w3

w3+w4>w2+w4 w3>w2

w1 ••• wj ••• wn

Tx1 ••• xj ••• xn

fw1 ••• -wj ••• wn

T-wj

x1 ••• xj ••• xn

g

We have to prove that f and g are identical fn.

n

jiijiijj

n

kkk

n

jiijiijj

n

iii

gwTxwxwfTaw

gwTxwxwfTxw

,11

,11

0')(0

1')(1

Case 1: xj=0 (xj’=1)

left side (f) right side (g)

n

jiiiijj fTxwwx

,1

10

n

jiijiijj gwTxwxw

,1

1)(1

n

jiiiijj fTxwwx

,1

00

n

jiijiijj gwTxwxw

,1

0)(1

Case 1: xj=1 (xj’=0)

left side (f) right side (g)

n

jiiiijj fTxwwx

,1

11

n

jii

n

jiiiijjii gTxwwwTxw

,1 ,1

1

n

jiiiijj fTxwwx

,1

01

n

jiiii

n

jiijjii gTxwwwTxw

,1,1

0

Therefore, f and g are identical.

If a function is realizable by a single threshold element (i.e. threshold function) then by an appropriate selection of complemented and uncomplemented input variables, it is realizable by an threshold element whose weight have any desired sign distribution.

Let a threshold fn f(x1, x2, ••• , xn) be positive in var xi and the weight-threshold vector

V= {w1, w2, ••• , wn; T}

,since f is positive in var xi, there exists a set of values

a1, a2, ••• , ai-1, ai+1, ••• , an for inputs x1, x2, ••• , xi-1, xi+1, ••• , xn such that

f(a1, a2, ••• , ai-1, 1, ai+1, ••• , an) = 1 and f(a1, a2, ••• , ai-1, 0, ai+1, ••• , an) = 0

Hence,

w1a1+w2a2+ ••• + wi-1ai-1+wi+wi+1ai+1+ ••• +wnan T and w1a1+w2a2+ ••• + wi-1ai-1 +wi+1ai+1+ ••• +wnan < T

®wi>0

The weight wi associated with a threshold function which is positive in var xi, is positive.

ÞThe weights associated with a threshold function which is a positive in all its vars, are all positive.

If a function f(x1, x2, ••• , xn) is threshold fn with V1= {w1, w2, ••• , wn; T}, is the complement f ’(x1, x2, ••• , xn) a threshold fn? Then what is weigh-threshold vector, V2?

We assume that the weighted sum is not equal to T for any input combination

wixi>T f=1wixi<T f=0 multiply by (-1) to each side.

(-wi)xi<-T f=1 (f ’=0) (-wi)xi>-T f=0 (f ’=1)

V2= {-w1, -w2, ••• , -wn; -T}

Linear separability

If we use the n-cube representation for n-var threshold functions and regard the vertices as points in n-D space,

w1x1+w2x2+ ••• +wnxn = T

Correspond to an (n-1)-D hyperspace which cuts through the n-cube.

Now, if w1x1+w2x2+ ••• +wnxn T then f=1, if w1x1+w2x2+ ••• +wnxn < T then f=0, the hyper plane separates the true vertices from the false vertices Threshold function = linearly separable function.

If n=2, w1x1+w2x2=T

x1

x2

If n=3, w1x1+w2x2 +w3x3=T Plane equation

x2

x3

x1

True vertices

x2

x3

x1

Linear equation

False vertices

XOR function

0110

0 0 0 1 1 0 1 1

fx1 x2

OR function

0111

0 0 0 1 1 0 1 1

fx1 x2

x1

x2

x1

x2

(1,0) (1,0)(0,0)

(1,1)(1,1) (0,1)

(0,0)

(0,1)

separableNot separable XOR isn’t threshold function We can separate between

true and false vertices

Our objective is to present a procedure which will determine whether a given sw fn is a threshold fn, and if it is, will provide the value of weights and threshold

1. Test the given fn for unateness. convert to a positive unate fn

2. Try to find only positive weights for a positive unate fn using minimal true vertices and maximal false vertices.

3. Convert to original inputs and adjust weights and threshold.

Ex) f(x1, x2, x3, x4) = (0,1,4,5,6,7,8,9,11,12,13,14,15)

01

00

10110100 x1x2 x3x4

1111

1111

11

111

10

11

f = x2+x3’+x1x4

We can say

positive unate in x1, x2, x4 negative unate in x3

Let g(y1, y2, y3, y4) = f(x1, x2, x3’, x4) then

g(y1, y2, y3, y4) = y2+y3+y1y4

Minimal true vertices of a positive unate fn: any true vertex, say (a1, a2, ••• , an) such that there is no other true vertex, say (b1, b2, ••• , bn) such that

(b1, b2, ••• , bn) < (a1, a2, ••• , an)

Maximal false vertices of a positive unate fn: any false vertex, say (a1, a2, ••• , an) such that there is no other false vertex, say (b1, b2, ••• , bn) such that

(b1, b2, ••• , bn) > (a1, a2, ••• , an)

01

00

10110100 y1y2 y3y4

111

11

1111

1111

10

11

false vertices

0000 0001

1000

true vertices

0010 0011 0100 0101 0111 1001 1010

1011 1100

1101 1110 1111

Tmaximal false vertices minimal

true vertices

f 0 wixi < T

f 1 wixi T

w4 w1

w3 w2 w1+w4

T

Conti. example) w4<w3 w4<w2

w4<w1+w4 w1<w3 w1<w2

If we choose, w3=4, w4=2, w1=2, and w2=4

Ex) f(x1, x2, x3, x4) = (0,1,3,4,5,6,7,12,13)

01

00

10110100 x1x2 x3x4

111

111

1

11

10

11

f = x1’x2+x1’x3’+x1’x4+x2x3’

positive unate in x2, x4 negative unate in x1, x3

Let g(y1, y2, y3, y4) = f(x1’, x2, x3’, x4) then

g(y1, y2, y3, y4) = y1y2+y1y3+y1y4+y2y3

2 4 -4 2

3 3-4 fy1 y2 y3 y4

x1 x2 x3 x4

2 4 4 2

01

00

10110100 y1y2 y3y4

11

1

111

111

10

11

false vertices

1000 0101 0100 0011 0010 0001

0000

true vertices

0110 0111 1001 1010 1011 1100 1101

1110 1111

T

w1 w2+w4

w3+w4

w2+w3 w1+w4 w1+w3

w1+w2

T

w1<w2+w3 w2+w4<w2+w3 w2<w1 w2+w4<w1+w3

w4 <w1 w4<w2

w3 <w1

w3+w4<w1+w2

w1>w2,w3,w4

w4<w3

If we choose, w1=6, w2=5, w3=4, w4=2, and T=8

6 5 4 2

8 -2 fy1 y2 y3 y4

x1 x2 x3 x4

-6 5 -4 2