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EECS 247 Lecture 24: Oversampling Data Converters © 2005 H. K. Page 1

EE247Lecture 24

Oversampled ADCs– Why oversampling?– Pulse-count modulation– Sigma-delta modulation

• 1-Bit quantization• Quantization error (noise) spectrum• SQNR analysis• Limit cycle oscillations

– 2nd order ΣΔ modulator• Dynamic range • Practical implementation

– Effect of various nonidealities on the ΣΔ performance


The Case for OversamplingNyquist sampling:

Oversampling:

• Nyquist rate fN = 2B• Oversampling rate M = fs/fN >> 1

fs >2B +δFreqB

Signal

“narrow”transition

SamplerAA-Filter

“Nyquist”ADC DSP

=MFreqB

Signal

“wide”transition

SamplerAA-Filter

OversampledADC DSP

fs

fs fN

fs >> fN??


Nyquist v.s. Oversampled ConvertersAntialiasing

|X(f)|

frequency

frequency

frequency

fB

fB 2fs

fB fs

Input Signal

Nyquist Sampling

Oversampling

fS ~2fB

fS >> 2fB

fs

Anti-aliasing Filter


Oversampling Benefits• No stringent requirements imposed on analog

building blocks • Takes advantage of the availability of low

cost, low power digital filtering• Relaxed transition band requirements for

analog anti-aliasing filters• Reduced baseband quantization noise power• Allows trading speed for resolution


ADC ConvertersBaseband Noise

• For a quantizer with step size Δ and sampling rate fs :– Quantization noise power distributed uniformly across Nyquist

bandwidth ( fs/2)

– Power spectral density:

– Noise is aliased into the Nyquist band –fs /2 to fs /2

2 2

es s

e 1N ( f )

f 12 f

⎛ ⎞Δ= = ⎜ ⎟

⎝ ⎠

-fB f s /2-fs /2 fB

Ne(f)

NB


Oversampled ConvertersBaseband Noise

B B

B B

f f 2

B ef f s

2B

s

B s2

B0

B B0B B0

ss

B

1S N ( f )df df

12 f

2 f12 f

where for f f / 2

S12

2 f SS S

f Mf

where M oversampling rat io2 f

− −

⎛ ⎞Δ= = ⎜ ⎟

⎝ ⎠

⎛ ⎞Δ= ⎜ ⎟⎜ ⎟

⎝ ⎠

=Δ

=

⎛ ⎞= =⎜ ⎟⎜ ⎟

⎝ ⎠= =

∫ ∫

-fB f s /2-fs /2 fB

Ne(f)

NB


Oversampled ConvertersBaseband Noise

2X increase in M3dB reduction in SB½ bit increase in resolution/octave oversampling

B B0B B0

ss

B

2 f SS S

f Mf

where M oversampling rat io2 f

⎛ ⎞= =⎜ ⎟⎜ ⎟

⎝ ⎠= =

To increase the improvement in resolution: Embed quantizer in a feedback loop

Predictive (delta modulation)Noise shaping (sigma delta modulation)


Pulse-Count Modulation

Vin(kT) Nyquist ADC

t/T0 1 2

OversampledADC, M = 8

t/T0 1 2

Vin(kT)

Mean of pulse-count signal approximates analog input!


Pulse-Count Spectrum

f

Magnitude

• Signal: low frequencies, f < B << fs• Quantization error: high frequency, B … fs / 2• Separate with low-pass filter!


Oversampled ADCPredictive Coding

• Quantize the difference signal rather than the signal itself• Smaller input to ADC Buy dynamic range• Only works if combined with oversampling• 1-Bit digital output• Digital filter computes “average” N-Bit output

+

_vIN

DOUT

Predictor

ADC


Oversampled ADC

Decimator:• Digital (low-pass) filter• Removes quantization error for f > B• Provides most anti-alias filtering• Narrow transition band, high-order• 1-Bit input, N-Bit output (essentially computes “average”)

fs= MfN

FreqB

Signal“wide”

transition

SamplerAnalogAA-Filter

E.g.Pulse-CountModulator

Decimator“narrow”transition

fs1= M fN

DSP

Modulator DigitalAA-Filter

fs2= fN+ δ

1-Bit Digital N-BitDigital


Modulator

• Objectives:– Convert analog input to 1-Bit pulse density stream– Move quantization error to high frequencies f >>B– Operates at high frequency fs >> fN

• M = 8 … 256 (typical)….1024• Since modulator operated at high frequencies need to

keep circuitry “simple”

ΣΔ = ΔΣ Modulator


Sigma- Delta ModulatorsAnalog 1-Bit ΣΔ modulators convert a continuous time analog input vIN into a 1-Bit sequence dOUT

H(z)+

_vIN dOUT

Loop filter 1b Quantizer (comparator)

fs

DAC


Sigma-Delta Modulators• The loop filter H can be either switched-capacitor or continuous time• Switched-capacitor filters are “easier” to implement + frequency

characteristics scale with clock rate• Continuous time filters provide anti-aliasing protection• Loop filter can also be realized with passive LC’s at very high frequencies

H(z)+

_vIN

dOUT

fs

DAC


Oversampling A/D Conversion

• Analog front-end oversampled noise-shaping modulator• Converts original signal to a 1-bit digital output at the high rate of

(2MXB)• Digital back-end digital filter

• Removes out-of-band quantization noise• Provides anti-aliasing to allow re-sampling @ lower sampling rate

1-bit@ fs

n-bit@ fs /M

Input Signal Bandwidth

B=fs /2MDecimation

FilterOversampling

Modulator

fs

fs = sampling rateM= oversampling ratio

fs /M


1st Order ΣΔ ModulatorIn a 1st order modulator, simplest loop filter an integrator

+

_vIN dOUT∫

H(z) =z-1

1 – z-1

DAC


1st Order ΣΔ ModulatorSwitched-capacitor implementation

Vi

-

+

φ1 φ2 φ2

1,0dOUT

+Δ/2

-Δ/2


1st Order ΔΣ Modulator

• Properties of the first-order modulator:– Analog input range is equal to the DAC reference– The average value of dOUT must equal the average value of vIN– +1’s (or –1’s) density in dOUT is an inherently monotonic function of vIN

linearity is not dependent on component matching– Alternative multi-bit DAC (and ADCs) solutions reduce the quantization error

but loose this inherent monotonicity & relaxed matching requirements

+

_vIN

dOUT

∫-Δ/2≤vIN≤+Δ/2

DAC-Δ/2 or +Δ/2


1st Order ΣΔ Modulator

Instantaneous quantization error

Tally of quantization error

1-Bitquantizer

1-Bit digital output stream,

-1, +1

Implicit 1-Bit DAC+Δ/2, -Δ/2

(Δ = 2)

Analog input-Δ/2≤Vin≤+Δ/2

3Y

2Q

1X

Sine Wave

z -1

1-z -1Integrator Comparator

• M chosen to be 8 (low) to ease observability


1st Order Modulator Signals

T = 1/fs = 1/ (M fN)

X analog inputQ tally of q-errorY digital/DAC output

Mean of Y approximates X

0 10 20 30 40 50 60

-1.5

-1

-0.5

0

0.5

1

1.5

Time [ t/T ]

Am

plitu

de

1st Order Sigma-DeltaXQY


ΣΔ Modulator Characteristics• Quantization noise and thermal noise (KT/C)

distributed over –fs /2 to +fs /2Total noise within signal bandwidth reduced by

1/M• Very high SQNR achievable (> 20 Bits!)• Inherently linear for 1-Bit DAC• To first order, quantization error independent

of component matching• Limited to moderate & low speed


Output Spectrum• Definitely not white!

• Skewed towards higher frequencies

• Notice the distinct tones

• dBWN (dB White Noise) scale sets the 0dB line at the noise per bin of a random -1, +1 sequence

Input

0 0.1 0.2 0.3 0.4 0.5-50

-40

-30

-20

-10

0

10

20

30

Frequency [ f /fs]

Am

plitu

de

[ dB

WN

]


Quantization Noise Analysis

• Sigma-Delta modulators are nonlinear systems with memory difficult to analyze directly

• Representing the quantizer as an additive noise source linearizes the system

Integrator

ΣQuantizer

Model

QuantizationError e(kT)

x(kT) y(kT)1

1H( )1

zzz

−

−=+ Σ


Signal Transfer Function

( )

1

1

0

H( )1

zzz

H jjωωω

−

−=+

=

Signal transfer function low pass function:

IntegratorH(z)Σ

x(kT)y(kT)

-

Frequency

Mag

nitu

de

f0

( )

( )0

1

1 1

( ) ( ) Delay( ) 1 ( )

Sig

Sig

H j s

Y z H zH z zX z H z

ωω

−

=+

= = = ⇒+


Noise Transfer FunctionQualitative Analysis

2eqv

22

0n

fv f⎛ ⎞× ⎜ ⎟⎝ ⎠

Σvi

-vo0

jωω

22 2

0eq n

fv v f⎛ ⎞= × ⎜ ⎟⎝ ⎠

Σvi -vo0

jωω

Frequencyf0

2nv

Σvi

-vo0

jωω

2 2

0eq n

fv v f⎛ ⎞= × ⎜ ⎟⎝ ⎠

• Input referred-noise zero @ DC (s-plane)


STF and NTF

Signal transfer function:1( ) ( )STF Delay

( ) 1 ( )Y z H z zX z H z

−= = = ⇒+

Noise transfer function:

erentiator Diff 1)(1

1)()(NTF 1 ⇒−=

+== −z

zHzEzY

Integrator

ΣQuantizer

Model

QuantizationError e(kT)

x(kT) y(kT)1

1H( )1

zzz

−

−=+ Σ


Noise Transfer Function

( )( )

( ) ( )

( ) ( )

1

/ 2 / 2/ 2

/ 2

/ 2 / 2

/ 2

( ) 1 1 ( ) 1 ( )

( ) (1 )=22

2 sin / 2

2 sin / 2

2sin / 2

where 1/Thus:

( ) =2 sin / 2 =2 sin /

( )

j T j Tj T j T

j T

j T j

j T

s

s

y

Y zNTF zE z H z

e eNTF j e e

e j T

e e T

T e

T f

NTF f T f f

N f

ω ωω ω

ω

ω π

ω π

ω

ω

ω

ω

ω π

−

−− −

−

− −

− −

= = = −+

⎛ ⎞−= − ⎜ ⎟⎝ ⎠

=

= × ⎡ ⎤⎣ ⎦

= ⎡ ⎤⎣ ⎦=

= 2( ) ( )eNTF f N f


First Order ΣΔ ModulatorNoise Transfer Characteristics

( )

2

2

( ) ( ) ( )

4 sin /

y e

s

N f NTF f N f

f fπ

=

=

Noi

se S

hapi

ng F

unct

ion

FrequencyfB fN fs /2

First-Order Noise Shaping

Low-passDigital Filter

Key Point:Most of quantization noise pushed out of frequency band of interest


First Order ΣΔ ModulatorSimulated Noise Transfer Characteristic

0 0.1 0.2 0.3 0.4 0.5-50

-40

-30

-20

-10

0

10

20

30

Frequency [f/fs]

Ampl

itude

[ d

BW

N ]

Simulated output spectrumComputed NTF

Signal

( ) 2( ) 4 sin /y sN f f fπ=


Quantizer Error• For quantizers with many bits

• Let’s use the same expression for the 1-Bit case

• Use simulation to verify validity

• Experience: Often sufficiently accurate to be useful, with enough exceptions to be very careful

( )12

22 Δ=kTe


First Order ΣΔ ModulatorIn-Band Quantization Noise

( )( ) ( )

( ) ( )

( )

2

2

2

1

2 2

2

2 2

2 2

3

1

4 sin / for 1

1 2sin12

13 12

jfT

fsM

fsM

s

B

Y Q z eB

s

Y

NTF z z

NTF f f f M

S S f NTF z df

fT dff

SM

π

π

π

π

−

−

=−

= −

= >>

=

Δ≅

Δ→ ≈

∫

∫


Dynamic Range

M DR16 33 dB32 42 dB

1024 87 dB

2

2 2

3

32

32 2

peak signal power10log 10logpeak noise power

1 sinusoidal input, 12 2

13 129

29 910log 10log 30log

2 2

3.4 30l

X

Y

X

Y

X

Y

SDRS

S STF

SM

S MS

DR M M

DR dB

π

π

π π

⎡ ⎤⎡ ⎤= = ⎢ ⎥⎢ ⎥⎣ ⎦ ⎣ ⎦

Δ⎛ ⎞= =⎜ ⎟⎝ ⎠

Δ=

=

⎡ ⎤ ⎡ ⎤= = +⎢ ⎥ ⎢ ⎥⎣ ⎦ ⎣ ⎦

= − + + og M

2X increase in M 9dB (1.5-Bit) increase in dynamic range


Oversampling and Noise Shaping

• ΣΔ modulators have interesting characteristics– Unity gain for input signal VIN– Large in-band attenuation of quantization noise injected at quantizer

input– Performance significantly better than 1-Bit noise performance possible

for frequencies << fs

• Increase in oversampling (M = fs/fN >> 1) improves SQNR considerably– 1st order ΣΔ: DR increases 9dB for each doubling of M– To first order, SQNR independent of circuit complexity and accuracy

• Analysis assumes that the quantizer noise is “white”– Not true in practice, especially for low-order modulators– Practical modulators suffer from other noise sources also

(e.g. thermal noise)


DC Input

• DC input A = 1/11

• Doesn’t look like spectrum of DC at all

• Tones frequency shaped the same as quantization noise

More prominent at higher frequencies

Seems like periodic quantization “noise”

0 0.1 0.2 0.3 0.4 0.5-50

-40

-30

-20

-10

0

10

20

30

Frequency [ f /fs ]

Am

plitu

de

[ dB

WN

]


Limit Cycle

-111+110-19+18-17+16-15+14-13+12+11

DC input 1/11 Periodic sequence:

0 10 20 30 40 50

-0.4

-0.2

0

0.2

0.4

0.6

Time [t/T]

Out

put

First order sigma-delta, DC input


Limit Cycle

In-band spurious tone with f ~ DC input

• Problem: quantization noise is periodic•Solution:

Use dithering: randomizes quantization noise- Thermal noise acts as dither

Second order loop

Noi

se S

hapi

ng F

unct

ion

FrequencyfB fN fs /2


Ideal Low-passDigital Filter



( )1 1( ) ( ) 1 ( ) Y z z X z z E z− −= + −


2nd Order ΣΔ Modulator

• Two integrators• 1st integrator non-delaying• Feedback from output to both integrators• Tones less prominent compared to 1st order


2nd Order ΣΔ Modulator

( )

( )1 1 2

21 1 1

Recursive drivation: 2

Using the delay operator : ( ) ( ) 1 ( )

n n n n nY X E E E

z Y z z X z z E z

− − −

− − −

= + − +

= + −


2nd Order ΣΔ ModulatorIn-Band Quantization Noise

( )

( ) ( )( )

( )

1

1

21

2

44

11

1

2 sin / for 1s

zH zz

G

NTF z z

NTF f

f f Mπ

−

−

−

=−

=

= −

=

= >>

( ) ( )

( )

2

2

2

2

24

4 2

5

1 2sin12

15 12

jfT

fsM

fsM

B

Y Q z eB

s

S S f NTF z df

fT dff

M

π

π

π

−

=−

=

Δ≅

Δ≈

∫

∫


Quantization Noise2nd Order ΣΔ Modulator

Noi

se S

hapi

ng F

unct

ion

FrequencyfB fs /2


Ideal Low-passDigital Filter

2nd -Order Noise Shaping


2nd Order ΣΔ Modulator Dynamic Range

M DR16 49 dB32 64 dB

1024 139 dB

2

4 2

5

54

54 4

peak signal power10log 10logpeak noise power


15 1215

215 1510log 10log 50log

2 2

11.1

X

Y

X

Y

X

Y

SDRS

S STF

SM

S MS

DR M M

DR dB

π

π

π π

⎡ ⎤⎡ ⎤= = ⎢ ⎥⎢ ⎥⎣ ⎦ ⎣ ⎦

Δ⎛ ⎞= =⎜ ⎟⎝ ⎠

Δ=

=

⎡ ⎤ ⎡ ⎤= = +⎢ ⎥ ⎢ ⎥⎣ ⎦ ⎣ ⎦

= − + 50log M+

2X increase in M 15dB (2.5-bit) increase in DR


2nd Order ΣΔ Modulator Example

M 256=28 to allow some margin & also for ease of digital filter implementation

Sampling rate (2x20kHz + 5kHz)M = 12MHz

•Digital audio application•Signal bandwidth 20kHz•Resolution 16-bit

min

16 98 Dynamic Range

11.1 50log153

bit dB

DR dB MM

− →

= − + +=


Higher Order ΣΔ Modulator Dynamic Range

2X increase in M (6L+3)dB or (L+0.5)-bit increase in DR

( )

( )

( )

( )

1 1

2

2 2

2 1

2 12

2 12

2

( ) ( ) 1 ( ) , L order


12 1 123 2 1

23 2 1

10log2

3 2 110log 2

2

L

X

L

Y L

LXL

Y

LL

L

Y z z X z z E z

S STF

SL M

LS MS

LDR M

LDR

π

π

π

π

− −

+

+

+

⎛ ⎞⎜ ⎟⎝ ⎠

⎡ ⎤⎢ ⎥⎢ ⎥⎣ ⎦

⎡ ⎤⎢ ⎥⎢ ⎥⎣ ⎦

= + − → ΣΔ

Δ= =

Δ=+

+=

+=

+= + ( )1 10 logL M+ × ×


ΣΔ Modulator Dynamic RangeAs a Function of Modulator Order

• Potential stability issues for L >2

L=2

L=3

L=1


Tones in 1st Order & 2nd Order ΣΔ Modulator

• Higher oversampling ratio lower tones

• 2nd order much lower tones compared to 1st

• 2X increase in M decreases the tones by 6dB for 1st order loop and 12dB for 2nd order loop

Ref: B. P. Brandt, et al., "Second-order sigma-delta modulation for digital-audio signal acquisition,"

IEEE Journal of Solid-State Circuits, vol. 26, pp. 618 - 627, April 1991.R. Gray, “Spectral analysis of quantization noise in a single-loop sigma–delta modulator with dc

input,” IEEE Trans. Commun., vol. 37, pp. 588–599, June 1989.

6dB

12dB 2nd Order ΣΔ Modulator



2nd Order ΣΔ ModulatorSwitched-Capacitor Implementation

IN Dout


Switched-Capacitor Implementation 2nd Order ΣΔPhase 1

•Sample inputs•Compare output of 2nd integrator•At the end of phase1, S3 opens prior to S1 opening


Switched-Capacitor Implementation 2nd Order ΣΔPhase 2

• Enable feedback from output to input of both integrators• Integrate• Reset comparator• At the end of phase2 S4 opens before S2


ΣΔ ImplementationPractical Design Considerations

• Internal nodes scaling & clipping

• Finite opamp gain & linearity

• Capacitor ratio errors

• KT/C noise

• Opamp noise

• Power dissipation considerations


Switched-Capacitor Implementation 2nd Order ΣΔNodes Scaled for Maximum Dynamic Range

• Modification (gain of ½ in front of integrators) reduce & optimize required signal range at the integrator outputs ~ 1.7x input full-scale (Δ)

Ref: B.E. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation A/D Converters,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1298-1308, Dec. 1988.


2nd Order ΣΔ ModulatorSwitched-Capacitor Implementation

C2=2C1

• The ½ loss in front of each integrator implemented by choice of:


2nd Order ΣΔEffect of Integrator Maximum Signal Handling Capability on SNR

• Effect of 1st Integrator maximum signal handling capability on converter SNRRef: B.E. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation A/D Converters,”

IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1298-1308, Dec. 1988.


2nd Order ΣΔEffect of Integrator Maximum Signal Handling Capability on SNR

• Effect of 2nd Integrator maximum signal handling capability on SNRRef: B.E. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation A/D Converters,”



2nd Order ΣΔEffect of Integrator Finite DC Gain

Vi

-

+

φ1 φ2

aVo

Cs

CI( )

( )

1

1

1

1

1

1

111

ideal

Finit DC Gain

Cs zH zCI z

a zCsaCs CIH zCI

a zCsaCI

−

−

−

−

= ×−⎛ ⎞⎜ ⎟⎜ ⎟

+ +⎜ ⎟⎝ ⎠= ×⎛ ⎞⎜ ⎟+− ⎜ ⎟

+ +⎜ ⎟⎝ ⎠



• Low integrator DC gain Increase in total in-band noise • Can be shown: If a > M (oversampling ratio) Insignificant degradation in

SNR• Normally DC gain designed to be >> M in order to suppress nonlinearities

f0 /a

a

0P1 aω=

0ω

a

( )log H s Ideal Integ. (a=infinite)

Integrator magnitude response

Max signal level



• Example: a =2M 0.4dB degradation in SNRRef: B.E. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation A/D Converters,”


M / a


2nd Order ΣΔEffect of Integrator Overall Integrator Gain Inaccuracy

• Gain of ½ in front of integrators determined by ratio of C1/C2

• Effect of inaccuracy in ratio of C1/C2 inspected by simulation


2nd Order ΣΔEffect of Integrator Overall Gain Inaccuracy

• Simulation show gain can vary by 20% w/o loss in performanceConfirms insensitivity of ΣΔ to component variations

• Note that for gain >0.65 system becomes unstable & SNR drops rapidly


2nd Order ΣΔEffect of Integrator Nonlinearities

2 32 3

2 32 3

v( kT T ) u(kT ) v( kT )

With non-linearity added:

v( KT T ) u(kT ) .....u(kT ) u(kT )v( kT ) ....v( kT ) v( kT )

α αβ β

⎡ ⎤ ⎡ ⎤⎣ ⎦ ⎣ ⎦

⎡ ⎤ ⎡ ⎤⎣ ⎦ ⎣ ⎦

+ = +

+ = + +

+ + + +

Ref: B.E. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation A/D Converters,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1298-1308, Dec. 1988

Delay

Ideal Integrator

u(kT) v(kT)




• Simulation for single-ended topology• Even order nonlinearities can be significantly attenuated by using

differential circuit topologies

2 20.01, 0 .02,0.05, 0.1%

α β= =




• Simulation for single-ended topology• Odd order nonlinearities (3rd in this case)

3 30.05, 0.2, 1%

α β= =

6dB 1=Bit