Transcript

DEPARTMENT OF COMPUTER SCIENCE

PI/4 DQPSK Modem Implementation

Muhammad Zuhair Arfeen

A dissertation submitted to the University of Bristol in accordance with the requirements

of the degree of Master of Science in the Faculty of Engineering

September 2008 CSMSC-08

Declaration A dissertation submitted to the University of Bristol inaccordance with the requirements of the degree of Master of Science inthe Faculty of Engineering. It has not been submitted for any otherdegree or diploma of any examining body. Except wherespecifically acknowledged, it is all the work of the Author.

Muhammad Zuhair Arfeen, September 2008

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ABSTRACT

The project undertaken has made a comprehensive review of digital modulation and demodulation techniques and it has two phases of implementation. The 1st phase is real-time implementation of phase lock loop for carrier phase synchronisation between transmitter and receiver. The 2nd phase is real-time synchronisation of transmitter DSP board and receiver DSP board so as to inform the receiver about the start of data. The modulator and demodulator use pi/4 DQPSK scheme and the implementation is carried out on TI’s DSP platformTMS320C6416.

When the carrier is transmitted in channel, it undergoes delays. The receiver must know exact timing delays for perfect operation and demodulation. Various techniques for carrier phase synchronisation are studied which include deriving carrier phase from unmodulated carrier or using modulated signal for carrier phase estimate including decision directed and non decision directed loops. Finally classical analogue phase lock loop is implemented in real-time as it simplifies receiver circuitry and is commonly used in mobile cellular environment.

Synchronisation is achieved in real-time by transmitting a training sequence known at the receiver. The receiver first detects the training sequence and then it starts decoding the data. The receiver used is correlator receiver and look up tables are used for pi/4 DQPSK modulation and demodulation. The receiver is working satisfactory with out employing Symbol Timing Recovery (STR) Loop as the final data is decoded absolutely on the basis of correlated sum. When the correlated sum is positive decision is made in favour of binary ‘1’ and when the correlated sum is negative decision is made in favour of binary ‘0’.

Phase lock loop is working satisfactory at varying input frequencies and at different sampling frequencies provided Nyquist rule of sampling is followed. Synchronisation is achieved in real-time for a frequency of 100 Hz which can be increased up to 480 Hz, but the receiver gets unsynchronized from transmitter for more than expected time. The remedy proposed is use of error correction and detection scheme which is an essential component in any communication system.

Another future development proposed is use of VOCODER (Voice Coder and Decoder) for upgrading the MODEM to Voice grade MODEM. VOCODER uses PCM / ADPCM to compress the data and decrease the data rate, so that DSP board can handle real-time voice easily.

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ACKNOWLEDGEMENT

The author would like to acknowledge Dr. N. Dahnoun for his supervision and constant guidance throughout the research and implementation phase.

The author would also like to thank Electrical Engineering laboratory technicians and staff for their support.

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Table of ContentsABSTRACT...........................................................................................................................................iACKNOWLEDGEMENT ...................................................................................................................ii1 Introduction ...................................................................................................................................1

1.1 Aims and Objectives .............................................................................................................21.2 Previous Work Analysis........................................................................................................21.3 Organization of thesis............................................................................................................4

2 Review of Digital Modulation Techniques .................................................................................52.1 Digital Modulation ................................................................................................................52.2 The need for Modulation.......................................................................................................52.3 Types of Digital Modulation Techniques ............................................................................5

3 System Overview........................................................................................................................203.1 Phase Lock Loop .................................................................................................................203.2 Synchronisation in pi/4 DQPSK MODEM........................................................................21

4 Carrier Phase Estimation ............................................................................................................224.1 Maximum Likelihood Carrier Phase Estimate ..................................................................234.2 Phase Lock Loop .................................................................................................................274.3 Decision directed loops.......................................................................................................294.4 Non Decision Directed Loops ............................................................................................304.5 Implementation Issues.........................................................................................................32

5 Synchronisation...........................................................................................................................345.1 Synchronisation in FSK MODEM .....................................................................................345.2 Synchronisation in pi/4 DQPSK MODEM........................................................................37

6 Future Work ................................................................................................................................416.1 Use Of VOCODER For Voice Grade Modem..................................................................416.2 Error Detection and Correction ..........................................................................................416.3 Wireless Link.......................................................................................................................416.4 Rake Receiver for Removal of Multipath Fading .............................................................42

7 Bibliography................................................................................................................................438 Appendices ..................................................................................................................................44

8.1 Appendix A IIR Filter as Oscillator ...................................................................................448.2 Appendix B Program Listing..............................................................................................47

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List of Figures(Figure 2.1 ASK Modulated wave) .....................................................................................................6(Figure 2.2 Block Diagram of ASK Modulator).................................................................................7(Figure 2.3 Block Diagram of ASK Demodulator) ............................................................................7(Figure 2.4 FSK Modulation).............................................................................................................8(Figure 2.5 FSK Modulator) ................................................................................................................9(Figure 2.6 Demodulation using Goertzel Algorithm).................................................................10(Figure 2.7 BPSK Modulator Block Diagram).................................................................................11(Figure 2.8 BPSK Demodulator Block Diagram).............................................................................12(Figure 2.9 QPSK Modulator Block Diagram).................................................................................14(Figure 2.10 QPSK Demodulator Block Diagram) ..........................................................................15(Figure 2.11 pi/4 QPSK Constellation Diagram) .............................................................................16(Figure 2.12 BER vs. Eb/No) ..............................................................................................................19(Figure 3.1 System Level Block Diagram for Implementation of Phase Lock Loop) ...................20(Figure 3.2 Synchronisation in pi/4 DQPSK MODEM)..................................................................21(Figure 4.1 Maximum Likelihood Phase Estimate with Unmodulated carrier) .............................26(Figure 4.2 Phase Lock Loop) ..........................................................................................................27(Figure 4.3 Decision Directed Feedback Loop)...............................................................................30(Figure 4.4 Mth power loop)..............................................................................................................31(Figure 8.1 IIR filter working as an oscillator).................................................................................45(Figure 8.2 Pole Zero Plot).................................................................................................................46

PI/4 DQPSK Modem Implementation

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1 Introduction

Software Defined Solutions (SDS) offer great advantage over complete hardware solutions as Software Defined Solutions are programmable and flexible. With ever changing communication protocols it is very easy to update or modify software in DSP. However, they need a front end RF circuitry. Digital Signal Processors are very cheap compared to analog counter parts. Now with fast growing digital signal processors and processing techniques it becomes almost impossible for analog signal processors to achieve the same performance.

Quadrature amplitude modulation (QAM) is a widely used technique for transmitting digital data. QAM technique is now widely used in modems based on CCITT V series. Programmable digital signal processors can provide necessary performance and throughput to implement base band modem (modulator demodulator) functions. These functions include symbol timing recovery, automatic gain control, symbol detection, pulse-shaping, and matched filters. Many of these functions were formally implemented in hardware. With the event of high-performance DSPs and the growing need for multipurpose hardware designs, many of these functions are implemented in DSP software.

Digital communication techniques are currently focus of intensive research as they provide higher signal reliability, extremely low error rates, error detection and correction. Analog counter parts are relatively faster since the speed of digital systems is limited by the input ADCs and output DACs. However, digital circuits are more reliable and can be reproduced at a lower cost than analog counter parts.

Digital modulation techniques include ASK (Amplitude Shift Keying), FSK (Frequency Shift Keying), PSK (Phase Shift Keying), MSK (Minimum Shift Keying). The choice for which modulation technique to select depends upon various factors including data rate, probability of symbol Error, transmitted Power, channel bandwidth, resistance of interfering signals and circuit complexity.

Pi/4 DQPSK (‘pi/4 Differential-Quadrature Phase Shift Keying’) is a four level modulation scheme first proposed by Baker in 1962. The technique is currently implemented in the American Digital Cellular, Japanese Handy Phone and the European TETRA systems and is used in wireless protocols as IS-95 (Interim Standard 95) and WCDMA (Wideband Code Division Multiple Access).

Pi/4 QPSK preserves the constant envelope property better than the band limited QPSK but is more susceptible to envelope variations than OQPSK. The main focus of this project is efficient implementation of pi/4 DQPSK modulation and demodulation on DSP.

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The aims of this project are:

1) To produce a comprehensive review of modulation and demodulation techniques and to implement a Pi/4 DQPSK Modem on the TMS320C6416 digital signal processor.

2) To modulate input data and transmit in real-time from one board (Transmitter) to the other board (Receiver). The receiver will synchronize with the transmitter and demodulate the input data in real-time and display it on the scope.

3) There are many issues in modulation and demodulation including clock recovery (carrier phase recovery), synchronisation between transmitter and receiver, symbol timing recovery. All of these functions minimize the error rate in the data. This project aims to review and finally implement carrier phase recovery and synchronisation between transmitter and receiver on DSP.

1.2.1 Stirrup, Rodney MSc project in year 1996 (University of Bristol)

Stirrup, Rodney covered a broad and in depth review of modulation and demodulationtechniques. Stirrup simulated signal mapping of pi/4 DQPSK technique and also covered filtering techniques. He simulated root raised cosine filter. Stirrup finally came up with implementation based on advance / retard technique. However, he has not addressed any real-time issues.

1.2.2 Hedwige, Shenal Undergraduate project in year 2007 (University of Bristol)

Hedwige has reviewed modulation and demodulation techniques. He has successfully implemented non real-time MODEM but could not synchronize two boards in real-time.

1.2.3 Bertele, ICS Undergraduate project in year 1999 (University of Bristol)

Bertele has covered Pulse shaping filters. Bertele has also implemented non real-time modulatorand demodulator but has not covered real-time implementation. Bertele has reviewed techniques for symbol timing recovery but has not implemented it. All his work is done in assembly language.

1.1 Aims and Objectives

1.2 Previous Work Analysis

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1.2.4 Webber, JL Undergraduate project in year 1996 (University of Bristol)

Webber, JL has reviewed modulation and demodulation of shift pi/4 DQPSK. Webber has covered Analog to Digital and Digital to Analog conversion issues. He has also covered root raised cosine, FIR and IIR filtering techniques. He has elaborated three different methods for modulation and demodulation of pi/4 DQPSK i.e. by algorithm, by look up table using offsets and by look up table using circular buffer. He has also covered symbol timing recovery mechanism but has not implemented it. His work is based on assembly language.

1.2.5 Weiss S., Braithwaite S. J. and Stewart R. D. Software pi/4 DQPSK Modem: A Student Project Using the TMS320-C6201 EVM Board in year 2000 (University of Southampton)

The project undertaken in not completely real-time as the input is taken as pre-stored array. However my thesis has taken input in real-time with under sampling the input before modulation. My thesis has also covered issues of carrier phase synchronisation (i.e. Phase Lock Loop) which Weiss, S. et al. have not covered. However Weiss, S. et al. have covered pulse shaping and synchronisation issues between transmitter and receiver.

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The thesis is organized into 6 chapters.

Chapter 1 defines the problem, the aim and the objectives and evaluates the work done by previous students in the area.

Chapter 2 takes a comprehensive review of digital modulation techniques and elaborates advantages, disadvantages of each of modulation techniques. It also includes block diagrams of modulator and demodulator of various modulation techniques.

Chapter 3 focuses on System Overview and describes different components in the project with specifications of input frequency, voltage levels and data rates achieved.

Chapter 4 focuses on Carrier Phase Synchronisation, with background theory of decision directed and non decision directed loops. Finally Implementation of phase lock loop is described in the chapter.

Chapter 5 focuses on Synchronisation between Transmitter and Receiver in FSK MODEM and then in pi/4 DQPSK MODEM. It explains the pseudo code of modulator and demodulator,reasons of critical decisions, frequencies and data rates at various interfaces.

Chapter 6 describes future work in connection to the thesis.

1.3 Organization of thesis

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2 Review of Digital Modulation Techniques

Modulation is a technique in which some characteristic of carrier signal (amplitude, frequency or phase) is varied based on information in the message signal to be transmitted.

Modulation is primarily used for transmission purposes. In digital modulation, digital data having discrete levels is transmitted after being imposed on the carrier signal.

Modulation serves a big advantage by reducing antenna size. Antenna size is proportional to λ/4 where ‘λ’ is the wavelength. Suppose a message signal of 1 kHz is required to transmit unmodulated. The wavelength is given by λ = c / f where ‘c’ is speed of light. So the wavelength comes out to be 300 km and antenna size corresponding to this wavelength is 75 km which is unrealistic.

For cellular communication, let’s say 1800 MHz carrier is used (used in CDMA), so the antenna length or diameter comes out to be 4 cm. Due to reduced antenna size the carrier frequency is stepped up in essentially all radio communication systems.

Typical types of Digital Modulation Techniques are:

Amplitude Shift Keying (ASK) Frequency Shift Keying (FSK) Phase Shift Keying (PSK)

2.3.1 Amplitude Shift Keying (ASK)

In Amplitude Shift Keying (ASK) binary ‘1’ is transmitted with an amplitude say ‘A1’ and binary ‘0’ is transmitted with a different amplitude say ‘A2’ which may or may not be zero as shown in figure below. In ASK phase and frequency of carrier is not varied.

2.1 Digital Modulation

2.2 The need for Modulation

2.3 Types of Digital Modulation Techniques

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(Figure 2.1 ASK Modulated wave)

2.3.1.1Advantage(s)

1) Simple circuitry for modulation and demodulation.

2.3.1.2Disadvantages

1) More noise susceptible since noise can get superimpose on one amplitude level and change it into the other amplitude level.

2) Envelope of transmitted signal is not constant so processing like power amplification becomes more difficult as it can make the signal non linear.

3) Higher power consumption since two distinct levels and power supply must be greater than both.

2.3.1.3 Modulator Block Diagram

The input data is first fed to a decision device. Based on either ‘1’ or ‘0’ the amplitude of carrier is assigned to be either A1 or A2 as shown in figure below:

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(Figure 2.2 Block Diagram of ASK Modulator)

2.3.1.4 Demodulator Block Diagram

For demodulation the received signal is correlated with the carrier having amplitude A = (A1+A2) / 2. The correlated signal is compared with a pre set threshold. If the correlation output is greater than threshold than binary ‘1’ is decoded else binary ‘0’ is decoded as shown in figure below where ‘t’ is discrete and periodic with step change of 1/Fs (sampling frequency) and frequency ‘f’ :

(Figure 2.3 Block Diagram of ASK Demodulator)

‘1’ or ‘0’

Input data

Amplitude ’A1’

Amplitude ‘A2’

1

0

XRx sig

N-1Σn=0

A cos wt

> Thr

Binary ‘1’

Binary ‘0’

1

0

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2.3.2 Frequency Shift Keying (FSK)

In frequency shift keying frequency of carrier is varied according to the message signal. Binary ‘1’ is assigned a frequency ‘f1’ whereas binary ‘0’ is assigned a different frequency ‘f2’ as shown in figure below:

(Figure 2.4 FSK Modulation)

2.3.2.1 Advantage(s)

1) Constant envelope.

2.3.2.2 Disadvantages

1) Relatively complex circuitry than ASK.

2) Probability of bit error is double than BPSK (Binary Phase Shift Keying).

3) Higher Bandwidth requirement (BW = f2 – f1)

2.3.2.3 Modulator Block Diagram

The input data is first fed to a decision device. Based on either ‘1’ or ‘0’ the frequency of carrier is assigned to be either f1 or f2 as shown in figure below:

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(Figure 2.5 FSK Modulator)

2.3.2.4 Demodulator Block Diagram

Demodulation of FSK modulated signal can be done by using Discrete Fourier Transform (DFT) or Fast Fourier Transform (FFT) but to minimize computational complexity (number of MACs), an optimized algorithm known as Goertzel Algorithm is used which is based on DFT and exploits the phase factor periodicity exp (-j2k / N) of the signal. (1)

The characteristics equations of Goertzel Algorithm are given below:

)2()1()/2cos(2)()( nQnQNknxnQ (2.1)

)2sin2(cos*)1()()(N

kjN

knQnQny

(2.2)

)2cos(*)1()(2)1()(|)(| 222

NknQnQnQnQny

(2.3)

The square of modulus is not problematic in this calculation as the concern is magnitude not phase. Where the constant coefficient ‘k’ is given by

s

in

ff

Nk * (2.4)

Where N is the number of samples in one frequency:

In figure below the feedback path is evaluated N times where as feed forward path is evaluated once as evident from above equations. Based on above output and pre-calculated coefficient (coeff = 2*cos (2πk/N)) the frequency of signal is decided.

‘1’ or ‘0’

Input data

Frequency ‘f1’

Frequency ‘f2’

1

0

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(Figure 2.6 Demodulation using Goertzel Algorithm)

2.3.2.5 Probability of Error

The probability of bit error is given by (2)

)(*5.0o

be N

EerfcP

(2.5)

2.3.3 Phase Shift Keying (PSK)

2.3.3.1 Binary Phase Shift Keying (BPSK)

In Binary Phase Shift Keying (BPSK) the phase of the carrier is varied according to the message signal. In BPSK binary ‘0’ and ‘1’ are distinguished by 180 degree phase shift.

2.3.3.1.1 Advantages

1) BPSK modulated wave has constant envelope.

+ x(n)

+

z-1

z-1

2*cos(2πk/N)+

-1

-exp(-j2πk/N)

Y(n)Q(n)

Q(n-1)

Q(n-2)

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2) Lesser Bandwidth requirement compared to FSK.

3) Lesser complex demodulation circuitry.

2.3.3.1.2 Disadvantages

1) There is 180 degree phase shift which produces non linear effects.

2) Higher bandwidth required compared to QPSK.

2.3.3.1.3 Modulator Block Diagram

(Figure 2.7 BPSK Modulator Block Diagram)

2.3.3.1.4 Demodulator Block Diagram

The received signal is correlated with carrier and if the correlator output is greater than zero then ‘1’ is detected else ‘0’ is detected.

‘1’ or

‘0’Input data

A cos wt

A cos (Wt+π)

1

0

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(Figure 2.8 BPSK Demodulator Block Diagram)

2.3.3.1.5 Probability of bit error

The Probability of bit error is calculated using likelihood function based on the fact that if zero is transmitted then one is received or vice versa.

The likelihood function of AWGN channel for 0 to be transmitted and one received given in (3) is as under,

])1(1exp[1 21 b

ooX Ex

NNf

(2.6)

The probability of error is given by,

10

1 )0|1()0( dxxfP Xe

(2.7)

)1()(*5.0)0( eo

be P

NE

erfcP (2.8)

The probability of error of BPSK is half of FSK given same bit energy (Eb).

XRx sig

N-1Σn=0

A cos wt

> 0

Binary ‘1’

Binary ‘0’

1

0

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2.3.4 Quadrature Phase Shift Keying (QPSK)

In QPSK instead of sending data bits by bits, data is coupled into two bits (dibits) and every time a dibit is transmitted. Each symbol is represented by two bits so four possible phases. The signal mapping is shown below:

(Table 2.1: Signal Mapping of QPSK)

The transmitted signal is represented by equation below:

]4

)12(cos[2)(

itTEts ci

(2.9)

Where i=1, 2, 3, 4 and E is the transmitted symbol energy per symbol and T is symbol time period. The transmitted signal is zero outside ‘T’.

Chia Liang et al, (4) have proposed a method for modulation of QPSK using cubic spline interpolation between every two neighboring values of θk. They have shown that this scheme produces spectral and power efficient modulation which can be non linearly amplified. They have also shown that pi/4 QPSK is 20% to 30% more spectrally efficient than that of GMSK (Gaussian Minimum Shift Keying) with BTb = 0.3 for attenuation between 40 dB to 70 dB.

2.3.4.1 Advantages

1) Bandwidth efficient compared to BPSK. It takes half of the bandwidth compared to BPSK.

2) It also has constant envelope.

Symbol Phase

SO (00) -3π/4

S1 (01) 3π/4

S2 (10) -π/4

S3 (11) π/4

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2.3.4.2 Disadvantages

1) Complex circuitry.

2) Zero crossings are not periodic.

3) 180 degree phase shift can occur so phase reversal is possible.

4) Probability of bit error is double than BPSK.

5) High transmission power required compared to BPSK.

2.3.4.3 Modulator Block Diagram

Input data is divided into dibits and converted into parallel through serial to parallel converter (SPC). The Even bit is multiplied by In phase carrier (cos wt) whereas the Odd bit is multiplied by Quadrature carrier (sin wt) and added together to transmit as shown in figure below:

(Figure 2.9 QPSK Modulator Block Diagram)

SPC

X

X

+

cos wt

sin wt

Tx signalinput

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2.3.4.4 Demodulator Block Diagram

The received data is correlated in parallel with In phase and Quadrature carriers. When the correlated output is positive then ‘1’ is decoded and vice versa. The even and odd channels are demultiplexed together to decode the transmitted data.

(Figure 2.10 QPSK Demodulator Block Diagram)

2.3.5 pi/4 Quadrature Phase Shift Keying (pi/4 QPSK)

pi/4 QPSK avoids 180 phase shift in QPSK by altering the constellation. If one of two consecutive dibits is sent on integral multiple of π/4 radians then the next consecutive dibit is sent on integral multiple of π/2 radians so the phase shift is π/4 or 3π/4 or -π/4 or - 3π/4. The constellation diagram is shown below:

X

cos wt

X

sin wt

N-1

Σn=0

N-1

Σn=0

> 0 or < 0

> 0 or < 0

DeMux

Rx sigBinary out

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(Figure 2.11 pi/4 QPSK Constellation Diagram)

2.3.5.1 Advantages1) There is no 180 phase reversal since it works on altering constellation.

2.3.5.2 Disadvantages1) Complex circuitry compared to QPSK.

2) Zero crossings are not uniform or periodic so use of zero crossing detector for frequency detection is not feasible.

2.3.5.3 Modulator

Since pi/4 QPSK works on altering constellation so essentially on one of two consecutive dibits it works on modulator of simple QPSK shown in fig.2.9 and on the next dibit it sends either cosine wave (when symbol is “10”) or minus of cosine wave (when symbol is “01”) or sine wave (when symbol is “11”) or minus of sine wave (when symbol is “00”).

2.3.5.4 Demodulator

On one of two consecutive dibits it works same as simple QPSK so demodulator is same as that of QPSK as shown in fig. 2.10. Even for next dibit the demodulator is same as in fig. 2.10 except that threshold is changed a bit. For detecting sine wave in phase value is zero and quadrature value is positive. For detecting minus sine wave in phase value is zero and quadrature value is negative.

I

Q

3(11)

0(00)

2(10)

1(01)

0(0,0)

1(1,0)

3(0,1)

2(-1,0)

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For detecting cosine wave in phase value is positive and quadrature value is zero. For detecting minus cosine wave in phase value is negative and quadrature value is zero.

2.3.6 pi/4 Differential Quadrature Phase Shift Keying (pi/4 DQPSK)

Xion, Fuqin et al. (10) has shown that in light or medium fading Rician channels at about 1 dB gain in Eb/No at BER = 10-4 can be achieved by using four symbol differential detection compared to two symbol differential detection. They have also shown that multiple symbol differential detection is not possible for severe fading Rician or Rayleigh channels. The signal mapping and phase change in pi/4 DQPSK in the following table:

Previous Symbol

Present symbol

00 01 10 11

00 45° 135° -135° -45°

01 45° 135° -135° -45°

10 45° 135° -135° -45°

11 45° 135° -135° -45°

(Table 2.2. Phase shift in pi/4 DQPSK Modulation)

From constellation shown in Fig. 2.11 the signal mapping is shown below:

Previous Symbol

Present symbol

00 01 10 11

11 (0,1) (-1,0) (0,-1) (1,0)

10 (-1,0) (0,-1) (1,0) (0,1)

01 (1,0) (0,1) (-1,0) (0,-1)

00 (0,-1) (1,0) (0,1) (-1,0)

(Table 2.3 Signal mapping when previous symbol is integral multiple of pi/4 phase)

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Previous Symbol

Present symbol

00 01 10 11

3 (0,1) 10 00 01 11

2 (-1,0) 00 01 11 10

1 (1,0) 11 10 00 01

0 (0,-1) 01 11 10 00

(Table 2.4 Signal mapping when previous symbol is on IQ axis)

2.3.6.1 Advantages1) No envelope variation.

2) Non coherent detection is possible.

2.3.6.2 Disadvantages1) Higher probability of error than pi/4 QPSK since because of differential nature

the error propagates in the frame.

2.3.6.3 Probability of bit error

Rappaport (5) has showed that in Flat Fading radio environment BPSK offers 2.8 dB improvement at high Eb/No and 3.0 dB improvement at low Eb/No over pi/4 DQPSK. However pi/4 DQPSK offers 3 dB increase in capacity for a given spectrum which makes it most appropriate modulation technique for in building flat fading mobile radio channels.

The Probability of bit error for QPSK signal, given in (3) is as under:

)()0(o

be N

EerfcP (2.10)

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which is double than that of BPSK. The probability of error for DQPSK signal is given as under:

)*54.0(o

be N

EerfcP (2.11)

So, DQPSK has 3dB poorer performance than coherent QPSK. For same performance Eb

has to be increase by a factor of 1.707. The probability of error for pi/4 DQPSK in AWGN (Additive White Gaussian Noise) channel as given in (5) is:

)*176.1(o

be N

EQP

(2.12)

(Figure 2.12 BER vs. Eb/No as in (3))

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3 System Overview

The project undertaken has two major portions: Carrier Phase Synchronisation using Phase Lock Loop and Synchronisation of Transmitter and Receiver using Training Sequence. Both the systems are not integrated because of lack of time.

(Figure 3.1 System Level Block Diagram for Implementation of Phase Lock Loop)

The input is taken in real-time from function generator as sinusoid of 1 kHz frequency, 1 V (pk-pk) amplitude but the phase of input is random. The PLL works at frequency of 1 kHz and can work for any frequency but the coefficients (calculated from Matlab simulations and DSP simulations) need to be changed accordingly. The sampling frequency used in implementation is 24 kHz, but the phase lock loop can be shown to be operational for any sampling frequency. Generally, the higher the sampling frequency, the more samples are there for phase offset calculations so better performance is achieved. But increased sampling rate, increases clock rate of CODEC so power consumption is increased which is an important performance issue in cellular devices. The DSP TMS320C6416 can work for sampling frequencies of 8 kHz, 16 kHz, 24 kHz, 44 kHz and 96 kHz. It is not possible for it to sample for more than 96 ksamples/sec.

For correct operation of PLL, the phase difference between incoming carrier and on board VCO (voltage controlled oscillator) must be small. For the implementation the PLL work satisfactory for phase difference of up to ±90 degrees. During the initial phase of implementation it was assumed that phase difference is within the range of ±90 degrees, but the results achieved were not satisfactory. So a remedial action was taken and it was ensured that the corrective action will be taken provided phase difference is small. This is a key difference between real-time input and on board stored input, because the phase of on board input is controllable but real-time input is random.

3.1 Phase Lock Loop

Function Generator

PC

OscilloscopeDSP Output

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(Figure 3.2 Synchronisation in pi/4 DQPSK MODEM)

The communication system between transmitter (DSP1) and receiver (DSP2) is wired and simplex. The input in pure sinusoid at frequency of 100 Hz and has an amplitude of 1 V (pk-pk). The MODEM can be upgraded to voice graded MODEM using VOCODER, which is left as further work to the project. VOCODER compresses the input and is an essential component of mobile communication system.

The sampling frequency used is 96 kHz with 24 samples to represent the unmodulated carrier (sine or cosine). The maximum input frequency achievable is 200 Hz which can be increased to 480 Hz with 5 samples to represent the unmodulated carrier. The relevant calculations are shown in section 5.2.3.

The reason for low frequency system is that every sample of input from function generator is represented by 16 bits (because ADC is of 16 bits). So against a single sample there is a need for 16 bits transmission and each bit (or in case of QPSK ‘dibit’) is represented by 24 samples. So, in real-time there is an inherent under sampling ratio of (number of bits / sample) * (number of samples in unmodulated carrier) : 1.

Consequently under sampling is used at input in which 100 Hz input is sampled at 96 kHz. Ideally for 100 Hz input sampled at 96 kHz, there are 960 samples per period. In the implementation undertaken instead of 960 samples, 10 samples are taken. Relevant calculations are shown in section 5.2.3.

The channel is working for maximum possible data rate which can be handled by TMS320C6416 i.e. 96 ksamples/sec * 16 bit/sample = 1536 kbps.

3.2 Synchronisation in pi/4 DQPSK MODEM

Function Generator

PC

DSP DSP

PC

OscilloscopeChannel

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4 Carrier Phase Estimation

When the signal is transmitted, it undergoes delays and phase offsets due to channel impairments. For correct demodulation or detection of transmitted information, correct estimate of carrier phase is necessary. Suppose the transmitted signal is,

)*cos()( tWcAts(4.1)

Due to channel impairments the phase changes and the received signal is,

)'*cos()( tWcAtr (4.2)

The phase of carrier is given by,

*2 fc (4.3)

From the above equation it appears that phase can only be estimated with the correct knowledge of time delay since carrier frequency is known. But in practice it is not the case since local oscillators at transmitter and receiver are not phase synchronous and they may drift in frequency in opposite direction as worst case. So, both phase and time delay must be estimated for correct recovery of message.

Usually carrier frequency is large in the order of MHz’s, so small delay in time can cause large phase errors.

There are two ways for correct carrier phase estimation:

1) first is to transmit carrier with the message information and the receiver will use the Phase Lock Loop (PLL) to track the phase. This technique uses more power since carrier is transmitted. This technique is used in telephony and mobile communication where a number of users in a cell share the same clock and hence power is divided among all users. The obvious advantage is simple circuitry of receiver.

2) Another technique widely used having relatively complex circuitry is to derive the carrier phase directly from modulated signal. It is power efficient.

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The first technique in which unmodulated carrier is transmitted is investigated mathematically as under:

As shown in (3) the received signal is expressed as under:

)(),;()( tntstr (4.4)

where phase and time delay are the parameters to be estimated. Let φ and τ be expressed jointly as ψ so signal is represented as s (t; ψ).

So the above equation becomes:

)();()( tntstr (4.5)

The likelihood function of the above received signal given ψ errors have occurred in the signal is:

N

n

nnN srrp

1 2

2}

2

)]([exp{*)

21()|(

(4.6)

where r is the received signal expressed in vector form and noise is Gaussian with zero mean.

rn and sn are given by the following equations:

To

nn dttftrr )(*)( (4.7)

To

nn dttftss )(*);()( (4.8)

The likelihood function can be re-written as:

4.1 Maximum Likelihood Carrier Phase Estimate

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TO

dttstrNo

}])];()([1exp{)( 2 (4.9)

Now consider are a QAM / M-ary PSK signal expressed as;

)'sin()'cos()( tWcBtWcAts (4.10)

The in phase and quadrature carriers are expressed as:

)(cos)( tWctc I(4.11)

)(sin)( tWctcQ(4.12)

To get the message back the incoming signal is multiplied by in phase and quadrature components and passed through Low pass filter to remove double frequency terms:

)'sin(5.0)'cos(5.0)( BAty I (4.13)

)'sin(5.0)'cos(5.0)( ABtyQ(4.14)

The above two equations show that due to carrier phase offset the power level of the signal is reduced by cos2(φ – φ’) and the in phase and quadrature components have cross talk between them.

The likelihood function can be further expanded into:

TOTOTO

dttsdttstrdttrNo }]);();(*)(2)({1exp[)( 22 (4.15)

where τ = 0 in the above expression and the first and third terms are constant since 1st term is independent of φ and the third term represents signal power. The second term represents the cross correlation between the received signal and the transmitted signal.

So the above expression can be represented as:

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]);(*)({2exp[)( dttstrNo

CTO (4.16)

Now suppose the unmodulated carrier is transmitted the received signal is expressed as:

)()cos()( tntWcAtr (4.17)

The likelihood function is expressed as:

dttWcAtr

NoC

TO)cos(*)(2exp)( (4.18)

Taking log of above equation to get log likelihood fn.

dttWctr

NoA

TOL )cos(*)(2)( (4.19)

Differentiate w.r.t φ,

dttWctr

dd

NoAdd

TOL )cos(*)(2/)(

(4.20)

To maximize the log likelihood function set above equation to zero.

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])cos(*)([0 dttWcddtr

TOML

(4.21)

])sin()([0 dttWctrTO

ML (4.22)

]sincos)(cossin)([0 dtWcttrtWctrTO TO

MLML (4.23)

TOc

TOc

ML tdtWtr

tdtWtr

cos)(

sin)(nta 1 (4.24)

The above equation gives a one shot estimate of the phase of unmodulated carrier and is represented in fig. below:

(Figure 4.1 Maximum Likelihood Phase Estimate with Unmodulated carrier)

∫TOX

X

ΦML=tan-1(B/A)

cos Wct

-sin Wct

∫TO

A

B

Rx sig

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(Figure 4.2 Phase Lock Loop)

The output of VCO is given by,

r(t) = sin (Wct + φ’) (4.25)

where as,

sVCO (t) = cos (Wct + φ) (4.26)

4.2 Phase Lock Loop

FIR filterX

VCO

e’(t)

cos(Wct+φ)

sin (Wct + φ’)

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So the input to the Loop filter e (t) is given by,

e(t) = r(t) sVCO(t) = cos (Wc t + φ) sin (Wc t + φ’) (4.27)

= 0.5 sin (2Wc t + φ + φ’) + 0.5 sin (φ’ - φ) (4.28)

After passing through the FIR filter the error signal e’ (t) becomes:

e’(t) = 0.5 * sin (φ - φ’) (4.29)

The FIR filter acting as Low Pass filter is always stable. The output of FIR filter in digital domain is given as:

1

0)()(

N

kk knxbny (4.30)

The transfer function is given as,

11

21

10 .....

)(

N

NNN

zbzbzb

zH(4.31)

Since all the poles of transfer function are at origin (within unit circle (|z| < 1)) so the FIR filter is always stable.

The output phase of VCO depends upon e’ (t) given as:

t

cc deKtWttW )(')(' (4.32)

t

deKt )(')(' (4.33)

when φ’ – φ is small then sin (φ’ – φ) ~ (φ’ – φ)

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When the transmitted signal carrier information In then it’s difficult to maximize ML function. The information In can either be known or random. In decision directed loops the information is considered to be known whereas in non decision directed loops it is considered to be random.

The received equivalent LP signal as given in (3) is:

)()()exp()( tznTtgIjtrn

n (4.34)

)()exp()()( tzjtstr l (4.35)

]})exp()()(1exp{Re[)( * dtjtstrN

C lTo

lo

(4.36)

Taking log of above eq and maximizing it by setting,

0/)( dd L(4.37)

we get

)Re(/)Im(tan1

0

1

0

1n

K

nnn

K

nnML yIyI (4.38)

Where

dtnTtytryTn

nTln )()(

)1(

(4.39)

For M-ary PSK where the phase of message contains the information:

)1(2'

mMm

(4.40)

Now we calculate r (t) cos (Wc t + φ’) sin Өm and r (t) sin (Wc t + φ’) cos Өm , add them together and pass them through low pass filter to remove double frequency terms, we get the error signal,

4.3 Decision directed loops

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)'cos()(5.0)'sin()(5.0)'sin(5.0)( mQmI tntnAte (4.41)

Where nI(t) and nQ(t) are the in phase and quadrature noise components. The loop shows phase ambiguity of 3600/M (900 in QPSK) which can be avoided by differentially encoding and decoding.

The block diagram for carrier phase estimate using Decision directed loop is shown below:

(Figure 4.3 Decision Directed Feedback Loop)

In non decision directed loops In (information) is treated as random variable and likelihood function is averaged over these random variables.

Mth power loop is an example of Non Decision Directed loops.

4.4 Non Decision Directed Loops

X

X

900 phase shift Rx sig

Delay

+

X

X

LoopFilterVCO

Delay

∫T ( )dt

cos θ’

Sampler

Sampler

∫T ( )dt

-sin θ’

Phase Estimator

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QPSK modulated signal is expressed as:

)()]1(2cos[()( tnmM

tWAtr c

(4.42)

By taking Mth power we get cos (MWct + Mφ) and use BPF at Mfc to get:

0)1(2)1(2

mMmM

(4.43)

This loop also exhibits 360/M phase ambiguity so need of differential encoding and decoding.

(Figure 4.4 Mth power loop)

The Quantitative analysis performed by (6) has shown that variance of Decision directed Feedback loop is 4 to 10 times better than Non Decision Directed Feedback Loop for SNR per bit above 0dB.

Usually jitter performance of data aided ones is worse than non data aided algorithms, but data aided techniques are slow and more erroneous. Kim, Beomsup et al. (7) have shown that if instead of square law device, absolute value rectifier is used for non data aided ones then jitter performance closer to data aided techniques can be achieved which is fast and removes error accumulation problem.

Donally T, et al. (8) have proposed DSP based Clock recovery algorithm which uses IIR filter whose poles are on unit circle. They showed that IIR filter clock recovery technique synchronizes within symbol time of first received transition. Kato S. et al. (9) have proposed a dual carrier filter (DCF) based clock recovery scheme which shows an improvement of 1.5 dB at Pe = 10-4 compared with Coastas loop scheme.

Mth power device

BPF at Mfc

X LoopFilter

VCODivide my M

Output Carrier To Demod

input

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Out of the above techniques discussed above, unmodulated carrier phase estimation technique using Phase Lock Loop is used to implement on the Digital Signal Processor. The reasons for selection of this technique are:

1) It simplifies the receiver circuitry and essentially the area, which is necessary in mobile cellular phones and other equipment.

2) It consumes more bandwidth since unmodulated carrier is transmitted with message, which is not an issue in mobile cellular environment since in mobile environment cellular phone operators have bandwidth in the range of MHz. WCDMA (Wide band Code Division Multiple Access) has 5 MHz bandwidth.

3) This technique consumes more power since carrier is transmitted. Since in telephony and mobile communication a number of users in a cell share the same clock and hence power is divided among all users.

4) Decision directed and non decision directed loops have complex circuitry which maximizes the area which is highly undesirable. And these loops contain more feedback elements so more stability issues have to be addressed.

The block diagram used for implementation is shown in Fig. 4.2. The pseudo code for implementation is:

1) Take sample as input.

2) Multiply the input sample with the VCO which is stored in an array in the code.

3) Perform FIR filtering of the multiplied signal. (The work of FIR filter is not done by author, it is given by Dr. Dahnoun.

4) Ensure that phase difference is less than equal to ±90 degree by checking the positive slope of input sine wave faces how many positive and negative values of VCO.

If number of positive samples of VCO during positive slope of input is greater than or equal to number of negative samples of VCO

Then go to step 5 else go to step 1.

4.5 Implementation Issues

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5) Based on the output of the FIR filter (fir_out) perform shift in the VCO.

If (fir_out ≈ 0) shift = 0

Else if ( thr1≥fir_out≤thr2 ) shift = 1 ( circular shift left the VCO by 1 )

Else if ( thr3≥fir_out≤thr4 ) shift = 2 ( circular shift left the VCO by 2 )

Else if ( thr5≥fir_out≤thr6 ) shift = 3 ( circular shift left the VCO by 3 )

Else if ( thr7≥fir_out≤thr8 ) shift = 4 ( circular shift left the VCO by 4 )

Else if ( thr9≥fir_out≤thr10 ) shift = 5 ( circular shift left the VCO by 5 )

Else if ( thr11≥fir_out≤thr12) shift = 6 ( circular shift left the VCO by 6 )

Else if ( -thr2≤fir_out≥-thr1) shift = -1 ( circular shift right the VCO by 1 )

Else if ( -thr4≤fir_out≥ -thr3) shift = -2 ( circular shift left the VCO by 2 )

Else if ( -thr6≤fir_out≥ -thr5) shift = -3 ( circular shift left the VCO by 3 )

Else if ( -thr8≤fir_out≥ -thr7) shift = -4 ( circular shift left the VCO by 4 )

Else if ( -thr10≤fir_out≥- thr9) shift = -5 ( circular shift left the VCO by 5 )

Else if ( -thr12≤fir_out≥-thr11)shift = -6 ( circular shift left the VCO by 6 )

(All the coefficients are calculated from Matlab and real-time Simulations)

6) Shift the VCO left or right based on the value of shift.

7) Make the VCO Sample out

8) Go to step 1.

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5 Synchronisation

The transmitter and receiver need to be tightly synchronized for correct data recovery. The receiver does not know the right sampling instant where the data starts. So a training sequence known at the receiver is send periodically. The receiver first detects the training sequence and when it is detected the receiver starts demodulating the data.

In the implementation PN code (pseudo random code) is chosen as Training sequence. It is unlikely that the PN code is present in the data. For the PN sequence of N bits the probability of finding the same sequence in data is 1/2N. For instance when N = 14 the probability of finding PN sequence is 6.1e-5 which is very low.

In the implementation synchronisation is first achieved in FSK (Frequency Shift Keying) MODEM and then with pi/4 DQPSK MODEM.

In FSK, binary ‘1’ is assigned a frequency ‘f1’ a binary ‘0’ is assigned a different frequency ‘f2’. The demodulation is done using Goertzel Algorithm which is described in section 2.3.2. The work of Goertzel Algorithm implementation is not done by the author, it is given by Dr. N. Dahnoun.

The pseudo code for modulator and demodulator are described as under:

5.1.1 Pseudo Code for FSK Modulator

1. Send PN sequence bit by bit.

2. Take sample as input from function generator (in Q15 format).

3. Truncate 4 least significant bits (4 LSBs) so only 12 most significant bits (MSBs) are used for transmission.

4. For each logical ‘1’ send frequency f1 and for each logical ‘0’ send frequency f2.

5. Repeat steps 2, 3 and 4 for a pre-set number of times and when that time is elapsed go to step 1.

5.1 Synchronisation in FSK MODEM

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5.1.2 Pseudo Code for FSK Demodulator

1. Take sample as input.

2. Decode it using Goertzel algorithm and store the decoded digit.

3. Compare with the stored PN (pseudo-random) sequence.

4. Repeat steps 1, 2 and 3 until PN sequence is found.

5. Take input sample.

6. Decode and store it until 12 bits are accumulated.

7. Sample the data out.

8. Repeat steps 5, 6 and 7 until the pre-set number of times as in modulator. When the pre-set time is elapsed got step 1.

5.1.3 Implementation Issues

The input sine at 100 Hz is sampled at 96 kHz (or 96000 samples / sec). So each period is represented by 960 sample points (n = Fs / fin). Each sample is represented by 12 data bits (where 4 LSBs are truncated since they don’t effect accuracy much). In the code each of logical ‘1 or ‘0’ is represented by 8 samples. So for every sample taken as input there is a need for sending 96 samples out (12 data bits * 8 samples / bit = 96 samples).

Therefore, the input is under sampled by 96 times and in effect 10 samples are taken from input which leads to effective frequency of input 9.6 kHz (96000 / 10 = 9600). Each logical ‘1’ is represented with frequency 24 kHz (96000 / 4 = 24000) and binary ‘0’ is represented by frequency of 12.5 kHz (96000 / 8 = 12500).

The maximum frequency achievable under this condition is 200 Hz but it will be distorted since it is represented by 5 samples / period only. This can also be visualize from the fact that for 100 Hz input sine wave, each logical ‘1’ is represented with 24 kHz, so for 200 Hz input wave, each logical ‘1’ must be represented with 48 kHz which is half of sampling frequency. According to Nyquist theorem the sampling frequency must be greater than double of maximum frequency component. So the output is distorted for 200 Hz.

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The data rate at which channel is operating is 1536 kbps (96 ksamples/s * 16 bits / sample = 15,36, 000). The effective data rate at which input data is operated is 12 kbps. The effective input sampling frequency is 1000 Hz because of under sampling by 96 times. So input data rate is 1000 samples / sec * 12 bits /sample = 12000 bps.

The data is sent in the form of frames with each frame consisting of two fields i.e. training sequence and data. The length (number of samples, number of bits) of each field and time of its transmission is shown below:

Training Sequence Data112 samples,1792

bits, 1.1167 ms7680 samples, 122880 bits, 80ms

Training sequence

Since training sequence has 14 digits and each digit is represented by 8 samples so total number of samples in training sequence is 112 samples.

Since each sample is represented by 16 bits so total number of bits in T.S is 1792 bits.

As the sampling rate is 96 kHz so the time which training sequence takes to transmit is 1.1167 ms.

Data

Each sample in data is represented by 12 digits and each digit is represented by 8 samples, and data is sent periodically 80 times so total number of samples in data is 7680 samples (80 samples * 12 bits * 8 samples / bit).

Since each sample is represented by 16 bits so total number of bits in data field is 122880 bits. input data rate is 1000 samples / sec * 12 bits /sample = 12000 bps.

As the sampling rate is 96 kHz so the time which training sequence takes to transmit is 80 ms.

A number of combinations with different length of T.S and data were experimented but the above combination showed the optimum results.

5.1.4 Results Achieved

At 100 Hz the output is satisfactory i.e. the receiver is reconstructing the original message, but as the frequency is increased to 200 Hz the output gets distorted.

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Observations have showed that the receiver decoded the data correctly for 9.426 sec. So 117 data frames (9.426 s / 80 ms = 117) are decoded properly.

After 9.426 sec there is an average delay for 1.1960 sec for checking the training sequence. This average delay should be around 1 to 2 ms. The possible reasons for higher delay may be:

1) Errors in modulation.

2) Errors in transmission.

3) Errors in demodulation.

4) Inherent delay of 112 samples or more before comparison with PN sequence.

A possible solution proposed for the large delay is use of some error correction mechanism like Viterbi coding/decoding, Convolutional coding/decoding, FEC (forward error correction).

In pi/4 DQPSK scheme input is sampled into dibits (group of two bits) and each dibit is assigned a phase depending on the current and previous dibit as discussed in section 2.3.6.

The pseudo code for modulator and demodulator are described as under:

5.2.1 Pseudo Code for Modulator

1. Send PN sequence.

2. Take sample as input from Function Generator (in Q15 format).

3. Truncate 8 Least Significant Bits (4 LSBs) so only 8 Most significant bits (MSBs) or 4 dibits are used for transmission.

4. For each dibit send a phase as elaborated in Section 2.3.6.

5. Repeat steps 2, 3 and 4 for a pre-set number of times and when that time is elapsed go to step 1.

5.2 Synchronisation in pi/4 DQPSK MODEM

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5.2.2 Pseudo Code for Demodulator

1. Take sample as input.

2. Decode it using look up table for DQPSK demodulation explained in Section 2.3.6 and store the decoded digit.

3. Compare with the stored PN sequence.

4. Repeat steps 1, 2 and 3 until PN sequence is found.

5. Take input sample.

6. Decode and store it until 4 dibits are accumulated.

7. Sample the data out.

8. Repeat steps 5, 6 and 7 until the pre-set number of times as in modulator. When the pre-set time is elapsed go to step 1.

5.2.3 Implementation Issues

In pi/4 DQPSK implementation training sequence is sent in simple QPSK modulated format. The reason for not choosing pi/4 DQPSK scheme for sending training sequence are:

In pi/4 DQPSK scheme phases are sent differentially. When the receiver suddenly wakes up and starts demodulation without the knowledge of first or initial phase, synchronisation is not possible.

pi/4 DQPSK scheme works on altering constellation with alternate phases are sent on IQ axes where only sines or cosines which are just 90 degrees phase shifted are sent. If the transmitter and receiver are 90 degree phase shifted then whole data will be decoded erroneous.

The input sine at 100 Hz is sampled at 96 kHz (or 96000 samples / sec). So each period is represented by 960 sample points (n = Fs / fin). Each sample is represented by 4 dibits (where 8 LSBs are truncated since they don’t effect accuracy much). In the code each dibit is represented

PI/4 DQPSK Modem Implementation

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by 24 samples. So for every sample taken as input 96 samples are sent out (24 data bits * 8 samples / bit = 96 samples).

Therefore, the input is under sampled by 96 times and in effect 10 samples are taken from input which leads to effective frequency of input 9.6 kHz (96000 / 10 = 9600). Each dibit is represented with frequency 4 kHz (96000 / 24 = 4000). If each dibit is represented with 5 samples (minimum possible) then frequency of each dibit will be 19.2 kHz (96000/5=19200). This frequency is 4.8 times higher than 4 kHz frequency used in implementation so the maximum input frequency attainable in this case in 480 Hz.

The data rate at which channel of MODEM is working is 1536 kbps (96 ksamples/s * 16 bits / sample = 15,36,000). The input data rate is 8 kbps. Since effective input sampling rate is 1 kHz and 8 bits are used to represent each sample so 1000 samples / sec * 8 bits / sample = 8000 bps.

The data is sent in the form of frames with each frame consisting of two fields i.e. training sequence and data. The length (number of samples, number of bits) of each field and time of its transmission is shown below:

Training Sequence Data168 samples, 2688

bits, 1.75 ms76800 samples, 1228800 bits, 0.8 s

Training sequence

Since training sequence has 7 dibits and each dibit is represented by 24 samples so total number of samples in training sequence is 168 samples.

Since each sample is represented by 16 bits so total number of bits in T.S is 2688 bits.

As the sampling rate is 96 kHz so the time which training sequence takes to transmit is 1.75 ms.

Data

Each dibit is represented by 24 samples, and data is sent periodically 3200 times so total number of samples in data is 76800 samples (3200 samples * 24 samples / dibit).Since each sample is represented by 16 bits so total number of bits in data field is 1228800 bits.

As the sampling rate is 96 kHz so the time in which data is transmitted is 0.8 s.

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A number of combinations with different length of T.S and data were experimented but the above combination showed the optimum results.

5.2.4 Results Achieved

At 100 Hz the output is satisfactory i.e. the receiver is reconstructing the original message, but as the frequency is increased to 200 Hz the output gets distorted.

Observations have showed that the receiver decoded the data correctly for 6.4 sec. So 8 data frames (6.4 s / 800 ms = 8) are decoded properly.

After 6.4 secs there is an average delay for 1.21 sec for tracing the training sequence. This average delay should be around 2 ms. The possible reasons for higher delay are:

1) Errors in modulation.

2) Errors in transmission.

3) Errors in demodulation.

4) Inherent delay of 168 samples or more before comparison with PN sequence.

A possible solution proposed for improving the performance is use of some error detection and correction mechanism like Viterbi coding/decoding, Convolutional codes, FEC (forward error correction). Since in DQPSK symbols are sent differentially so the error propagates through out the frame. So, in DPQSK scheme employing error correction mechanism is essential.

Data is decoded without the use of symbol timing recovery loop as the decision is basedabsolutely on the bases of the correlated sum output. When the output is positive then decision is made in favour of ‘1’ and when it is negative decision is made in favour of ‘0’.

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6 Future Work

For voice Modems, the input voice has maximum frequency of 4000 Hz, so minimum sampling rate of 8 kHz is required. For transmission 16 bit sample must be compressed into 2 to 8 bits so that data rate of 16 kbps to 64 kbps can be easily handled by DSP. The author tried to usefreeware VOCODER ‘Smart Audio Converter’ downloaded from internet, which claims to convert recorded voice in PCM format to different formats i.e. 64 kbps PCM, 32 kbps ADPCM, 64 kbps CCITT u-LAW, 13 kbps GSM format. The author plugged in these audio files to DSP but it was observed that the samples are still 16 bits instead of being compressed into 2 to 8 bits. Many other free ware softwares from online resources were tried but they didn’t work as expected.

It is now left as future work to implement real-time Voice Compression using PCM / ADPCM (Adaptive Differential Pulse Code Modulation) techniques and integrate into the system so that real-time voice can be transmitted.

Error detection and correction is an essential component of any communication system. And it is essentially must in a technique like pi/4 DQPSK where phases are sent differentially i.e. current phase depends upon its previous phase and previous phase depends on its previous phase, and so on. So an error in a single phase is likely to propagate through out the frame.

It is proposed that error detection and correction techniques like Convolution Encoding / Decoding, Viterbi Encoding / Decoding or Forward Error Correction must be integrated into the communication system.

In the implementation carried in this project, transmitter and receiver are connected through wired medium. A possible and easy conversion from wired to wireless medium can be done by using Walkie Talkie. But this is only possible after incorporation of VOCODER. Instead of wired link between two DSPs, the output of transmitter should be connected to one walkie talkie

6.1 Use Of VOCODER For Voice Grade Modem

6.2 Error Detection and Correction

6.3 Wireless Link

PI/4 DQPSK Modem Implementation

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which transmits it on air. Another walkie talkie will receive the voice and should be connected to the DSP at receiver. The receiver will then demodulate the message and the final output will be listened at the audio jack out of DSP.

When a signal is transmitted on RF channel, it undergoes reflection, dispersion, diversion from different obstacles. So different multipaths are formed and each multipath has different amplitude and carries different information. At the receiver they all must be combined using MRC (maximal ratio combining) to get the original signal back with maximum strength. The idea is to use multiple correlator receivers, each for a different multipath and each mutipath is correlated with a known signal at receiver. Rake receivers are commonly used in CDMA / WCDMA (Wideband Code Division Multiple Access) systems. For implementing Rake receiver the correlator receiver is copied ‘N’ times provided there are ‘N’ multipaths. Each correlator receiver is said to be a ‘finger’. Each finger’s operational timings are controlled by the peaks of matched filter response.

It is left as future work to copy the receiver for appropriate number of times depending upon the channel information and integrate it with the system.

6.4 Rake Receiver for Removal of Multipath Fading

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7 Bibliography

1. Dahnoun, Naim. Lecture 17, Goertezel Algorithm. s.l.: Univeristy of Bristol, UK, 2004.

2. Haykin, Simon. Digital Communications. New York: John Wiley & Sons, 1988. 0-471-62947-2.

3. Proakis, John G. Digital Communications. 4th. New York: McGraw-Hill, 2001. 0-07-232111-3.

4. An Efficient Constant Envelope pi/4 QPSK Modulation Scheme. Tong Fu Lee, Shih Ho Wang, Chia Liang Liu. s.l. : Circuits and Systems, Proceedings of the 40th Midwest Symposium on Persistent Link, 1997, Vol. 1.

5. BER Expression for Differentially Detected pi/4 DQPSK Modulation. Leonard E. Miller, Jhong S.Lee. 1, s.l. : IEEE Transactions on Communcations, 1998, Vol. 46.

6. WC Lindsey, MK Simon. Telecommunication Systems Engineering. Englewood Cliffs NJ : Prentice Hall, 1973.

7. Baseband Clock Recovery Algorithm for pi/4 QPSK Modulated Signals. J E Lee, S H Choi, B Kim. s.l. : Vehicular Technology Conference, IEEE 47th, 1997, Vol. 3.

8. DSP based Clock Recovery Implemented in a Field Programmable Gate Array. P M Smithson, M Tomlinson, T Donnelly. s.l. : New Synchronisation Techniques for Radio Systems,IEE Colloquium on Persistent Link , 1995.

9. A New Carrier Recovery Circuit for Land Mobile Satellite Communication. K. Kobayashi. T. Sakai, S. Kubota, M.Morikura, S. Kato. s.l. : IEEE Journal on Selected Areas in Communication, 1992, Vol. 10.

10. Chassaing, Rulph. DSP Applications Using C and the TMS320C6x. New York : John Wiley & Sons, 2002. 0-471-20754-3.

11. Dahnoun, Naim. Lecture 17, Goertzel Algorithm. s.l. : Univeristy of Bristol, UK., 2004.

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8 Appendices

For implementation of voltage controlled oscillator to use in PLL, the author tried IIR (Infinite Impulse Response) filter to act as voltage controlled oscillator. The frequency of sinusoid was changed successfully based on coefficient value but the phase can not be changed by changing the coefficient value.

For IIR filter when the poles are placed on the unit circle then it yields an oscillatory response. The general difference equation for IIR filter is given as:

)()()(0 0

mnyblnxanyN

l

M

mml

(7.1)

The equation shows recursive nature of IIR filter, that is, present output depends upon previous outputs.

As mentioned in (10) difference equation used for generation of sinusoid used is:

)1()2()1()( nCxnynAyny (7.2)

with initial conditions

A = 2 cos wt

C = sin wt

y(-1) = -sin wt

y(-2) = -sin 2WT

W = 2πf and T = 1/Fs

For f = 1 kHz and Fs = 8 kHz, so A = 1.414 and C = 0.707

If an impulse is applied at n = 1 so, x(0) = 1 and zero else where.

y(0) = Ay(-1) – y(-2) + C x(0) = 2 cos wt * - sinWT + sin 2WT + 0 = 0

From Matlab simulation and CCS implementation it is observed that above difference equation works satisfactory as sine wave generator as shown in fig 8.1 below:

8.1 Appendix A IIR Filter as Oscillator

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(Figure 8.1 IIR filter working as an oscillator)

The poles of the above IIR filter are on unit circle as shown in fig 8.2 below:

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(Figure 8.2 Pole Zero Plot)

Note: ‘x’ denotes poles and ‘o’ denotes zeros.

The mathematical proof is as under;

The transfer function of the IIR filter under above described conditions is

1414.1707.0)( 2

zz

zzH (7.3)

By setting the denominator of above transfer function to be zero, the poles are found to be 0.707 ± j0.707. So the magnitude of pole is |z| = 1.

The author tried to change the phase of oscillator by introducing one more term to coefficients:

A = 2 cos (wT + phase)

C = sin (wT + phase)

It was expected that this constant ‘phase’ term will change the phase of the oscillator but simulations showed that it also affected the frequency and not the phase. So the idea was left out.

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Phase Lock Loop

int main(void){ // Set codec frequency to 24 kHz DSK6416_AIC23_setFreq(hCodec, DSK6416_AIC23_FREQ_24 KHZ );

while (1){

// Read sample from left channelwhile (!DSK6416_AIC23_read(hCodec, &IN_L));

// Read sample from the right channel while (!DSK6416_AIC23_read(hCodec, &IN_R));

t2 = t1 ; //storing previous samplet1 = IN_L; //storing present samplesine_val = (short) IN_L;OUT_L = vco_inuse[j];temp1 = sine_val*OUT_L; //generating error signaltemp1 = temp1 >> 15 ; //converting to Q15 format

mul = (short) temp1; fir_out = fir_filter(mul); //takes FIR filtering of error signal

shift = numberofshift (fir_out); //calculates the shift based on FIR output

vco_phase_change(shift); //changes the phase of VCO

// Send output sample to the left channel while (!DSK6416_AIC23_write(hCodec, OUT_L));

// Send output sample to the right channel while (!DSK6416_AIC23_write(hCodec, OUT_R)); } //end while (1)

} //end main()

8.2 Appendix B Program Listing

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Pi/4 DQPSK Modulator

void main(void){

// Set codec frequency to 96 kHzDSK6416_AIC23_setFreq(hCodec, DSK6416_AIC23_FREQ_96 KHZ );

while (1){

//transmitting Training Seq and Data in form of periodic framePN_transmit();

Modulator ();

}}

void Modulator (){

arr[0] = (input>>8) & 0x0003; //extracting dibit after trucating 8 LSBs

if ( arr[0] == 0 ){ for (i=0; i<24; i++)

{out = (short) (0.707*(-sine_table[i] - cosine_table[i])); //normal QPSK modulation

}}//same procedure for 1, 2 or 3 dibit.

for (j = 1 ; j < (80*40) ; ) //Data Frame{

arr[j] = (input >> shift) & 0x0003 ; //extracting dibit//deciding what to transmit based on LUTto_send_first = array_even[to_send_second][arr[j]] ; if ( to_send_first == minus_sine ){for (i=0; i<24 ; i++) out = -1*sine_table[i]; //transmission on IQ Axes

}

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//same procedure repeated for sine, cosine, and minus cosine

j++;// deciding what to transmit based on LUTto_send_second = array_odd[to_send_first][arr[j]];

if ( to_send_second == 0 ) {

for (i=0; i<24; i++)out = (short) (0.707*(-sine_table[i] - cosine_table[i])); //QPSK modulation

}

// same procedure for 1, 2 or 3 valued dibit

}}

Pi/4 DQPSK demodulator

void main(void){

while (1) {

y = PN_detect(); //PN_detect checks for training sequence, works roughly same as demodulator but under hard constraints

x = Demodulator(); }

}

int Demodulator(void){

for (i=0; i<24; i++) //performing correlation{

temp1 = (input_hold[i] * cosine_table[i])>>15;corr1[i] = (short) temp1;sum1+=corr1[i];

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temp2 = (input_hold[i] * sine_table[i])>>15;temp2 = temp2 >> 15 ;corr2[i] = (short) temp2;sum2+=corr2[i];

}//decoding dibit based on value of sum1 and sum2if (sum1 > 0 && sum2 > 0)

received[0] = 3;else if (sum1 > 0 && sum2<0)

received[0] = 1 ;else if (sum1 < 0 && sum2>0)

received[0] = 2 ;else if (sum1 < 0 && sum2<0)

received[0] = 0;

for (l=1; l < (80*40); l+=2) {

temp = IQ_Detect(l) ; //fn to find out IQ value i.e dibit on IQ axis//for IQ dibit either I=0 or Q=0

received[l] = array_even_decode[ temp1 ][ temp ]; //decoding using LUT.

temp1 = piby4(l+1) ; //fn to find out pi/4 values received[l+1] = array_odd_decode[ temp ][ temp1 ]; // decoding using LUT.

}

}