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MicroLab, VLSI-2 (1/24)

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VLSI Design IThe MOSFET model Wow !

Are device models asnice as Cindy ?

OverviewThe large signal MOSFET model and second order

effects. MOSFET capacitances.Introduction in fet process technology

Goal: You can use the large signal equivalent MOS device equation. You are familiar with second order effects like body effect, channel length modulation. You know the MOS capacitances. You know the basic steps in MOS fabrication.


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Let’s build a MOSFETThere are lots of different recipes to choose from. Like most things in life, you get what you pay for: the ability to have good bipolar devices, radiation hardness, reduced latch-up and substrate noise, … are all extra cost options. We’ll consider a general process: bulk CMOS with a p-type substrate:

p-type

500um slice of a silicon ingot that has been doped with an acceptor (typically boron) to increase the concentration of holes to 1014/cm3

- 1018/cm3.

Back is metallized to providea good ground connection.

Good for n-channel fets, but p-channelfets will need a n-type “well” (or tub) tolive in!

Use <100> surfaceto minimize surfacecharge


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Next, a “thick” (0.4um) layer of silicon dioxide, called field oxide, is formed on the surface by oxidation in wet oxygen. This is then etched to expose surface where we want to make a mosfet:

p

Now grow a “thin” (0.01um = 100 Å) layer of silicon dioxide, called gate oxide, on the surface by exposing the wafer to dry oxygen.

p

The gate oxide needs to be of high quality: uniform thickness, no defects! The thinner the gate oxide, the more oomph the fet will have (we’ll see why soon) but the harder it is to make it defect free.


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On top of the thin oxide a 0.7um thick layer of polycrystalline silicon, called polysilicon or poly for short, is deposited by CVD. The poly layer is patterned and plasma etched (thin ox not covered by poly is etched away too!) exposing the surface where the source and drain junctions will be formed:

p

field oxidepoly wiresgate oxide(only under poly)

exposed surface for sourceand drain junctions

Poly has a high sheet resistance (25 ohms/square) which can be reduced by adding a layer of a silicided refractory metal such titanium (TiSi2), tantalum (TaSi2) or molybdenum (MoSi2). These have sheet resistances of 1, 3 or 5 ohms per square, respectively. This is great for memory structures that have lots of poly wiring.


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The entire surface is doped, either by diffusion or ion implantation, with phosphorus (an electron donor) which creates two n-type regions in the substrate. The phosphorus also penetrates the poly reducing its resistance and affecting the nfet’s threshold.

pn+ wires: 20-30 ohms/sq.

Finally an intermediate oxide layer is grown and then reflowed to flatten its surface. Holes are etched in the oxide (where contacts to poly/diff are wanted) and aluminum deposited, patterned and etched.

metal wires (0.08 ohms/square)

diff contact (0.25 - 10 ohms) n- channel MOSfield effect transistor!

diffusions are “self-aligned”with poly

n+ n+

???


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NFET Operation

S DG

B

n+ n+

p

mobile electrons,fixed positive ions(n+ means heavilydoped with donors,doesn’t implypositive charge!)

mobile holes,fixed negative ions

depletion layerno mobile carriers,but fixed negative ions(slight intrusion into n+,but mostly in p area)

Picture shows configuration when Vgs < Vto

B

S D

GTerminal with higher voltage is labelled D,the other is labelled Sso Ids >= 0.

Ids = 0

Other symbols:

almost always ground


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FET = field effect transistorThe four terminals of a fet (gate, source, drain and bulk) connect to conducting surfaces that generate a complicated set of electric fields in the channel region which depend on the relative voltages of each terminal.

Eh Ev

source drain

gate

bulk

INVERSION:A sufficiently strong verticalfield will attract enoughelectrons to the surface tocreate a conducting n-type channel between the source and drain.

CONDUCTION:If a channel exists, ahorizontal field will causea drift current from thedrain to the source.Expect Ids proportionalto Vds*(W/L)?

inversionhappens here

Picture shows configuration when Vgb > Vto


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Threshold voltageThe gate voltage required to form the channel is called the threshold voltage. Many factors affect the gate-source voltage at which the channel becomes conductive. Threshold voltage for source-bulk voltage zero:

0.7V for n-channel-0.7V for p-channel ??

?

????

?

i

A

nNln

qkT2

? ox

oxt

2 2? ?si A bqN

V V VTO t ms fb? ??

???

????

?2i

AD

nNNln

qkT

?

??????????

ox

fcms

ox

bbTO C

QCQV ???? ??2


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Body effect (second order)As Vsb increases, the depth of the depletion region increases, exposing more of the fixed acceptor (i.e. negative) ions in the substrate.Thus the second term in the threshold voltage equation on the previous slide increases from

to

the threshold voltage of the n-channel transistor is now:

? ?bsbAsi

bAsi

2VNq2

2Nq2

??

?

?

?

As we’ll see, this effect comes into play in series-connected fetswhere only one of the fets will have Vsb = 0 and the other fets will have Vsb > 0 and a higher threshold voltage.

Vsb>0

Vsb=0Vt2> Vt1

T2

T1

? ?bbsbtn0tn 22VVV ?????? ?ox

Asi

CNq2?

? ?


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Basic DC equations

MOS transistors have 3 regions of operation:?cutoff region (subthreshold)?linear region (triode region)?saturated region (active region)

L

W

polysilicon gate

source diffusiondrain diffusion

SiO2

Cutoff or subthreshold region:Vgs <=Vt

Ids = 0There is still a small current described in the second order effects (weak inversion). Important to model for analog circuits: I Vds ds?


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“Linear” operating regionVs Vgs > Vt 0 < Vds < Vdsat

Larger Vgs createsdeeper channel whichincreases Ids

Ids

Larger Vds increases drift current but also reduces vertical field component which in turn makes channel less deep. Channel will pinch-off, when

Vds = Vgs - Vt = Vdsat

only linear when Vds is small,otherwise parabolic

max value at Vds = Vdsat,but then channel ispinched off (see next slide)

channel length isalmost always minallowable

L

mobility(un > up)

? ?IWL t

V V VV

dsox

oxgs t ds

ds? ? ??

??

?

??

? ? 2

2

fet gain factor k=µCox


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Saturated operating regionVs Vgs > Vt Vdsat < Vds

Ids

Voltage at channel endremains essentiallyconstant at Vdsat sodrift current also remainsconstant: device is insaturation.

Electrons arriving from source are injected into drain depletion region and accelerated towards drain by field proportional to Vds - Vdsat usually reaching the drift velocity limit.

this is just Ids from previous slideevaluated at Vds = Vdsat

? ? ? ?I sat WL t

V Vdsox

oxgs t? ?

22? ?


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Channel-length modulation(second order)

Vs Vgs > Vt Vdsat < Vds

Ids

L’ = L - dLdL

As Vds increases,dL get larger

This looks just like afet with a channel lengthof L’ < L. Shorter L’ impliesgreater Ids...

As Vds increases the effective channel length gets shorter so Ids(sat) increases. dL is proportional to

but most people approximate channel length modulation as a linear effect:

? ? ? ? ? ?I sat WL t

V V Vdsox

oxgs t ds? ? ?

21

2? ??

V Vds dsat?


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NFET Ids curves

“Put it together and what have you got?”

plot of Ids vs. Vds for Vgs = 0 ,1, 2, 3, 4 and 5V

Can you find the following in the plot?Ids vs. Vds when Vgs = 0VIds vs. Vds when Vgs = 5Vvalue of Vtvalue of Vdsatevidence of body effectevidence of channel length modulation


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SPICE ModelsThere are different models used in circuit simulators:? level 1 is our simple model including the most

important second order effects described?level 2 model is based on device physics?level 3 is a semi-empirical model allowing to match

equations to the real circuit: example BSIM model from Berkeley models subthreshold characteristics

?summary of the main SPICE DC parameters used in all three models at the end of this chapter

.M1 4 3 5 0 nfet W=1u L=0.5u AS=1p AD=1p PS=3u PD=3u...MODEL nfet NMOS+TOX=1E-8+CGB0=345p CGS0=138p CGD0=138p+CJ=775u CJSW=344p MJ=0.35 MJSW=0.26 PB=0.75+. . . . ..


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MOSFET Capacitance Estimation

the dynamic response of MOS systems strongly depends on the parasitic capacitances associated with the MOS device. The total load capacitance on the output of a CMOS gate is the sum of:?gate capacitance (of other inputs connected to out)?diffusion capacitance (of drain/source regions)?routing capacitances (output to other inputs)

Csb Cdb

Cgs CgdCgb tox

source drain

substrate

depletionlayer

gate

channel

Cgs

gate substrate

source

drain

Csb

CdbCgd

Cgb


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MOSFET gate capacitances

Cg = Cgd + Cgs + CgbOxide-related capacitances come in two forms:

? overlap capacitance (extrinsic) since gate slightlyoverhangs diffusions and bulk:

C(overlap) = W LD Cox

C(overlap) = 2L CGB0

?channel-charge related capacitances (intrinsic):

cut-off: Cgb = Cox W LCgs = Cgd = 0

linear: Cgb = 0 Cgs = Cgd = 0.5 Cox W L

saturation: Cgb = 0Cgd = 0Cgs = 0.67 Cox W L

amount of overlap

for Cgb

shielded by channel

equally shared between S and Dnote capacitive coupling of gate and drain/source

channel pinched offchannel shortened

for both Cgs and Cgd

Cgs = W CGS0Cgd = W CGD0Cgb = 2L CGB0

for SPICE


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MOSFET diffusion capacitances

channel

bottom junction facesp-type substrate

sidewalls face p+channel stop

sidewall faceschannel

source/drain diffusion

Junction capacitances Cdb and Csb are a function of theapplied terminal voltages and diffusion dimensions:

zero-bias C/unit area of bottom junction

perimeter of diffusion

zero-bias C/unit length ofsidewall junction

grading coeff.

area of diffusion

xj

Mjsw

b

j

jswMj

b

j

jdiff

VV

1

PC

VV

1

ACC

???

????

??

?

???

????

??

?

built-in junctionpotential junction voltage

grading coeff.

negative forreverse biased


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P-channel MOSFETsS DG

B

p+ p+

p

n

n-well always connectedto Vdd to keep pnjunction back-biased

threshold voltage isnegative since we needattract holes to forminversion layer

B

S D

GOther symbols:

PFET is built inside itsown “substrate”: a n-typewell or tub diffused intop-type bulk substrate.Don’t forget well contacts!

Terminal with lowervoltage is labelled D,the other is labelled S

off: Vgs > Vtlin: Vgs>Vt, Vds>Vgs-Vtsat: Vgs>Vt, Vds<Vgs-Vt


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Depletion-mode MOSFETs

This mosfet is always conducting but, like ordinary enhancement fets, it will conduct more current as Vgsincreases. One can build logic circuits with only n-channel devices (NMOS): enhancement fets for pulldowns and depletion fets as static pullups. Since NMOS logic dissipates DC power it’s been largely replaced by CMOS.

S DG

n+ n+

p

Bchannel doped with donorsto give negative thresholdvoltage, i.e., depletion fetsare always on.


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Coming Up...

Next topic…Static characteristics of MOS inverters: inputand output voltages, noise margins, powerdissipation.

Readings for next time…Weste: ? sections 2 thru 2.23 except 2.2.2.4 - 2.2.2.7 (fet

models),? 3 thru 3.2.2 (process technology) and ? 4.3 through 4.3.4 (capacitances)

CBT:Study the chip fabrication text of the university of Manchester at the MicroLab VLSI course web link.


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Useful Constants

sym value units description?0 8.8542E-12 F/m permittivity?ox 3.9 ?0 F/m permittivity of SiO2

?Si 11.7 ?0 F/m permittivity of siliconVT 25.8 mV kT/q (@300°K)q 1.6022E-19 C charge of electronk 1.381E-23 J/°K Boltzmann‘s constantni 1.45E10 cm-3 intrinsic carrier concentration


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Alcatel 0,5um Process Parameterssym param nmos pmos units descriptionVt0 VTO 0.61 -0.61 V threshold voltagetox TOX 1E-8 1E-8 m thin oxide thicknessNA NSUB 4E16 4E16 cm-3 substrate doping density? U0 290 78 cm2/Vs charge mobilityk KP A/V2 fet gain factor? GAMMA V0.5 bulk threshold param.Cox COX F/m2 oxide capacitance ? ? /L V-1 channel length? modulat.1e-8 2e-8 V-1m-1 channel length mod fact.?0 PB 0.7556 0.78469 V built in junction potent.2?F PHI 0.77 0.77 V surface inversion pot.

Cgb0 CGB0 3.45E-10 dito F/m overlapping cap per 2LCgs0 CGS0 1.38E-10 dito F/m overlapping cap per WCgd0 CGD0 1.38E-10 dito F/m overlapping cap per WCj CJ 7.75E-4 8.15E-4 F/m2 zero-bias cap / unit ACjsw CJSW 3.44E-10 3.54E-10 F/m zero-bias cap per unit PMj MJ 0.35 0.36 grading coeff for bottomMjsw MJSW 0.26 0.27 grading coeff sidewall


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Exercises: VLSI-2Ex vlsi2.1 (difficulty: easy): Calculate the missing

parameters on the previous transparency like intrinsic transconductance k, bulk threshold parameter ? and oxide capacitance Cox of an nfet (Alatel 0.5? m process?

Result: kn=100? A/V2, kp=24.9? A/V2, ?=0.334V0.5, Cox=3.45E-7 F/cm2 (see Weste pp48ff)

Ex vlsi2.2 (difficulty: easy): Calculate the threshold voltage shift due to the body effect of an nfet at Vsb = 2.5V (Alcatel 0.5? m process)

Result: dVtn = 0.282V (see Weste pp55)Ex vlsi2.3 (difficulty: easy): Calculate the

transconductance ? n of an nfet (Alatel 0.5? m process), W=1 ? m, L= 0.5 ? m

Result: ? n=200 ? ? ?V2 (see Weste pp53) Ex vlsi2.4 (difficulty: easy): Calculate the capacitances of

an nfet with Vsb=Vdb=3V, W=1? m, L=0.5? m, A=1? m2, P=3? m (Alatel 0.5? m process)

Result: Cgate=2.35fF, Cdrain=Csource=1.2fF (see Westepp183-191)

Weste pp99: 2.10: Have a look at ex 8, 9