MICROPROCESSOR LECTURE
Evolution of Microprocessor
VACUUM TUBES 1 to 3 in high, it requires space, generate tremendous heat, and requires large amount of power.
TRANSISTOR act as a logical switches in digital circuits. It replaced the vacuum tubes. Invented at Bell lab in 1947. ¼ in high, little power.
JACK KILBY of texas instrument used very small wires to connect transistors (first IC), that was in 1958.
ROBERT NOYCE of fairchild semiconductor developed a method of evaporating aluminum in specific places on a silicon wafer to connect transistors. First practical IC was developed in 1959.
ROBERT NOYCE and GORDON MOORE started INTEL. To develop integrated electronic structure and computer memories. That was in 1968.
The FIRST MICROPROCESSOR was delivered by BUSICOM with the help of TED HOFF in 1971.
TED HOFF developed a single general-purpose chip that could be programmed to carry out a calculator’s function. But BUSICOM was bankrupted and INTEL bought the right to manufacture the said chip.
INTEL 8080 used in the first PC, the ALTAIR computer. Created at MITS by ED ROBERTS. No keyboard and monitor. Can only be programmed in straight binary.
BILL GATES AND PAUL ALLEN started out Microsoft. The first product of Microsoft was a basic interpreter for ALTAIR.
MOST-TECH produced 6502. This is an 8-bit Microprocessor/machine. Low cost. Used in COMMODORE PET and APPLE 2. That was in 1975.
ZILOG introduced Z80 in 1976. This is an 8-bit chip. Used by RADIO SHACH in its TRS-80 computer in 1977.
History of Microprocessor
INTEL 4004 4-bit microprocessor Runs at 108Khz Contains 2300 transistors 4KB of memory first microprocessor developed primarily for games, test equipment and other simple digital
systems. Used for electronic calculations. Not capable of running nor starting word processors, spreadsheets and databases. 1971
INTEL 8008 8-bit microprocessor improved version of 4004 16KB of memory can handle more complicated operations LATE 1971
INTEL 8080 Improved version of 8008 Speed of operation is ten times faster than 8008 64KB of memory simple word processors maybe used 1973
INTEL 8086/8088 Demand for greater and more powerful microprocessor and influence of competition 16-bit microprocessor 1MB of memory LATE 1970’s
INTEL 80X86 FAMILY Upgraded capability of 8086/8088 XT (Experimental Technology) AT (Advanced Technology)
MOTOROLA Followed the steps of INTEL corporation MC6800 MC68000, 32-bit microprocessor
Z80 Developed and manufactured by the original designers of INTEL 8086/8088
IBM (International Business Machine) POWERPC with their own microprocessor called RISC (Reduced Instruction Set Computing)
and CISC (Complex Instruction Set Computing). Server in Network System.APPLE/MACINTOSH
POWERMAC
INTEL PENTIUMBasic Structure of Microprocessor
BUS UNIT has the job of establishing communication with the external unit.
INSTRUCTION UNIT fetches and decodes the subsequent instruction of the program being run.
ADDRESS UNIT calculates the address (for memory location).
ALU performs data processing operations specified during the execution phase of the instruction being interrupted.
CONTROL UNIT generates the set of timings and controls necessary for the corresponding execute phase.
ALUCTRL UNIT
ADDR UNIT
INST UNIT
BUS UNIT
Bus Structure
SYSTEM BUS a physical group of signal lines that has a related function within a microprocessor system.
Three Buses in a microprocessor system1. SYSTEM ADDRESS BUS
The job is to enable or select the correct path for electrical communication. 2. SYSTEM DATA BUS
A bi-directional that carries back and forth data to specified location with basis to the address location of the address bus.
3. SYSTEM CONTROL BUSAn output bus whose function is to send signal that determines and initiates the type of electrical communication that is to take place on the system data bus.
Two kinds of Buses1. INTERNAL BUS or internally connected bus. When two or more parts that make-up an element of a
computer system is connected by a set of lines.2. EXTERNAL BUS when a set of line connects two or more elements of a computer system.
Four Kinds of Control Lines1. RST reset2. NMI non-maskable interrupt3. R/W read/write4. IRQ interrupt request
I/O Control
Two different techniques for handling the CTRL of I/O devices1. MEMORY MAPPED I/O which I/O devices are treated as memory.2. ISOLATED I/O OR MAPPED I/O I/O device has a unique address, not a memory address. Processor
that uses this, has a special instruction the IN and OUT.
Two Basic Control Signal of Memory Mapped I/O1. memory read2. memory write
Isolated I/O Scheme1. memory read2. memory write3. I/O read 4. I/O write
MICROPROCESSOR the central processing unit of a computer, which includes an ALU, control unit, and bus unit all, integrated on a single IC.
MICROCONTROLLER a single chips microcomputer consisting of a memory unit and in I/O unit. Typically used for dedicated applications such as industrial controller, telecommunications, home appliances and automotive.
MICROCOMPUTER a complete computing system consisting of a microprocessor, a memory unit and an I/O unit.
Three main sections of a computer1. INPUT consists of all the circuits needed to get programs and data into the computer2. MEMORY stores program and data before the computer run/begins.3. CONTROL directs the operation of all other sections. It tells the other sections what to do and when to
do a certain task.4. ALU grids out answers of number and logic problems.5. OUTPUT passes answers and other processed data to the outside world.
Level of Integration1. SMALL SCALE INTEGRATION 12 number of gates2. MEDIUM SCALE INTEGRATION 12 to 100 number of gates3. LARGE SCALE INTEGRATION 100plus number of gates4. VERY LARGE SCALE INTEGRATION 5,000 TO 50,000 number of gates
Basic Technologies1. BIPOLAR preferred for SSI and MSI because it is much faster but bulky.
DTL diode transistor logic. Obsolete. TTL transistor-transistor logic. Popular family of SSI and MSI. ECL emitter-coupled logic. Fastest, used in high-speed application.
2. MOS more MOSFETD can be packed on the same chip area. PMOS p-channel MOSFETS. Oldest obsolete and slowest. NMOS n-channel MOSFETS. Dominates LSI. Used for microprocessor and memories. CMOS complementary MOSFETS. Push-pull arrangement of n- and p- channel MOSFETS used
where low power consumption is needed.
Main Functions Shared by All MPUs1. DATA TRANFERS OPERATIONS the MPU spends 95% of its time transferring data. Transferring
of data is to/from the memory in the system. Data is transferred to/from the I/O and passes around the processor.
2. ARITHMETIC AND LOGIC OPERATIONS 4% is spent on simple ALU operations. Addition most performed, through addition the microprocessor can subtract using 2’s complement.
3. DECISION-MAKING OPERATIONS least used. Based upon numerical test.
Speed of Operation of the Microprocessor Unit
Two determinants of the Speed of a Microprocessor Unit1. The clock frequency of the microprocessor. Measured in megahertz.2. The number of instructions it can perform or execute at a single time. Measured in Millions of
Instructions per Second or MIPS.
Three Major Parts of a Microprocessor Unit
1. ARITHMETIC LOGIC UNIT (ALU) made up of logic circuits whose primary function is to process data. All arithmetic and logical operations are performed here in ALU.
2. CONTROL UNIT is made of the following: INSTRUCITON DECODER serves as the control logic’s intelligence, which also serves as the
brain of the microprocessor unit. The circuit responsible in the synthesis and decoding of the instructions fed or received by the microprocessor.
TIMING used to synchronize the operation of the different parts of the control unit and the computer system. Always in phase with the clock system of the microcomputer.
CONTROL LOGIC the circuit responsible in the operation of the different parts of the microprocessor unit and the microcomputer system. The control signals flowing in the control bus is sent by the control logic. All operations to be performed by the microprocessor are driven by the control logic.
3. REGISTERS play a very important role in the operation of the microprocessor. All data and instruction that is sent to the microprocessor are first stored in the registers. Serves as temporary storage devices of the microprocessor. The following are the seven registers present in all MPU:\ ACCUMULATOR register that works very closely always with the ALU unit. All results of the
processes performed by the ALU are stored at the accumulator. In some case an operand is also stored in this register before the ALU processes the operands. Its main purpose to accumulate data. Only data is stored in this register that is why this is considered as 8-bit register.
INSTRUCTION REGISTER registers that works very closely with the instruction decoder of the control unit. It stores all instructions coming from the data bus. Before the instruction decoder synthesizes the instruction, it is first stored in this register. What is stored or placed in the instruction decoder is the Opcode or Operation Code of the instruction to be executed by the microprocessor. That is used to specify what operation is to be performed by the microprocessor.
PROGRAM COUNTER register responsible in tracking the address in memory of the instructions to be executed by the microprocessor. As soon execution of the program starts, the first memory location containing the instruction is stored to the program counter. It automatically increments as soon it is finished with the memory location. Serves as the marker in memory of the instruction or data to be fetched.
STATUS REGISTER register that is referred to as the Flag Register or Condition Code Register. The term flag is used as an indicator of the status, which can be set or reset. When the microprocessor is executing a program. Always, it affects the status register. This register is composed of several flags, which comprises the bits of the status register. Setting the flag means placing a logic 1 and resetting means placing a logic 0. The most flags in the microprocessor are the following:
CARRY FLAG HAL-CARRY FLAG ZERO FLAG SIGN FLAG/NEGATIVE FLAG OVERFLOW FLAG INTERRUPT FLAG
STACK POINTER register whose purpose is to point to the top of the stack. A stack is a temporary storage of data or instruction that is temporarily not in use. The stack uses a last-in-first-out algorithm. This register simply points to the data or instruction on the top of the stack. Placing information to the stack is also invoking a push operation while retrieving the topmost information is invoking a pop operation.
GENERAL PURPOSE REGISTER used to store data and are directly connected to the data bus of the system. The use of this register varies depending on the purpose of the user or programmer.
INDEX REGISTER used as an aid in accessing data found in tables stored in the memory. It can be incremented or logic or decrements and normally do not have any other arithmetic or logical capability.
PROGRAM is a set of instructions or rules to follow to perform a specific task.MNEMONICS instruction somewhat English-like languageCategories of Instruction Set of Every Microprocessor
DATA TRANSFER INSTRUCTIONS ARITHMETIC OPERATION INSTRUCTIONS LOGICAL OPERATION INSTRUCTIONS PROGRAM FLOW CONTROL INSTRUCTIONS INPUT/OUTPUT INSTRUCTIONS MISCELLANEOUS INSTRUCTIONSAllowable Data transferring
REGISTER TO REGISTER REGISTER TO MEMORY LOCATION MEMORY LOCATION TO REGISTER
Addressing Modes1. INHERENT IMPLIED ADDRESSING MODE the instruction does not require an address in memory.
One byte instructions.
Example:
INX (add one to the index register)
2. IMMEDIATE ADDRESSING MODE the actual data is found in the next one or two locations immediately following the instruction.
Example:
ADC A, #$25 (add 25H to the content of accumulator A with carry flag content, sum into accumulator A)
3. DIRECT OR ABSOLUTE ADDRESSING MODE the address where the data can be found ( the target address) is in the next memory location. Two byte instruction.
Example:
ADC A $25 (add the content of address 25 to the content of accumulator A with carry flag content, sum into the accumulator A)
4. ACCUMULATOR ADDRESSING MODE one byte instructions that address either accumulator A or accumulator B.
Example:
COM A (complement the content of accumulator A)
5. EXTENDED ADDRESSING MODE similar to the direct mode except that it uses three bytes of memory instead of two, one for the instruction and the next two for the target address.
Example:
ADC A, $CCFF (add the content of address CCFFH into the content of accumulator A with carry flag content, sum into the accumulator A)
6. INDEXED MODE OF ADDRESSING uses two bytes of instruction. The next instruction contains a number (often referred to as an offset) that is added to the contents of the index register to from an address. This new address, as in the extended mode, contains the data.
Example:
ADC A, $D2,X (add the content of address D2 plus the offset with the content of accumulator A with carry flag content, sum into the accumulator A.
7. RELATIVE ADDRESSING MODE the next instruction to be executed by the MPU is located at some other address than the one following. This will be categorized as branch instructions. Such instructions cause the MPU to go to some other address for its next instruction in accordance with some condition within the condition code register. Two bytes long.
FORWARD BRANCHING
PL = DL+2+OFFSET
Example:
If a branch always instruction were located at address 4050 and it was desired to branch to address 4080, what would the contents of 4051 be?
BACKWARD BRANCHING
PL = DL+2-OFFSET
Example:
If a branch always instruction were located at address 4050 and it was desired to branch to address 4000, what would the contents of 4051 be?
Note: PL stands for present location, DL stands for destination location.
INTEL FAMILY
The programming model of the Intel 8086 through the Pentium II
8-bit names
Notes:1. The shaded area registers exist only on the 80386 through the Pentium II.2. The FS and GS register have no special names.
MULTIPURPOSE REGISTERS EAX (Accumulator) referenced as 32-bit register (EAX), as a 16-bit register
(AX), or as either of two 8-bit registers (AH and AL). Used for instructions such as multiplication, division, and some of the adjustment instructions. In 80386 and above, the EAX register may also hold the offset address of a location in the memory system.
AH AX AL
BH BX BL
SP
BP
DI
SI
FLAGS
GS
CS
ES
DS
SS
FS
CH CX CL
DH DX DL
EAX
EBX
ECX
EDX
ESP
EBP
EDI
ESI
EIP
EFLAGS
32-bit names 16-bit name
Accumulator
Base Index
Count
Data
Stack Pointer
Base Pointer
Destination Index
Source Index
IP Instruction pointer
Flags
Code
Data
Extra
Stack
EBX (Base Index) addressable as EBX, BX, BH, or BL. The BX register sometimes holds the offset address of a location in the memory system in all versions of the microprocessor. In 80386 and above, EBX also can address memory data.
ECX (Count) general-purpose register that also holds the count for various instructions. In 80386 and above, the ECX register also can hold the offset address of memory data. Instructions that use a count are the repeated string instructions (REP/REPE/REPNE); shift, rotate, and LOOP/LOOPD instructions. The shift and rotate instructions use CL as the count, the repeated string instructions use CX, and the LOOP/LOOPD instructions use either CX or ECX.
EDX (Data) general-purpose register that holds a part of the result from a multiplication or part of the dividend before a division. IN 80386 and above, this register can also address memory data.
EBP (Base Pointer) points to a memory location in all versions of the microprocessor for memory data transfers. This register is addressed as either BP or EBP.
EDI (Destination Index) often addresses string destination data for the string instructions. It also functions as either a 32-bit (EDI) or 16-bit (DI) general-purpose register.
ESI (Source Index) used as either ESI or SI. The source index register often addresses source string data for the string instructions. Like EDI, ESI also functions as a general-purpose register. As a 16-bit register, it is addressed as SI; as a 32-bit register, it is addressed as ESI.
SPECIAL-PURPOSE REGISTERS EIP (Instruction Pointer) addresses the next instruction in a section of
memory defined as a code segment. This register is IP (16-bits) when the microprocessor operates in the real mode and EIP (32-bits) when the 80386 and above operate in the protected mode. The instruction pointer, which points to the next instruction in a program, is used by the microprocessor to find the next sequential instruction in a program located within the code segment. It can be modified with a jump or a call instruction.
ESP (Stack Pointer) addresses an area of memory called the stack. The stack memory stores data through this pointer. This register is referred to as SP if used as a 16-bit register and ESP if referred to as a 32-bit register.
EFLAGS indicate the condition of the microprocessor and control its operation. The 8086 – 80286 contain a FLAG register (16-bits) and the 80386 and above contain an EFLAG register (32-bit extended flag register).
THE FLAG REGISTER
11 10 9 8 7 6 4 2 0 O D I T S Z A P C
8086/8088/80186/80188
The rightmost five flags and the overflow flag change after many arithmetic and logic instructions execute. The flags never change for any data transfer or program control operation. Some of the flags are also used to control features found in the microprocessor.
C (carry) holds the carry after addition or the borrow after subtraction. The carry flag also indicates error conditions, as dictated by some programs and procedures.
P (parity) a logic 0 for odd parity and a logic 1 for even parity. A (auxiliary carry) holds the carry (half-carry) after addition or the borrow
after subtraction between bits positions 3 and 4 of the result. Z (zero) shows that the result of an arithmetic or logic operation is zero. If
Z=1, the result is zero; of Z=0, the result is not zero. T (trap) enables trapping through an on-chip-debugging feature. (A program
is debugged to find an error or bug). If the T flag is enabled (1), the microprocessor interrupts the flow of the program on conditions as indicated by the debug registers and control registers. If the T flag is logic 0, the trapping (debugging) feature is disabled.
I (interrupt) controls the operation of the INTR (interrupt request) input pin. If I=1, the INTR pin is enabled; if I=0, the INTR pin is disabled. The state of the flag bit is controlled by the STI (set I flag) and CLI (clear I flag) instructions.
D (direction) selects either the increment or decrement mode for the DI and/or SI registers during string instructions. If D=1, the registers are automatically decrement; if D=0, the registers are automatically incremented. The D flag is set with the STD (set direction) and cleared with the CLD (clear direction) instructions.
O (overflow) occurs when signed numbers are added or subtracted. An overflow indicates that the result has exceeded the capacity of the machine.
SEGEMENT REGISTERS CS (code) a section of memory that holds the code (programs and
procedures) used by the microprocessor. This register defines the starting address of the section of memory holding code.
DS (data) a section of memory that contains most data used by a program. Data are accessed in the data segment by an offset address or the contents of other registers that hold the offset address.
ES (extra) is an additional data segment that is used by some of the string instructions to hold destination data.
SS (stack) defines the area of memory used for the stack. The stack segment and stack pointer registers determine the stack entry point. The BP register also addresses data within the stack segment.
Real Mode Memory Addressing Allows the microprocessor to address only the first 1Mbyte of memory even if its Pentium II microprocessor. The first 1Mbyte of memory is called either the real memory or conventional memory system. The DOS operating system requires the microprocessor to operate in this mode. It allows application software.
Segment and Offset Through the combination of these two a memory location is accessed in the real mode. All real mode memory address must consist of a segment address plus an offset address.
Segment Address Defines the beginning address of any 64k-byte memory segment.
Offset AddressSometimes called displacement. Selects any location within the 64k-byte
memory segment. It is the distance above the start of the segment.
Note: Each segment register is internally appended with a 0H on its right end.
Example: Segment register contains 1200H. It addresses a 64k-byte memory
segment, beginning at location 12000H.
The segment address can begin only at a 16-byte boundary, which is called paragraph.
Once the beginning address in known, an ending address is find, by adding FFFFH.
Example:
1000 H -segment address 2000 H - offset12000H - memory location
12000H + 0FFFH = 12FFFH – ending address
The code segment register defines the start of the code segment and the instruction pointer to locate the next instruction within the code segment. This combination (CS:IP or CS:EIP) locates the next instruction executed by the microprocessor.
Example:
CS = 1400H IP/EIP = 1200H
The microprocessor fetches its next instruction from memory location 1400H + 1200H or 15200H.
Stack data are referenced through the stack segment at the memory location addressed by either the stack pointer (SP/ESP) or the base pointer (BP/EBP). These combinations are referred to as SS:SP (SS:ESP) or SS:BP (SS:EBP).
Example:
SS = 2000H BP = 3000H
The microprocessor addresses memory location 23000H for the stack segment memory location.
Protected Mode Memory AddressingAllows access to data and programs located above the first 1Mbyte of
memory as well as within the first 1Mbyte of memory. Segment address is no longer present in this mode. In place of the segment address, the segment register contains a selector that selects a descriptor from a descriptor table. The descriptor describes the memory segment location, length and access rights. Most function in the real mode will function without change in the protected mode. The difference between modes is in the way that the segment register is interpreted by the microprocessor to access the memory segment.
Example:In the real mode, if code segment=008H, the code segment begins at
location 00080H. In the protected mode, the segment number can address any memory location in the entire system for the code segment.
There are two descriptor tables used with the segment registers: one contains global descriptors and the other contains local descriptors.
Global Descriptor Contains segment definitions that apply to all programs. Other term is system descriptor.
Local DescriptorUsually unique to an application. Other term is application descriptor.
Each table contains 8192 descriptors. The base address portion of the descriptor indicates the starting location of the memory segment. The segment limit contains the last offset address found in a segment.
Example:If a segment begins at memory location F00000H and ends at location
F000FFH, the base address is F00000H and the limit is FFH. For the 80286 microprocessor, the base address is F00000H and the limit is 00FFH. For the 80386 microprocessor and above, the base address is 00F00000H and the limit is 000FFH.
There is another feature found in the 80386 through the Pentium II descriptor that is not found in the 80286 descriptor: the G bit or granularity bit. If G=0, the limit specifies a segment limit of 00000H to FFFFFH. If G=1, the value of the limit is multiplied by 4kbytes (appended with XXXH). The limit is then 00000XXXH to FFFFFXXXH, if G=1.
Example:1. If the base address is 10000000H, the limit is 001FFH, and the G bit =0, show
the segment start and end.
Base = Start =10000000HG=0End = Base + Limit =10000000 + 001FFH =100001FFH
2. Uses the same data as example 1, except that the G bit =1.
Base = Start = 10000000HG=0End = Base + Limit = 10000000H + 001FFXXXH = 101FFFFFH
Note: In this example, the XXXH is replaced with FFFH because that is the highest possible memory location within the segment.
Addressing Modes REGISTER ADDRESSINGMODE transfers a copy of a byte or word from the
source register or memory location to the destination register or memory location.
Example: MOV BX,CX
Instruction copies the word-sized contents of register CX into the register BX.
IMMEDIATE ADDRESSING MODE transfers the source-immediate byte or word of data into the destination register or memory location.
Example:MOV EAX, 13456H
Instruction copies the immediate data 13456H into register EAX.
DIRECT ADDRESSING MODE moves a byte or word between a memory location and a register. The instruction set does not support a memory-to-memory transfer, except for the MOVS instruction.
Example:MOV AL, [1234]
Instruction copies word-sized contents of memory location 11234H into register AL.
A F
3 4
7 6
1 2
2 2 3 4
1 1 A C
EAX
EBX
ECX 1 2 3 4
3 3 3 3 6 2 9 1EAX
EBX
MOV EAX, 13456H
13456
AH AL 8AHEAX
EBX
ECX
8A8AH
11235H
11234H
11233H
11232H
Note: This example uses DS = 1000h.
REGISTER INDIRECT ADDRESSING MODE transfers a byte or word between a register and a memory location addressed by an index or base register. The index and base registers are BP, BX, DI, and SI.
Example:MOV AX, [BX]
Instruction copies the word-sized data from the data segment offset address indexed by BX into register AX.
BASE-PLUS-INDEX ADDRESSSING MODE transfers a byte or word between a register and the memory location addressed by a base register (BP or BX) plus an index register (DI or SI).
Example:MOV DX, [BX+DI]
Instruction copies the word sized contents of memory location addressed by the BX and DI to the DX register.
AH 3 4
1 0
AL 1 2
0 0
EAX
EBX
0 1 0 0
CS
DS
3 4
1 2
*1000
1000 2000
341200002002
00002001
00002000
00001002
00001001
00001000
EAX
EBX
ECX
EDX
REGISTER RELATIVE ADDRESSING MODE moves a byte or word between a register and the memory location addressed by an index or base register plus a displacement.
Example:MOV AX, [BX+1000]
Loads AX from the data segment address formed by BX plus 1000.
1 0 0 0
A B
0 3
0 0 1 0
ESP
EBP
ESI
EDI
0 3
Memory
A B
DS X 10H
1010H
1000H
0010H
1000H
0200FH
02015H
02014H
02013H
02012H
02011H
02010H
A B 0 3
2 2 2 2
0 0 0 0
A
7 6
0 1 0 0
EAX
EBX
A 0
7 6
Memory
03101H
03100H
A 0 7 6
Register Array
DS= 100H
BASE-RELATIVE-PLUS INDEX ADDRESSING MODE transfers a byte or word between a register and the memory location addressed by a base and an index register plus a displacement.
Example:MOV AX, [BX+SI+100h]
These instructions load AX from a data segment memory location. It uses an address formed by adding BX, DI and 100h.
A 3 1 6
0 0
2 0 1 6
Memory
A 3
0100H
1000H
1100H
3100H2000H
DS X 10H
10131H10130H
A 3 1 6EAX
EBX
ECX
EDX
Register Array
DS = 200H
PROGRAM MEMORY ADDRESSING MODES
Used with the JMP and CALL instructions, consist of three distinct forms: direct, relative, and indirect.
DIRECT PROGRAM MEMORY ADDRESSINGThe microprocessor uses this form of addressing, but not as often as relative and indirect program memory addressing is used. The instructions for direct program memory addressing store the address with the opcode.
Example:
JMP [10000H]
If a program jumps to memory location 10000H for the next instruction, the address (10000H) is stored following the op-code in the memory. JMP instruction loads CS with 1000H and IP with 0000H to jump to memory location 10000H for the next instruction.
The 5-byte machine language version of a JMP [10000H] instruction.
An intersegment jump is a jump to any memory location within the entire memory system. The direct jump is often called a far jump because it can jump to any memory location for the next instruction. The only other instruction that uses direct program addressing is the intersegment or far CALL instruction.
0 0 1 0
ESP
EBP
ESI
DS X 10H
0100H
1000H
0010H
0020H
0030H 0130
H
10130H
Displacement = 100H, DS = 100H
E A 0 0 0 0 0 0 1 0
Opcode Offset(low) Offset(high)Segment(low)
Segment (high)
Usually, the name of a memory address, called a label, refers to the location that is called or jumped to instead of the actual numeric address. When using a label with the CALL or JMP instruction, most assemblers select the best from of program addressing.
RELATIVE PROGRAM MEMORY ADDRESSING The term relative means “relative to the instruction pointer (IP).
Example:
JMP [2]
If a jump instruction skips the next two bytes of memory, the address in relation to the instruction pointer is a 2 that adds to the instruction pointer. It is a one-byte instruction.
With a one-byte or a two-byte displacement that adds to the instruction pointer. A one-byte displacement is used in short jumps, and a two-byte displacement used with near jumps and calls. Both types are considered to be instrasegment jump, a jump anywhere within the current code segment. Relative JMP and CALL instructions contain either an 8-bit or a 16-bit signed displacement that allows a forward memory reference or reverse memory reference. An 8-bit displacement (short) has a jump range of between +127 and –128 bytes from the next instruction, while a 16-bit displacement (near) has a range of 32K bytes.
INDIRECT PROGRAM MEMORY ADDRESSINGIf a 16-bit register holds the address of a JMP instruction, the jump is near.
Example:
If the BX register contains a 1000H and a JMP BX instruction executes, the microprocessor jumps to offset address 1000H in the current code segment.
If a relative register holds the address, the jump is also considered to be an indirect jump.
1000010001100021000310004
EB02--
JMP [2]
Example:
JMP [BX]
Refers to the memory location within the data segment at the offset address contained in BX. At this offset address is a 16-bit number that is used as the offset address in the intrasegment jump. This type of jump is sometimes called an indirect-indirect or double-indirect jump.
STACK MEMORY ADDRESSING MODES
Two registers maintain the stack memory: the stack pointer (SP or ESP) and the stack segment register (SS). Whenever a word of data is pushed onto the stack, the higher-order 8-bits are placed in the location addressed by SP – 1. The low order 8-bits are placed in the location addressed by SP – 2. The SP is then decremented by 2 so that the next word of data is stored in the next available stack memory location. The SP/ESP register always points to an area of memory located within the stack segment. The SP/ESP register adds to SS x 10H to form the stack memory address. Whenever data are popped from the stack, the low-order 8-bits are removed from the location addressed by SP. The high-order 8-bits are removed from the location addressed by SP + 1. The SP register is then incremented by 2.
Example:
a. PUSH BX (places the contents of BX onto the stack)b. POP CX (removes data from the stack and places them into CX.
PUSH BX
1 2 3 4 1 2
3 4
1 2 3 4
Memory
Register Array
EAX
EBX
ECX
EDX
POP CX
DATA MOVEMENT INSTRUCTIONS
ESP
SS x 10H
1 2 3 4
1 2
3 4
Register Array
SS x 10H
ESP
EAX
EBX
ECX
EDX
1 2 3 4
16-bit instruction mode
Opcode1-2 bytes
Immediate0-2 bytes
Displacement0-1 byte
MOD-REG-R/M0-1 BYTE
D W
Opcode MOD REG R/M
FIG 1
The opcode selects the operation (addition, subtraction, move, and so on) that is performed by the microprocessor. The opcode is either one or two bytes long for most machine language instructions. The first six bits of the first byte (FIG 2) are the binary opcode. The remaining two bits indicate the direction (D) or direction flag bit of the data flow, and indicate whether the data are a byte or a word (W). If the direction bit (D) =1, data flow to the REG field from the R/M field located in the second byte (FIG 3) of an instruction. If the D-bit = 0 in the opcode, data flow to the R/M field from the REG field. If the W-bit =1, the data size is a word or doubleword; if the W-bit = 0, the data size is always a byte. The W-bit appears in most instructions, while the D-bit appears mainly with the MOV ans some other instructions. The MOD filed specifies the addressing (MOD) for the selected instruction. The MOD field selects the type of addressing and whether a displacement is present with the selected type. If the MOD field contains 11, it selects the register-addressing mode. Register addressing uses the R/M field to specify a register instead of a memory location. If the MOD field contains 00, 01, or 10, the R/M field selects one of the data memory-addressing modes. When MOD selects a data memory-addressing mode, it indicates that the addressing mode contains no displacement (00), an 8-bit sign-extended displacement (01), or a 16-bit displacement (10).
MOD FUNCTION
00 No displacement01 8-bit sign-extended displacement10 16-bit displacement11 R/M is a register
FOR REG and R/M (when MOD =11)
CODE W = 0 (BYTE) W = 1 (WORD)000 AL AX001 CL CX010 DL DX011 BL BX100 AH SP101 CH BP110 DH SI111 BH DI
FIG 2 FIG 3
TABLE 1
TABLE 2
FOR R/M (when MOD = 00, 01, or 10)
R/M Code Addressing Mode000 DS:[BX + SI]001 DS:[BX + DI]010 SS:[BP + SI]011 SS:[BP + DI]100 DS:[SI]101 DS:[DI]110 SS:[BP]*111 DS:[BX]
Examples:
1.
2.
3.
4.
5.
1 10 0 0 1 0 1 1 1 001101
1 01
0 0 0 1 0 1 0 0 101010
1 00 0 0 1 0 0 0 0 011010
0 01
0 0 0 0 0 0 0 0 000010
1 00 0 0 1 0 0 0 1 011010
0 0 0 0 0 0 0 0
1 11 0 0 0 1 1 1 0 111000
0 01
0 0 0 0 0 0 0 0 000010
0 00 1 1 0 1 0 0 0 010010
SEGMENT OVERRIDE PREFIXMay be added to almost any instruction in any memory addressing mode,
allows the programmer to deviate from the default segment. It is an additional byte that appends the front of an instruction to select an alternate segment register. The only instructions that cannot be prefixed are the jump and call instructions that must use the code segment register for address generation.
Example:
MOV AX, [DI]
Accesses data within the data segment by default. If required by a program, prefixing the instruction can change this. Suppose that the data are in the extra segment instead of in the data segment. This instruction addresses the extra segment if changed to:
MOV AX, ES:[DI]
Assembly Language Segment Accessed Default SegmentMOV AX, DS:[BP] Data StackMOV AX, ES:[BP] Extra StackMOV AX, SS:[D] Stack Data
MOV AX, CS:LIST Code DataMOV AX, ES:[SI] Extra DataLODS ES:DATA1 Data Extra
ASSEMBLER DIRECTIVESControls the assembly process. Directives indicate how an operand or
section of a program is to be processed by the assembler. Some directives generate and store information in the memory, while the others do not.
DB (define byte) DW (define word) DD (define doubleword)
DQ (define quadword) DT (define ten bytes) SEGMENT indicate the start of the segment and its symbolic name ENDS indicate the end of the segment ? operand for DB, DW, or DD directive, used for memory reservation, the
assembler stores a zero into locations specified by this DUP (duplicate) creates an array ALIGN ensures that the memory are stored on byte boundaries ALIGN 2 places data on word boundaries ALIGN 4 PLACES THEM ON DOUBLEWORD BOUNDARIES EQU (equate) equates a numeric THIS always appear as THIS BYTE, THIS WORD, or THIS DWORD. In
certain cases, data must be referred to as both a byte and a word. The assembler can only assign either a byte or a word address to a label. To assign a byte label to a word use this directive
ORG (origin) changes the starting offset address of the data in the data segment to any location.
ASSUME tells the assembler what names have been chosen for the code, data, extra, and stack segments. Without this, the assembler assumes nothing and automatically uses a segment override prefix on all instructions that address memory data.
PROC indicate the start of the procedure ENDP indicate the end of the procedure, requires a label to indicate the name
of the procedure. Must also be followed with a NEAR or FAR. A NEAR procedure is one that resides in the same code segment as the program. A FAR procedure may reside at any location in the memory system. Often the call NEAR procedure is considered to be local, and the call FAR is considered to be global. The term global denotes a procedure that can be used by any program, while local defines a procedure that is only used by the current program.
USES indicates which registers are used by the procedure, so that the assembler can automatically save them before your procedure begins and restore them before the procedure ends with the RET instruction.
.MODEL followed by the size of the memory system. TINY model requires that all software and data fit into one 64K-byte memory
segment, useful for many small programs SMALL model requires that only one data segment be used with one code
segment, for a total of 128K-bytes of memory. .EXIT returns to DOS, but the error code is not defined .EXIT 0 returns to DOS with an error code 0 (no error)
SAMPLE PROGRAMS
DATA1 DB 1, 2, 3 ;define bytes
DB 45H ; hexadecimalDB ‘A’ ; ASCIIDB 11110000B ; binary
DATA2 DW 12, 13 ; define wordsDW LIST1 ; symbolicDW 2345H ; hexadecimal
DATA3 DD 300H ; hexadecimalDD 2.123 ; realDD 3.34E+12 ; real
LISTA DB ? ; reserve 1 byte LISTB DB 10 DUP (?) ; reserve ten bytes ALIGN 2 ; set word boundaries
LISTC DW 100H DUP (0) ; word array LIST_0 DD 22 DUP (?) ; doubleword array TEN EQU 10
NINE EQU 9MOV AL, TENMOV AL, NINE
DATA_SEG SEGMENTORG 100H
DATA1 EQU THIS BYTE DATA2 DW ? DATA_SEG ENDS CODE_SEG SEGMENT ‘CODE’
ASSUME CS:CODE_SEG, DS:DATA_SEG MOV BL, DATA1
MOV AX, DATA2MOV BH, DATA1+1
CODE_SEG ENDS ADDEM PROC FAR ;start procedure
ADD BX, CXADD BX, DXMOV AX, BXRET
ADDEM ENDP ; end procedure ADDS PROC NEAR USES BX CX DX
Push bxPush cxPush dxAdd bx, axAdd cx, bxAdd dx. CxMov ax,dxRetPop dx
Pop cxPop bxRet 00000h
ADDS ENDP
INSTRUCTION SETS
DATA TRANSFER INSTRUCTIONS
MOV destination, source (move byte or word data. Example: MOV BX, [DI] loads the data stored at the memory location
addressed by [DI] into register BX.PUSH source (push word onto stack)Example: PUSH BX places data from the source register BX into
the stack.POP destination (pop word off stack)
Example: POP CX places data from the stack into register CX.IN accumulator, port (input byte or word from port)
Example: IN AL, p8 8 bits are input to AL from I/O port p8.OUT port, accumulator (output byte or word to port)
Example: OUT p8, AX 16 bits are output from AX to I/O port p8.LEA destination, source (load effective address)Example: LEA BX, [DI] loads the offset address specified by [DI]
(contents of DI) into BX register.
PUSHF (push flag onto stack)POPF (pop flags off stack)XCHG destination, source (exchange byte or word)
Example: XCHG AL, [DI] exchanges the content of the memory location addressed by [DI] with the content of AL.
XLAT translate_table (translate byte)Example: MOV AL,4 translate 4 into its equivalent from table.
MOV BX, OFFSET TABLEXLATMOVE CODE7, AL
LDS destination, source (load pointer using DS)Example: LDS BX, [DI] transfers the 32bit number, addressed by DI in
data segment, into the BX and DS register.LES destination, source (load pointer using ES)
Example: LES BX, [DI] transfers the 32bit number, addressed by DI inextra segment, into the BX and ES register.
LAHF (load AH register from flags)SAFH (store AH register into flags)
ARITHMETIC INSTRUCTIONS ADD destination, source (add byte or word)Example: ADD AL, BL BL contents add to the contents of AL with the
sum stored in AL.
ADC destination, source (add byte or word with carry)Example: ADC AL, AH the byte contents of AH add to the content of
AL with carry with the sum stored in AL.INC destination (increment byte or word by 1)Example: INC BL adds 1 to the content of BL.SUB destination, source (subtract byte or word)Example: SUB CL, BL subtract the contents of BL from the contents
of CL with the difference stored in CL.SBB destination, source (subtract byte or word with borrow)Example: SBB AH, AL both carry and contents of AL subtract from the
contents of AH with the difference stored in AH.
DEC destination (decrement byte or word by 1)Example: DEC BH subtracts 1 from the byte content of BH.CMP destination, source (compare byte or word)Example: CMP CL, BL BL content subtracts from the content of CL
without changing the content of the destinationUsually followed by JA or JB.
MUL source (multiply byte or word unsigned)Example: MUL CL AL content is multiplied by CL content; the
unsigned product is stored in AX.MUL DX AX content is multiplied by DX content, the
unsigned product is stored in DX-AX.IMUL source (integer multiply byte or word)Example: IMUL DH AL content is multiplied by DH content, the
signed product is stored in AX. IMUL CX AX content is multiplied by CX content, the
signed product is stored in DX-AX.DIV source (divide byte or word unsigned)Example: DIV CL AX content is divided by the content of CL,
The unsigned quotient is stored in AL and the remainder is stored in AH.
DIV CX DX-AX content is divided by the content of CX, The unsigned quotient is stored in AX and the remainder is stored in DX.
IDIV source (integer divide byte or word)Example: IDIV BL AX content is divided by the content of BL, the
Signed quotient is stored in AL and the remainder is stored in AH.
IDIV SI DX-AX content is divided by the content of SI, The signed quotient is stored in AX and the remainder is stored in DX.
NEG destination (negate byte or word)Example: NEG CH CH content is 2’s complemented
CBW (convert byte to word)CWD (convert word to double word)
DAA (decimal adjust for addition)DAS (decimal adjust for subtraction)AAA (ASCII adjust for addition)AAS (ASCII adjust for subtraction)AAM (ASCII adjust for multiply)AAD (ASCII adjust for division)
BIT MANIPULATION INSTRUCTIONS
NOT destination (NOT byte or word)Example:
AND destination, source (AND byte or word)Example: AND AL, BL AL content is ANDed with the content of BL,
Result is stored in AL.OR destination, source (OR byte or word)Example: OR AH, BL AH content is Ored with the content of BL,
Result is stored in AH.XOR destination, source (Exclusive-OR byte or word)Example: XOR CH, DL CH content is exclusive-ORed with the,
contents of DL, result is stored in CH.TEST destination, source (test byte or word)
Example: TEST DL, DH content of DL is ANDed with the content ofDH without changing the destination.
BT register, bit_numberExample: BT AX, 4 Test bit position in AX. The result of the test is
Located in the carry flag bit. If bit position 4 is A 1, carry is set; if bit position 4 is 0, carry isCleared.
BTC register, bit_number Example: .BTC AX, 4 Complement bit position 4 after testing it.BTR register, bit_numberExample: BTR AX, 4 Clears bit position 4 after the test.BTS register, bit_numberExample: BTS AX, 4 Sets bit position 4 after the test.SHL/SAL destination, count (shift logical/arithmetic left byte or word)Example: SHL AX, 1 AX is logically shifted left 1 place
SAL AX, 10 AX is arithmetically shifted left 10 places.
SHR destination, count (shift logical right byte or word)Example: SHR BX, 12 BX is logically shifted right 12 places
SAR destination, count (shift arithmetic right byte or word)Example: SAR SI, 2 SI is arithmetically shifted right 2 places
ROL destination, count (rotate left byte or word)Example: ROL SI, 14 SI rotates left 14 places
ROR destination, count (rotate right byte or word)Example: ROR SI, 2 SI rotate right 2 places
0
C DATA
0
DATA C
SIGN BIT
DATA C
C DATA
DATA C
RCL destination, count (rotate left through carry byte or word)\Example: RCL BL, 6 BL rotates left through carry 6 places
RCR destination, count (rotate right through carry byte or word)Example: RCR AH, CL AH rotates right through carry the number of
places specified by CL
STRING INSTRUCTIONS
MOVS destination-string, source-string (move string)Example: MOVS BYTE1, BYTE2 ES:[DI]=DS:[SI];DI=DI1;SI=SI1
MOVS WORD1,WORD2 ES:[DI]=DS:[SI];DI=DI2;SI=SI2MOSB/MOVSW (move byte or word string)Example: MOVSB ES:[DI]=DS:[SI];DI=DI1;SI=SI1
MOVSW ES:[DI]=DS:[SI];DI=DI2;SI=SI2
CMPS destination-string (compare byte or word string)Example: CMPS Compare two sections of memory data, the
contents of data segment memory locationaddressed by SI is compared with the contents of the extra segment memory location addressed by DI
CMPSB string bytes are comparedCMPSW string word are compared
SCAS destination-string (scan byte or word string)Example: SCAS compares the AL register with a byte block of
Memory, the AX register with a word block of memory
C DATA
DATA C
SCASB subtract the content of memory location fromAL, without affecting either register or the memory location
SCASW subtract the content of memory location from AX, without affecting either register or thememory location
LODS source-string (load byte or word string)Example: LODS BYTE AL=DS:[SI];SI=SI1
LODS WORD AX=DS:[SI];SI=SI2LODSB AL=DS:[SI];SI=SI1LODSW AX=DS:[SI];SI=SI2
STOS destination-string (store byte or word string)Example: STOS BYTE ES:[DI]=AL;DI=DI1
STOS WORD ES:[DI]=AX;DI=DI2STOSB ES:[DI]=AL;DI=DII1STOSW ES:[DI]=AX;DI=DI2
NOTE:
MOVS (move string) and STOS (store string) make use of the REP (repeat), when preceded by REP, these string operations repeat until CX decrements to 0.
SCAS (scan string) and CMPS (compare string) make use of1. RPE (repeat while equal) and REPZ (repeat while zero)
Each time SCAS or CMPS completes its operation the zero flag is tested and execution continues (repeats) as long as the zero flag is set.
2. REPNE (repeat while not equal) and REPNZ (repeat while not zero) also repeats as long as CX does not equal to 0, but require that the zero flags be cleared to continue.
Repeating string as follows:1. Repeat while CX does not equal to 0.2. Repeat while CX does not equal to 0 and the zero flag is set.3. Repeat while CX does not equal to 0 and the zero flag is cleared.
LOOP AND JUMP INTRUCTIONS
Unconditional JUMP
JMP target (unconditional jump to target)1. Direct jump the address is given in the instruction.2. Indirect jump the target address might be contained in a register or a
memory location.
Conditional JUMP
JNC jump if no carryJAE jump if above or equal
JNB jump if not belowJC jump if carryJB jump if belowJNAE jump if not above nor equalJNZ jump if not zeroJNE jump if not equal JZ jump if zeroJE jump if equalJNS jump if no signJS jump if signJNO jump if no overflowJO jump if overflowJNP jump if no parityJP jump if parityJPE jump if parity evenJA jump if aboveJBNE jump if not below nor equalJBE jump if not below or equalJNA jump if not above
JGE jump if greater or equalJNL jump if not lessJL jump if less
JNGE jump if not greater nor equalJG jump if greater
JNLE jump if not less or equalJLE jump if less or equal
JNG jump if not greater
LOOP short-label (loop)LOOPE/LOOPZ short-label (loop if equal/ loop if zero)JCXZ short-label (jump if CX =0)
PROGRAM CONTROL INSTRUCTIONS
CALL PROCEDURE-NAME (call procedure)RET optional-pop-value (return from procedure)
CLC (clear carry flag)STC (set carry flag)CMC (complement carry flag)CLD (clear direction flag)STD (set direction flag)
CLI (clear interrupt enable flag)STI (set interrupt-enable flag)
HLT (halt until interrupt or reset)WAIT (wait for test pin active)
NOP (no operation)LOCK (lock bus during next instruction)
ESC (escape to external processor)
OTHER INSTRUCTIONS IN INTEL BUT NOT AVAILABLE IN 8086/8088INS (input string)Example: INS BYTE ES:[DI]=[DX];DI=DI1
INS WORD ES:[DI]=[DX];DI=DI2INSB ES:[DI]=[DX];DI=DI1INSW ES:[DI]=[DX];DI=DI2
OUTS (output string)Example: OUTS BYTE [DX]=DS:[SI];SI=SI1
OUTS WORD [DX]=DS:[SI];SI=SI2
OUTSB [DX]=DS:[SI];SI=SI1OUTSW [DX]=DS:[SI];SI=SI2
MOVSX (move and sign extend) and MOVZX (move and zer0-extend)Example: MOVSX CX, BL sign-extends BL into CX
MOVZX DX, AL zero-extends AL into DX
NOTE: when a number is zero-extended, the most significant part fills with zeros. For example, if an 8-bit 34H is zero-extended into a 16-bit number, it becomes 0034H. A number is signed-extended when its sign-bit is copied into most significant part. For example, if an 8-bit 84H into a 16-bit number, it becomes FF84H. The sign bit of an 84H is a one, which is copied into the most significant part of the sign-extended result.CMOV (conditional move) move the data only if the condition is trueCMOVZ move data only if the result from some prior
Instruction is zero.CMOVB move if belowCMOVAE move if above or equalCMOVBE move if below or equalCMOVA move if aboveCMOVE or CMOVZ move if equal or set if zeroCMOVNE or CMOVNZ move if not equal or set if not zeroCMOVL move if less thanCMOVLE move if less than or equalCMOVG move if greater thanCMOVGE move if greater than or equalCMOVS move if signCMOVNS move if no signCMOVC move if carryCMOVNC move if no carryCMOVO move if overflowCMOVNO move if no overflowCMOVP or CMOVPE move if parity or set if parity evenCMOVNP or CMOVPO move if no parity or set if parity odd
INTERRUPTSInterrupt either hardware generated CALL (externally derived from
hardware signal or software generated CALL (internally derived from the execution of an instruction or by some other internal event). Sometimes an
internal interrupt is called an exception. Interrupt vector is a four-byte stored in the first 1024 bytes of the memory (000000H-0003FFH) when the microprocessor operates in the real mode. In the protected mode, an interrupt descriptor table that uses eight-byte descriptors to describe each of the interrupts replaces the vector table.
INT interrupt-type (interrupt)There are 256 different software interrupt instructions. It has a numeric
operand that ranges from 0-255 (00H-FFH). It is two bytes long. Th first byte contains the op-code, and the second byte contains the vector type number. Exception is INT 3.
IRET (interrupt return)The interrupt return instruction. It is used only with software or hardware
interrupt service procedures. It pop the stack data back into the IP, pop stack back into CS and pop stack data back into flag register. It restores the content of I and T from the stack.
INTO (interrupt on overflow0Interrupt on overflow. It is a conditional software interrupt that tests the
overflow flag(O). If )=0, the INTO instruction performs no operation; if O=1 and an INTO instruction executes, an interrupt occurs via vector type number 4.
INT 3 (special software interrupt used for breakpoints)It is a one-byte instruction. This is used to interrupt or break the flow
of the software. Breakpoint occurs for any software interrupts, which helps to debug faulty software.PENTIUM AND PENTIUM PRO MICROPROCESSORS
Segment RegisterFS and GS are supplemental segment registers available in the 80386, 80486, Pentium and Pentium pro microprocessors to allow two additional memory segments for access by programs.
Flags
IOPL (I/O privilege level) used in protected mode operation to select the privilege level for I/O devices. I/O executes without hindrance if the privilege level is higher than the IOPL otherwise an interrupt will occur, causing the execution to suspend. Highest is 00 lowest is 11.
NT (nested task) indicates that the current task is nested within another task in protected mode operation. Set when the task is nested by software.
RF (resume) used with debugging to control the resumption of execution after the next instruction.
VM (virtual mode) selects virtual mode operation in a protected mode system. Allows multiple DOS memory partitions that are 1M byte in length to coexists in the memory system and allows system program to execute multiple DOS programs.
AC (alignment check) activates if a word or double word is addressed on a non-word or non-double-word boundary. 486 have this for its companion numeric coprocessor, while 487 for synchronization.
VIF (virtual interrupt flag) a copy of the interrupt flag bit available to the Pentium-Pentium II microprocessors.
VIP (virtual interrupt pending) provides information about a virtual mode interrupt for the Pentium-Pentium II microprocessors. Used in multitasking environments to provide the operating system with virtual interrupt flag and interrupt pending information.
ID (identification) indicates that the Pentium-Pentium II microprocessors support the CPUID instruction. This instruction provides the system with information about Pentium microprocessors, such as its version number and manufacturer.
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