Sequential Logic and Flip-Flops

SEQUENTIAL CIRCUITS AND FEEDBACK

SET- RESET (S-R) LATCHES : Cross- NOR S-R latch ( active high ) Cross- NAND S-R latch ( active low )

Cross-NOR S-R latch ( active high )

truth table of the NOR gate AB(A + B)’

001

010

100

110

if any of the inputs of the NOR gate is high (logic 1), the output is low (logic 0)

No-Change condition in S-R latch

Forbidden condition in S-R latch

function table of the NOR S-R latch

RSQQ’Comments

00QQ’No change ( hold ) condition

0110Set

1001Reset

1100Forbidden, Not used , race

the race situation If we go from SR = 11 to SR = 00, then we may have two

cases. Case 1: R changes first: SR = 10 then SR = 00 Case 2: S changes first: SR = 01 then SR = 00

1

1

0

Cross- NAND S-R latch ( active low ) – S’-R’ The truth table of NAND gate

Functions table of the NAND latch .

S – R Timing Analysis

EXAMPLE If the S and R waveforms shown in Fig (11.a) are applied to

the inputs of the NOR latch, determine the waveform that will be applied on the Q output. Assume that Q is initially low.

Switch Debouncing Circuits Switch bounce occurs as a mechanical switch lever snaps to a

new position. After reaching the new contact point, the pole bounces on a micrometer scale of millisecond duration (Fig (12)). Bounce can cause problems in circuits that are expecting an input to stabilize without oscillating, such as counters.

Debouncing using S’-R’ latch

When the switch is neither connected to the lower pin nor to the upper pin, both S’ and R’ equal + 5v ( Logic 1 ) and the latch is in the no change state .

Debouncing using S’-R’ latch (cont.)

Clocked SR latches ( flip – flops )

clocked (gated) latch using cross – NAND gates

Function table of gated S-R flip – flop

EXAMPLE Determine the Q output waveform if the inputs

shown in Fig (17-a) are applied to a clocked (gated) S-R latch that is initially RESET.

GATED D- latch

EXAMPLE Sketch the output waveform at Q for the inputs at

D and G of the gated D latch in Fig (20).

EXAMPLE Construct a D flip-flop using NOR and AND

gates.

J–K FLIP – FLOPS

J–K FLIP – FLOPS

T. (TOGGLE) FLIP–FLOP

Race problem in level-clocked J-K flip-flop

Clock edge and level edge – triggered FFs Master – slave FFs .

MASTER – SLAVE FLIP-FLOPS

Timing diagram of a master-slave FF

EDGE – TRIGGERED J K FFS

+ve edge triggered -ve edge triggered

EXAMPLE Determine the Q

output waveform if the inputs shown in Fig (32) are applied to a clocked S-R flip-flop that is initially RESET. The flip-flop is triggered at the positive edge.

MASTER-SLAVE FLIP-FLOP AND 1S CATCHING

DIRECT ( ASYNCHRONOUS ) INPUTS

FLIP- FLOP OPERATING CHARACTERISTICS Propagation Delay times:

SET-UP TIME HOLD TIME

Propagation Delay times:

Propagation Delay times:

SET-UP TIME

HOLD TIME