Lecture 11: Sequential Circuit Design

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 2

Outlineq Sequencingq Sequencing Element Designq Max and Min-Delayq Clock Skewq Time Borrowingq Two-Phase Clocking

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 3

Sequencingq Combinational logic

– output depends on current inputsq Sequential logic

– output depends on current and previous inputs– Requires separating previous, current, future– Called state or tokens– Ex: FSM, pipeline

CL

clk

in out

clk clk clk

CL CL

PipelineFinite State Machine

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 4

Sequencing Cont.q If tokens moved through pipeline at constant speed,

no sequencing elements would be necessaryq Ex: fiber-optic cable

– Light pulses (tokens) are sent down cable– Next pulse sent before first reaches end of cable– No need for hardware to separate pulses– But dispersion sets min time between pulses

q This is called wave pipelining in circuitsq In most circuits, dispersion is high

– Delay fast tokens so they don�t catch slow ones.

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 5

Sequencing Overheadq Use flip-flops to delay fast tokens so they move

through exactly one stage each cycle.q Inevitably adds some delay to the slow tokensq Makes circuit slower than just the logic delay

– Called sequencing overheadq Some people call this clocking overhead

– But it applies to asynchronous circuits too– Inevitable side effect of maintaining sequence

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 6

Sequencing Elementsq Latch: Level sensitive

– a.k.a. transparent latch, D latchq Flip-flop: edge triggered

– A.k.a. master-slave flip-flop, D flip-flop, D registerq Timing Diagrams

– Transparent– Opaque– Edge-trigger

D Flop

Latc

h

Q

clk clk

D Q

clk

D

Q (latch)

Q (flop)

D Flop

Latc

h

Q

clk clk

D Q

clk

D

Q (latch)

Q (flop)

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 7

Latch Designq Pass Transistor Latchq Pros

+ Tiny+ Low clock load

q Cons– Vt drop– nonrestoring– backdriving– output noise sensitivity– dynamic– diffusion input

D Q

f

Used in 1970�s

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 8

Latch Designq Transmission gate

+ No Vt drop- Requires inverted clock D Q

f

f

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 9

Latch Designq Inverting buffer

+ Restoring+ No backdriving+ Fixes either

• Output noise sensitivity• Or diffusion input

– Inverted output

D

f

f

X Q

D Q

f

f

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 10

Latch Designq Tristate feedback

+ Static– Backdriving risk

q Static latches are now essentialbecause of leakage

f

f f

f

QD X

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 11

Latch Designq Buffered input

+ Fixes diffusion input+ Noninverting

f

f

QD X

f

f

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 12

Latch Designq Buffered output

+ No backdriving

q Widely used in standard cells+ Very robust (most important)- Rather large- Rather slow (1.5 – 2 FO4 delays)- High clock loading

f

f

Q

D X

f

f

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 13

Latch Designq Datapath latch

+ smaller+ faster- unbuffered input

f

f f

f

Q

D X

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 14

Flip-Flop Designq Flip-flop is built as pair of back-to-back latches

D Q

f

f

f

f

X

D

f

f

f

f

X

Q

Qf

f

f

f

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 15

Enableq Enable: ignore clock when en = 0

– Mux: increase latch D-Q delay– Clock Gating: increase en setup time, skew

D Q

Latc

h

D Q

en

en

f

f

Latc

hDQ

f

0

1

en

Latc

h

D Q

f en

DQ

f

0

1

enD Q

f en

Flop

Flop

Flop

Symbol Multiplexer Design Clock Gating Design

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 16

Resetq Force output low when reset assertedq Synchronous vs. asynchronous

D

f

f

f

f

Q

Qf

f

f

f

reset

D

f

ff

f

f

f

Qf

f

Dreset

f

f

Qf

f

Dreset

reset

f

f

reset

Synchronous Reset

Asynchronous Reset

Symbol Fl

opD QLa

tch

D Q

reset reset

f f

f

f

Q

reset

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 17

Set / Resetq Set forces output high when enabled

q Flip-flop with asynchronous set and reset

D

f

f

f

ff

f

Q

f

f

reset

set reset

set

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 18

Sequencing Methodsq Flip-flopsq 2-Phase Latchesq Pulsed Latches

Flip-FlopsFl

opLa

tch

Flop

clk

f1

f2

fp

clk clk

Latc

h

Latc

h

fp fp

f1 f1f2

2-Phase Transparent LatchesPulsed Latches

Combinational Logic

CombinationalLogic

CombinationalLogic

Combinational Logic

Latc

h

Latc

h

Tc

Tc/2tnonoverlap tnonoverlap

tpw

Half-Cycle 1 Half-Cycle 1

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 19

Timing Diagrams

Flop

A

Y

tpdCombinational

LogicA Y

D Q

clk clk

D

Q

Latch

D Q

clk clk

D

Q

tcd

tsetup thold

tccq

tpcq

tccq

tsetup tholdtpcq

tpdqtcdq

tpd Logic Prop. Delay

tcd Logic Cont. Delay

tpcq Latch/Flop Clk->Q Prop. Delay

tccq Latch/Flop Clk->Q Cont. Delay

tpdq Latch D->Q Prop. Delay

tcdq Latch D->Q Cont. Delay

tsetup Latch/Flop Setup Time

thold Latch/Flop Hold Time

Contamination and Propagation Delays

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 20

Max-Delay: Flip-Flops

F1 F2

clk

clk clk

Combinational Logic

Tc

Q1 D2

Q1

D2

tpd

tsetuptpcq

tpd ≤ Tc − tsetup + tpcq( )sequencing overhead! "# $#

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 21

Max Delay: 2-Phase Latches

Tc

Q1

L1

f1

f2

L2 L3

f1 f1f2

CombinationalLogic 1

CombinationalLogic 2

Q2 Q3D1 D2 D3

Q1

D2

Q2

D3

D1

tpd1

tpdq1

tpd2

tpdq2

tpd = tpd1 + tpd 2 ≤ Tc − 2tpdq( )sequencing overhead!"#

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 22

Max Delay: Pulsed Latches

Tc

Q1 Q2D1 D2

Q1

D2

D1

fp

fp fp

Combinational LogicL1 L2

tpw

(a) tpw > tsetup

Q1

D2(b) tpw < tsetup

Tc

tpd

tpdq

tpcq

tpd tsetup

tpd ≤ Tc − max tpdq ,tpcq + tsetup − tpw( )sequencing overhead

! "#### $####

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 23

Min-Delay: Flip-Flops

holdcd ccqt t t³ - CL

clk

Q1

D2

F1

clk

Q1

F2

clk

D2

tcd

thold

tccq

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 24

Min-Delay: 2-Phase Latches

tcd1,tcd 2 ≥ thold − tccq − tnonoverlap CL

Q1

D2

D2

Q1

f1

L1

f2

L2

f1

f2

tnonoverlap

tcd

thold

tccq

Hold time reduced by nonoverlap

Paradox: hold applies twice each cycle, vs. only once for flops.

But a flop is made of two latches!

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 25

Min-Delay: Pulsed Latches

tcd ≥ thold − tccq + tpw CL

Q1

D2

Q1

D2

fp tpw

fp

L1

fp

L2tcd

thold

tccq

Hold time increased by pulse width

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 26

Time Borrowingq In a flop-based system:

– Data launches on one rising edge– Must setup before next rising edge– If it arrives late, system fails– If it arrives early, time is wasted– Flops have hard edges

q In a latch-based system– Data can pass through latch while transparent– Long cycle of logic can borrow time into next– As long as each loop completes in one cycle

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 27

Time Borrowing Example

Latc

h

Latc

h

Latc

h

Combinational Logic CombinationalLogic

Borrowing time acrosshalf-cycle boundary

Borrowing time acrosspipeline stage boundary

(a)

(b) Latc

h

Latc

hCombinational Logic Combinational

Logic

Loops may borrow time internally but must complete within the cycle

f1

f2

f1 f1

f1

f2

f2

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 28

How Much Borrowing?

Q1

L1

f1

f2

L2

f1 f2

Combinational Logic 1Q2D1 D2

D2

Tc

Tc/2 Nominal Half-Cycle 1 Delay

tborrow

tnonoverlap

tsetup

( )borrow setup nonoverlap2cTt t t£ - +

2-Phase Latches

borrow setuppwt t t£ -

Pulsed Latches

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 29

Clock Skewq We have assumed zero clock skewq Clocks really have uncertainty in arrival time

– Decreases maximum propagation delay– Increases minimum contamination delay– Decreases time borrowing

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 30

Skew: Flip-Flops

F1 F2

clk

clk clk

Combinational Logic

Tc

Q1 D2

Q1

D2

tskew

CL

Q1

D2

F1

clk

Q1

F2

clk

D2

clk

tskew

tsetup

tpcq

tpdq

tcd

thold

tccq

tpd ≤ Tc − tpcq + tsetup + tskew( )sequencing overhead! "## $##

tcd ≥ thold − tccq + tskew

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 31

Skew: Latches

Q1

L1

f1

f2

L2 L3

f1 f1f2

CombinationalLogic 1

CombinationalLogic 2

Q2 Q3D1 D2 D3

tpd ≤ Tc − 2tpdq( )sequencing overhead!"#

tcd1,tcd 2 ≥ thold − tccq − tnonoverlap + tskew

tborrow ≤Tc

2− tsetup + tnonoverlap + tskew( )

2-Phase Latches

tpd ≤ Tc − max tpdq ,tpcq + tsetup − tpw + tskew( )sequencing overhead

! "##### $#####

tcd ≥ thold + tpw − tccq + tskew

tborrow ≤ tpw − tsetup + tskew( )

Pulsed Latches

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 32

Two-Phase Clockingq If setup times are violated, reduce clock speedq If hold times are violated, chip fails at any speedq In this class, working chips are most important

– No tools to analyze clock skewq An easy way to guarantee hold times is to use 2-

phase latches with big nonoverlap timesq Call these clocks φ1, φ2 (ph1, ph2)

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 33

Safe Flip-Flopq Past years used flip-flop with nonoverlapping clocks

– Slow – nonoverlap adds to setup time– But no hold times

q In industry, use a better timing analyzer– Add buffers to slow signals if hold time is at risk

D

f2

X

Q

Q

f1

f2

f1

f1f1

f2

f2

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 34

Adaptive Sequencingq Designers include timing margin

– Voltage– Temperature– Process variation– Data dependency– Tool inaccuracies

q Alternative: run faster and check for near failures– Idea introduced as �Razor�

• Increase frequency until at the verge of error• Can reduce cycle time by ~30%

D Q

ERR

fp

fp

DQXERR

X

CMOS VLSI DesignCMOS VLSI Design 4th Ed.11: Sequential Circuits 35

Summaryq Flip-Flops:

– Very easy to use, supported by all toolsq 2-Phase Transparent Latches:

– Lots of skew tolerance and time borrowingq Pulsed Latches:

– Fast, some skew tol & borrow, hold time risk