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Lecture 10: Circuit Families

10: Circuit Families 2CMOS VLSI DesignCMOS VLSI Design 4th Ed.

OutlinePseudo-nMOS LogicDynamic LogicPass Transistor Logic


IntroductionWhat makes a circuit fast?– I = C dV/dt -> tpd ∝ (C/I) ΔV– low capacitance– high current– small swing

Logical effort is proportional to C/IpMOS are the enemy!– High capacitance for a given current

Can we take the pMOS capacitance off the input?Various circuit families try to do this…

BA

11

4

4

Y


Pseudo-nMOSIn the old days, nMOS processes had no pMOS– Instead, use pull-up transistor that is always ON

In CMOS, use a pMOS that is always ON– Ratio issue– Make pMOS about ¼ effective strength of

pulldown network

Vout

Vin

16/2

P/2

Ids

load

0 0.3 0.6 0.9 1.2 1.5 1.80

0.3

0.6

0.9

1.2

1.5

1.8

P = 24

P = 4

P = 14

Vin

Vout


Pseudo-nMOS GatesDesign for unit current on outputto compare with unit inverter.pMOS fights nMOS

Inverter NAND2 NOR2

AY

B

AY

A B

gu =gd =gavg =pu =pd =pavg =

Y



finputs

Y


Pseudo-nMOS GatesDesign for unit current on outputto compare with unit inverter.pMOS fights nMOS

Inverter NAND2 NOR2

4/3

2/3

AY

8/3

8/3

2/3

B

AY

A B 4/34/3

2/3

gu = 4/3gd = 4/9gavg = 8/9pu = 6/3pd = 6/9pavg = 12/9

Y



finputs

Y


Pseudo-nMOS DesignEx: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H

G = 1 * 8/9 = 8/9F = GBH = 8H/9P = 1 + (4+8k)/9 = (8k+13)/9N = 2D = NF1/N + P =

In1

Ink

Y

Pseudo-nMOS1

1 H

4 2 8 133 9

H k ++


Pseudo-nMOS PowerPseudo-nMOS draws power whenever Y = 0– Called static power P = IDDVDD

– A few mA / gate * 1M gates would be a problem– Explains why nMOS went extinct

Use pseudo-nMOS sparingly for wide NORsTurn off pMOS when not in use

A BY

C

en


Ratio ExampleThe chip contains a 32 word x 48 bit ROM– Uses pseudo-nMOS decoder and bitline pullups– On average, one wordline and 24 bitlines are high

Find static power drawn by the ROM – Ion-p = 36 μA

Solution:pull-up pull-up

static pull-up

36 μW

(31 24) 1.98 mWDDP V I

P P

= =

= + =


Dynamic LogicDynamic gates uses a clocked pMOS pullupTwo modes: precharge and evaluate

1

2A Y

4/3

2/3

AY

1

1

AY

φ

Static Pseudo-nMOS Dynamic

φ Precharge Evaluate

Y

Precharge


The FootWhat if pulldown network is ON during precharge?Use series evaluation transistor to prevent fight.

AY

φ

foot

precharge transistor φY

inputs

φY

inputs

footed unfooted

f f


Logical EffortInverter NAND2 NOR2

1

1

AY

2

2

1

B

AY

A B 11

1

gd = 1/3pd = 2/3

gd = 2/3pd = 3/3

gd = 1/3pd = 3/3

Yφ

φ

φ

2

1

AY

3

3

1

B

AY

A B 22

1

gd = 2/3pd = 3/3

gd = 3/3pd = 4/3

gd = 2/3pd = 5/3

Yφ

φ

φ

footed

unfooted

32 2


MonotonicityDynamic gates require monotonically rising inputs during evaluation– 0 -> 0– 0 -> 1– 1 -> 1– But not 1 -> 0


Y

Precharge

A

Output should rise but does not

violates monotonicity during evaluation

A

φ


Monotonicity WoesBut dynamic gates produce monotonically falling outputs during evaluationIllegal for one dynamic gate to drive another!

A X

φ Yφ Precharge Evaluate

X

Precharge

A = 1

Y should rise but cannot

Y

X monotonically falls during evaluation

A X

φ Yφ Precharge Evaluate

X

Precharge

A = 1

Y


Domino GatesFollow dynamic stage with inverting static gate– Dynamic / static pair is called domino gate– Produces monotonic outputs


W

Precharge

X

Y

Z

A

φ

B C

φφ

φ

C

AB

W X Y Z =X

ZH H

A

W

φ

B C

X Y Z

domino AND

dynamicNAND

staticinverter


Domino OptimizationsEach domino gate triggers next one, like a string of dominos toppling overGates evaluate sequentially but precharge in parallelThus evaluation is more critical than prechargeHI-skewed static stages can perform logic

S0

D0

S1

D1

S2

D2

S3

D3

φ

S4

D4

S5

D5

S6

D6

S7

D7

φ

YH


Dual-Rail DominoDomino only performs noninverting functions:– AND, OR but not NAND, NOR, or XOR

Dual-rail domino solves this problem– Takes true and complementary inputs – Produces true and complementary outputs

invalid11‘1’01‘0’10Precharged00Meaningsig_lsig_h

Y_h

f

φ

φ

inputs

Y_l

f


Example: AND/NANDGiven A_h, A_l, B_h, B_lCompute Y_h = AB, Y_l = ABPulldown networks are conduction complements

Y_hφ

φ

Y_lA_h

B_hB_lA_l

= A*B= A*B


Example: XOR/XNORSometimes possible to share transistors

Y_hφ

φ

Y_lA_l

B_h

= A xor B

B_l

A_hA_lA_h= A xnor B


LeakageDynamic node floats high during evaluation– Transistors are leaky (IOFF ≠ 0)– Dynamic value will leak away over time– Formerly miliseconds, now nanoseconds

Use keeper to hold dynamic node– Must be weak enough not to fight evaluation

A

φH

2

2

1 kX Y

weak keeper


Charge SharingDynamic gates suffer from charge sharing

B = 0

AY

φ

x

Cx

CY

A

φ

x

Y

Charge sharing noise

Yx Y DD

x Y

CV V VC C

= =+

A

φ

x

Y


Secondary PrechargeSolution: add secondary precharge transistors– Typically need to precharge every other node

Big load capacitance CY helps as well

B

AY

φ

x

secondaryprechargetransistor


Noise SensitivityDynamic gates are very sensitive to noise– Inputs: VIH ≈ Vtn

– Outputs: floating output susceptible noiseNoise sources– Capacitive crosstalk– Charge sharing– Power supply noise– Feedthrough noise– And more!


PowerDomino gates have high activity factors– Output evaluates and precharges

• If output probability = 0.5, α = 0.5– Output rises and falls on half the cycles

– Clocked transistors have α = 1Leads to very high power consumption


Domino SummaryDomino logic is attractive for high-speed circuits– 1.3 – 2x faster than static CMOS– But many challenges:

• Monotonicity, leakage, charge sharing, noiseWidely used in high-performance microprocessors in 1990s when speed was kingLargely displaced by static CMOS now that power is the limiterStill used in memories for area efficiency


Pass Transistor CircuitsUse pass transistors like switches to do logicInputs drive diffusion terminals as well as gates

CMOS + Transmission Gates:– 2-input multiplexer– Gates should be restoring

A

B

S

S

S

Y

A

B

S

S

S

Y


LEAPLEAn integration with Pass transistorsGet rid of pMOS transistors– Use weak pMOS feedback to pull fully high– Ratio constraint

B

S

SA

YL


CPLComplementary Pass-transistor Logic– Dual-rail form of pass transistor logic– Avoids need for ratioed feedback– Optional cross-coupling for rail-to-rail swing

B

S

S

S

S

A

B

AY

YL

L


Pass Transistor SummaryResearchers investigated pass transistor logic for general purpose applications in the 1990’s– Benefits over static CMOS were small or negative– No longer generally used

However, pass transistors still have a niche in special circuits such as memories where they offer small size and the threshold drops can be managed