How to create a MicroBlaze-based Multi-ProcessorSystem-on-Chip interconnected using a
Network-on-Chip
Yang Zhiyao [email protected]
16 May 2010
1 Introduction
This user guide will detail the steps required to create a Xilinx EDK project incorporatingfour MicroBlazes1 that are interconnected using a Network-on-Chip (NoC). The steps aretested using Xilinx EDK 10.1.03 running on Microsoft Windows XP.
2 Design Tool
The design tool generates NoCs with a mesh topology. Figure 1 shows an example of aNoC generated by the design tool. In this example, there are three rows and three columnsin the mesh array. The inter-router links consists of eight wires in each direction. Therouter addressing scheme is shown in Figure 1. The routers are addressed by their rowcoordinates and column coordinates. This router addressing scheme is used when enteringthe connection requirements (Figure 3).
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Figure 1: Router Addressing
1http://www.xilinx.com/microblaze
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3 Generating Network-on-Chip using Design Tool
Figure 2 shows the files included in the Design Tool folder.
Figure 2: Design Tool Folder
Enter the connection requirements in the file ConnectionRequirements.txt. Figure 3and Figure 4 shows the example we will be using and the corresponding NoC respectively.In this example we only use one wire out of the eight available (i.e., seven wires are leftunused).
Figure 3: Connection Requirements
01 11
00 10
Figure 4: NoC of Connection Requirements Example
Double click “RunDesignTool.bat” to run the Design Tool. A command prompt willappear, requesting for parameters to be used. Figure 5 shows the example we will be using.The number of send channels corresponds to the number of outgoing links from the IPcore to the NoC (Figure 1), similarly for the number of receive channels. The number ofsend and receive channels must be big enough to accommodate the requirements specifiedin ConnectionRequirements.txt else an error will occur. The data width parameter refersto the width of the links inter-connecting the IP core to the network interface. This willdepend on the IP core used and the width of the data that are sent among the IP cores.The number of wires per port refers to the width of the inter-router links. This parameterwill depend on how many unique connections are required as well as the throughputrequired.
If everything goes smoothly, the command prompt will disappear and a new folder“generated” should be created (Figure 6).
Now that we have created the files needed for the NoC, we will now create the XilinxEDK project.
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Figure 5: Entering Parameters
Figure 6: Folder “generated” Created
4 Creating Xilinx EDK Project
In this section, we will go through the steps required to create the Xilinx EDK Project.First, we will use the Base System Builder wizard to generate one MicroBlaze (Section 4.1),we will then create three other MicroBlazes based on what was created (Section 4.2),followed by adding Fast Simplex Links (FSLs) which will be used to connect the MicroBlazesthe to NoC(Section 4.3), we then add the NoC generated by the Design Tool and makethe necessary connections (Section 4.6). The final step would be to add the softwarecomponents for the MicroBlazes (Section 4.9).
4.1 Base System Builder Wizard
Click the “Start” button and navigate to the shortcut to run Xilinx EDK (Figure 7).
Figure 7: Run Xilinx EDK
We will be using the Base System Builder Wizard (Figure 8). Click “OK”.Click “Browse” and specify which folder to use for this project (Figure 9). Click “OK”.
We will be creating a new design (Figure 10). Click “Next”.Choose the board you will be using. Click the “Download Third Party Board Definition
Files” to download the necessary files if the board you are using is not in the list. We will
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Figure 8: Base System Builder
Figure 9: Specifying Project Folder
using the XUPV2P board (Figure 11). If XUPV2P is not in the list, download the necessaryfiles from http://www.xilinx.com/univ/XUPV2P/lib/lib_xupv2p_edk_10_1_sp3.zip.Unzip the file and copy the folder (Xilinx XUP V2P) toC:\Xilinx\10.1\EDK\board\Xilinx\boards. Click “Next”.
Check the MicroBlaze radio button under Processors (Figure 12). Click “Next”.We will use the default settings for the Configure MicroBlaze Processor page (Figure 13).
Click “Next”.Uncheck the Ethernet MAC and SysACE CompactFlash if they are not required. Select
the desired baudrate for the UART. (Figure 14). Click “Next”.We will not be using any of these IOs in the example. Uncheck all of them (Figure 15).
Click “Next”.We will not be adding any peripheral here (Figure 16). Click “Next”.Uncheck the checkboxes for now (Figure 17). Click “Next”.We are finally done with the Base System Builder (Figure 18). Click “Generate”.Click “Finish” (Figure 19) to close the wizard.You should see the following window after the wizard closes (Figure 20).
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Figure 10: Creating new design
Figure 11: Choosing Board
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Figure 12: Specifying Processor
Figure 13: Configure MicroBlaze Processor
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Figure 14: Configure IO Interfaces (1 of 2)
Figure 15: Configure IO Interfaces (2 of 2)
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Figure 16: Add Internal Peripheral
Figure 17: Software Setup
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Figure 18: System Created
Figure 19: Finish
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Figure 20: Finish
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4.2 Create Three Other MicroBlazes
Append “ 0” to indicate that they are for MicroBlaze 0 (Figure 21). First click on theline, wait for a while, then click it again and the box will become editable and you canappend “ 0”.
Figure 21: Append “ 0”
Find the MicroBlaze IP from the IP Catalog (Figure 22). Double-click it to add it toour design. Add three more MicroBlazes for this example. You should see the additions inthe frame on the right (Figure 23).
Figure 22: Add Three MicroBlazes
Figure 23: Add Three MicroBlazes Done
Next we will add six more Local Memory Buses (Figure 24). Double-click to add it toour design.
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Figure 24: Add Six Local Memory Buses
Figure 25: Rename the Six Local Memory Buses
Rename it as follows to associate them with each of the MicroBlazes (Figure 25).Next we will add six more “lmb bram if cntlr” and three more “bram block” (Figure 26).
Figure 26: Add Other IPs
Similarly, we will rename them to associate them with each of the MicroBlazes (Fi-gure 27).
Click on the “+” sign to the left of “microblaze 0” and “microblaze 1” and make thenecessary changes to associate the additional “ilmb” and “dlmb” we added (Figure 28).Do the same for “microblaze 2” and “microblaze 3”.
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Figure 27: Rename Other IPs
Figure 28: Configure MicroBlazes
Click on the “+” sign to the left of “dlmb cntlr 1”, “dlmb cntlr 2” and “dlmb cntlr 3”and make the necessary changes (Figure 29).
Figure 29: Configure dlmb cntlr x
Click on the “+” sign to the left of “ilmb cntlr 1”, “ilmb cntlr 2” and “ilmb cntlr 3”and make the necessary changes (Figure 30).
Click on the “+” sign to the left of “lmb bram 1”, “lmb bram 2” and “lmb bram 3”and make the necessary changes (Figure 31).
Double-click each of the “dlmb x” and “ilmb x” and uncheck the “Active High ExternalReset” option (Figure 32).
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Figure 30: Configure ilmb cntlr x
Figure 31: Configure lmb bram x
Figure 32: Configure “dlmb x” and “ilmb x”
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4.3 Add Fast Simplex Links (FSLs)
Find the Fast Simplex Links (FSLs) from the IP Catalog (Figure 33). Double-click itto add it to our design. We need a total of nine FSLs for this example, eight for datacommunication and one extra one for programming the NoC. You should see the additionsin the frame on the right. Rename them as seen in Figure 34. The naming convention ofthe FSL is “fsl x y z” where x connects to the master side of the FSL, y connects to theslave side of the FSL and z indicates the channel index (useful when we have more thanone channel).
Figure 33: Add Nine FSLs
Figure 34: Rename Nine FSLs
Double-click each of the FSL and uncheck the “External Reset Active High” option(Figure 35).
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Figure 35: Configure Nine FSLs
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4.4 Configure Ports for MicroBlazes, FSLs and LMBs
Click on the “Ports” tab. Then click on the “+” sign to the left of “microblaze 0”, “micro-blaze 1”, “microblaze 2” and “microblaze 3” and make the necessary changes (Figure 36).
Figure 36: Configure Port - MicroBlazes
Click on the “Ports” tab. Then click on the “+” sign to the left of all the fsl and makethe necessary changes for “SYS Rst” and “FSL Clk” (Figure 37).
Figure 37: Configure Port - FSLs
Click on the “Ports” tab. Then click on the “+” sign to the left of all the “dlmb x”and “ilmb x” and make the necessary changes for “SYS Rst” and “LMB Clk” (Figure 38).
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Figure 38: Configure Port - LMBs
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4.5 Configure Address
Click on the “Addresses” tab. Then make the necessary changes for the fields circled inFigure 39.
Figure 39: Configure Address
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4.6 Add NoC generated by Design Tool
Now save the project (Figure 40) and exit.
Figure 40: Save Project
Navigate to the ..\Design Tool\generated\pcores\ folder. You should see a foldersimilar to the one shown in Figure 41. Copy the folder to the pcore folder in the XilinxEDK project folder (Figure 41).
Figure 41: Copy pcore folder
Figure 42: Copy folder to Xilinx EDK project folder
Now open the Xilinx EDK project by double-clicking on “system.xmp” (Figure 43).In the IP Catalog, you should now see an additional entry under “Project Local pcores”
(Figure 44). Double-click it to add it to our design.
4.7 Connecting MicroBlazes, FSLs, and NoC together
This section will cover connecting the MicroBlazes to the FSLs, and the FSLs to the NoC.First we add FSLs to each of the MicroBlazes. microblaze 0 will need two FSLs while therest only need one. microblaze 0 needs an extra one for programming the NoC.
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Figure 43: Open Xilinx EDK project
Figure 44: Additional entry
Go to the “Bus Interfaces” tab and double click on microblaze 0. Click on the rightarrow to the left of the “HDL Toggle” button a few times till the “Buses” tab appear.Click on the “Buses” tab and increase the number of FSLs as appropriate (Figure 45). Dothe same for the other microblaze x.
We now have to configure the connection from the MicroBlazes to the FSLs. Click the“+” to the left of microblaze 0 and make the necessary changes for the FSLs (Circled inFigure 46). MFSL1 in this example is used to program the NoC, MFSL0 is for sendingdata to the NoC and SFSL0 is used to receive data from the NoC. Do the same for theother microblaze x (Figure 47).
We now have to configure the connection from the NoC to the FSLs. Click the“+” to the left of top_2b2_1send_1rcv_0 and make the necessary changes for the FSLs(Figure 48). The naming convention for the FSLs are the first digit is the row coordinates,the second digit is the column coordinates and the third digit is the channel index. So forthe example of MFSL110, M means master so it is the NoC sending to the MicroBlaze,the first and second digits being “11” means that this FSL is connected to the MicroBlazeat (1,1) (ie. microblaze 3) and the third digit being ‘0’ means channel index 0.
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Figure 45: Adding FSLs to MicroBlaze
Figure 46: Connecting FSL for MicroBlazes
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Figure 47: Connecting FSL for MicroBlazes
Figure 48: Connecting FSL for NoC
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4.8 Configure Ports for NoC
Click on the “Ports” tab. Then click on the “+” sign to the left of “top 2by2 1send 1rcv 0”and make the necessary changes for “RST” and “CLK” (Figure 49).
Figure 49: Configure Port - NoC
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4.9 Adding Software Component for MicroBlaze
Click on the “Applications” tab and double-click “Add Software Application Project”(Figure 50).
Figure 50: Applications Tab
Enter the project name. We will use actor0 for microblaze 0, actor1 for microblaze 1,etc.. Make sure the correct processor is selected (Figure 51).
Figure 51: Add Software Application Project
Right-click on the next line and left-click on “Mark to Initialize BRAMs” (Figure 52).Do the same for “Project: actor0”, “Project: actor1”, “Project: actor2” and “Project:actor3”. Note that the icon to the left changes (Figure 53).
Figure 52: Mark to Initialize BRAMs
Let us now add the .c file for actor0. Right-click “Sources” and left-click on “Add NewFile...” (Figure 54). Create a folder for each MicroBlaze. In our example, we create thefolder “actor0” for microblaze 0, folder “actor1” for microblaze 1, etc. Enter a filename forthe .c file and click save (Figure 55). Do the same for the other MicroBlazes (Figure 56).
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Figure 53: Mark to Initialize BRAMs
Figure 54: Add New Source File
Now double-click on a0.c and copy and paste the skeleton code from the “generated”folder (Figure 57).
Now click on “Hardware → Generate Bitstream” (Figure 58). If all goes well, youshould see the following in the output console window (Figure 59).
Now click on the icon (Figure 60) to update the software components. If all goes well,you should see the following in the output console window (Figure 61).
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Figure 55: Add New Source File
Figure 56: Add New Source File
Figure 57: Add Codes for Programming Core
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Figure 58: Generate Bitstream
Figure 59: Generate Bitstream Success
Figure 60: Update Bitstream
Figure 61: Update Bitstream Success
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5 FPGA Demonstration
In this section, we will detail the steps to setup the FPGA development board for ademonstration. The .bit file used can be downloaded from http://www.ics.ele.tue.
nl/~akash/NoCGenTool/MPSoCwithNoC.bit. This .bit file is for the Xilinx UniversityProgram Virtex-II Pro development board (XUPV2P). The Xilinx EDK project files canbe downloaded from http://www.ics.ele.tue.nl/~akash/NoCGenTool/MPSoCwithNoC.
zip.For this example, we will be using RealTerm2 for serial port communication. After
opening RealTerm, go to the ‘Display’ tab and check ‘newLine mode’ (Figure 62).
Figure 62: FPGA Demonstration Screenshot 1
Go to the ‘Port’ tab and set the parameters for the UART (Figure 63).
Figure 63: FPGA Demonstration Screenshot 2
Now go to Xilinx EDK software to download the .bit file to the FPGA (Figure 64).
2http://realterm.sourceforge.net/
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Figure 64: FPGA Demonstration Screenshot 3
If all goes well, you should see the Main Menu in the window in RealTerm (Figure 65).
Figure 65: FPGA Demonstration Screenshot 4
In this FPGA demonstration, there are four configurations to choose from (Figure 66).See the .c codes for each MicroBlaze in the Xilinx EDK software for more details.
In Figure 67, configuration 4 is loaded. Figure 68 shows the output when we send“1111”.
Do play around by sending different data and see the output and also to load differentconfigurations and see how the output changes.
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Figure 66: FPGA Demonstration Screenshot 5
Figure 67: FPGA Demonstration Screenshot 6
Figure 68: FPGA Demonstration Screenshot 7
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