Transcript
Page 1: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Introduction to Digital Signal Processing Systems

Lan-Da Van (范倫達), Ph. D.

Department of Computer Science

National Chiao Tung University Taiwan, R.O.C.

Fall, 2015

[email protected]

http://www.cs.nctu.edu.tw/~ldvan/

Page 2: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-2

Outlines

Introduction

DSP Algorithms

DSP Applications and CMOS IC’s

Representations of DSP Algorithms

Conclusion

References

Page 3: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-3

Why Use Digital Signal Processing?

Robust to temperature and process variations

Controlled better to accuracy

Noise/interference tolerances

Mathematical representation

Programming capability

Page 4: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-4

Common System Configuration

Multimedia-Communication-Biomedical

Applications

VLSI Signal Processing Library Processor Software

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-5

VLSI Signal Processing System Design Spectrum (1/2)

Computer arithmetic

Adder

Multiplier

Inverse square root

Division

Digital filter

Multidimensional filter

Symmetry filter

Adaptive digital filter

LMS/DLMS (Delay LMS) based

RLS based

Transform

Multiplier-accumulator based

Recursive-filter based

ROM-based: DA, CORDIC

Butterfly based

Processor

General purposed processor

DSP processor

Reconfigurable computing

processor

3D Graphics

Geometry transformation

Rasterization/Rendering

Z-buffer compression

Texture compression

Ear-Aid System

Adaptive algorithm

Filter bank

System Security

Page 6: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-6

VLSI Signal Processing System Design Spectrum (2/2)

MIMO Detection

Grouped Detection

VBLAST

K-Best

Biomedical Computation

Machine Learning

ICA

PCA

HRV

ADC

SAR ADC

Pipeline ADC

Sigma-Delta

PLL

Image Processing

Pattern Recognition

Median Filter

Image Reconstruction

Image Projection

Video Processing

Compression

Block Matching

Deblocking filter

Non-numerical operation

Error control coding

Viterbi Decoder

Turbo Code

Polynomial computation

Dynamic programmable

Page 7: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-7

VLSI Signal Processing System Publication Area (But not limited…)

IEEE Trans. on Biomedical Engineering

IEEE Trans. on Circuits and Systems I: Regular Papers

IEEE Trans. on Circuits and Systems II: Express Briefs

IEEE Trans. on Circuits and Systems for Video Technology

IEEE Trans. on Communications

IEEE Trans. on Computer-Aided Design of Integrated Circuits

IEEE Trans. on Computers

IEEE Trans. on Image Processing

IEEE Trans. on Information Theory

IEEE Trans. on Multimedia

IEEE Trans. on Neural Networks

IEEE Journal on Selected Areas in Communications

IEEE Trans. on Signal Processing

IEEE Journal of Solid-State Circuits

IEEE Trans. on VLSI Systems

IEEE Trans. on Visualization and Computer Graphics

Proceedings of the IEEE

ACM Trans. on Graphics

Journal of Signal Processing Systems

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Elsevier Integration - The VLSI Journal

Page 8: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-8

VLSI Signal Processing System Design Space

System Level

Algorithm Level

Architecture Level

Circuit Level

Logic Level

Process Level

Power

Area

PerformanceCost

Test

Page 9: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-9

Outlines

Features:

DSP Algorithms

DSP Applications and CMOS IC’s

Representations of DSP Algorithms

Page 10: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-10

DSP Algorithms

Convolution

Correlation

Digital filters

Adaptive filters

Discrete Fourier transform

Source Coding Algorithms Discrete cosine transform

Motion estimation

Huffman coding

Vector quantization

Decimator and expander

Wavelet and filter banks

Viterbi algorithm and dynamic programming

Algorithm: A set of rules for solving a problem in a finite number of steps.

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-11

Signals

Analog signal

t->y: y=f(t), y:C, t:C

Discrete-time signal

n->y: y=f(nT), y:C, n:Z

Digital signal

n->y: y=D{f(nT)}, y:Z,n:Z

)3(

)1(

)2(

)1(

2)1110(

2)1000(2)1011(

2)1000(

t n n

y y y

Analog Signal Discrete-Time Signal Digital Signal

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-12

LTI Systems

Linear systems

Assume x1(n)->y1(n) and x2(n)->y2(n), where “->” denotes

“lead to”. If ax1(n)+bx2(n)->ay1(n)+by2(n), then the systems is

referred to as “Linear System.”

Homogenous and additive properties

Time-invariant (TI) systems

x(n-n0)->y(n-n0)

LTI systems

y(n)=h(n)*x(n)

Causal systems

y(n0) depends only on x(n), where n<=n0

Stable systems

BIBO

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Sampling of Analog Signals

Nyquist sampling theorem

The analog signal must be band-limited

Sample rate must be larger than twice the bandwidth

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-14

System-Equation Representation

Impulse/unit sample response

Transfer function / frequency response

Difference equations

State equations

11

0

1)(

)()(

za

b

zX

zYzH

)()1()( 01 nxbnyany

][)( 10 nuabnh n

Page 15: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

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Lan-Da Van VLSI-DSP-1-15

Convolution & Correlation

Convolution

k

knhkxnhnxny )()()()()(

)()()()( nxnaknxka

k

k

knxkany )()()(

Correlation

)()( knxkhk

Page 16: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

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Linear Phase FIR Digital Filters

Digital filters are an important

class of LTI systems.

Linear phase FIR filter

)()( nMhnh

0)6()0( bhh

1)5()1( bhh

2)4()2( bhh

3)3( bh

)4()5()6(

)3()2()1()()(

210

3210

nxbnxbnxb

nxbnxbnxbnxbny

Page 17: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

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IIR Filter Structures

1z

2a

1a

1z

0b

1b

2b

)(nx )(ny

2

2

1

1

2

2

1

10

1)(

zaza

zbzbbzH

Page 18: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

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Introduction to an Adaptive Algorithm

Widely used in communications, DSP, biomedical,

and control system

Deterministic gradient / least square algorithm

Steepest descent algorithm

RLS algorithm

Stochastic gradient algorithm

LMS algorithm, DLMS algorithm

Block LMS algorithm

Gradient Lattice algorithm

Page 19: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

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Adaptive Applications

Channel equalizer

System identification

Echo canceller

Noise cancellation

Predictor

Line enhancement

Beamformer

Image enhancement

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Notation

)Error: e(n

Factor: μAdaptation

tor: W(n)Weight Vec

tput: d(n)Desired Ou

al: X(n)Input Sign

.5

.4

.3

.2

.1

: .10

.9

.8

.7

.6

MatrixDiagonal

:λEigenvalue

ix: Ration MatrAutocorrel

: NTap Number

ent: MMisadjustm adj

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Steepest Descent Algorithm

)()()( nXnWny T

TNnxnxnxnXwhere )]1( ... )1( )([)(

TN nwnwnwnW )]( ... )( )([)( 110

)()()(

)()()(

)()()(

nWnXnd

nXnWnd

nyndne

T

T

The error at the n-th time is

Page 22: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

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LMS Algorithm

))(ˆ(2

1)()1( nJnWnW

)()(2)(ˆ nXnenJ

μe(n)X(n)W(n))W(n 1

w0’, w1, w0

An efficient implementation in software of steepest

descent using measured or estimated gradients

The gradient of the square of a single error sample

Cost

Page 23: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

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)()()( nyndne

Summary of LMS Adaptive Algorithm (1960)

)()()( nnny T xw

)()( )()1( nnenn xww

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Block Diagram of an Adaptive FIR Filter Driven by the LMS Algorithm

1z)(nx 1z 1z

)(0 nw )(2 nw)(1 nw )(1 nwN

)1( nx )2( nx )1( Nnx

)(nd)(ny

)(ne

Page 25: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

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Unitary/Orthogonal Transform (1/4)

Definition: (from Linear Algebra)

Let A be nn matrix that satisfies

IAAAA .

We call A as an unitary matrix if A

has complex entries, and we call A as

an orthogonal matrix if A has real

number.

Page 26: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

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Why Orthogonal Transformation? (2/4)

Energy conservation

Energy compaction

Most unitary transforms tend to pack a large fraction of the

average energy of signals into a relatively few components

of the transform coefficients.

Decorrelation

When signals are highly correlated, the transform

coefficients tend to be uncorrected (or less correlated).

Information preservation

The information carried by signals are preserved under a

unitary transform.

Page 27: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

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Why Orthogonal Transformation? (3/4)

0 100 200 300 400 500 60050

100

150

200

250The original signal

0 100 200 300 400 500 600-2000

0

2000

4000The DCT coefficients

Source: Lecture of Prof. Dennis Deng

Page 28: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

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Why Orthogonal Transformation? (4/4)

0 5 10 15 20 25

0.98

1

The auto correlation of original signal

0 5 10 15 20 25-0.5

0

0.5

1The auto correlation of DCT coefficients

Source: Lecture of Prof. Dennis Deng

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VLSI Digital Signal Processing Systems

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Discrete Fourier Transform (1/9)

DFT

IDFT

1,...,1,0,)()(1

0

NnWnxkXN

n

nk

N

1,...,1,0,)(1

)(

1

0

NnWkXN

nx

N

k

nkN

nkN

jnkN

Nj

N eWeW

22

,

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Fast Fourier Transform (2/9)

The radix-2 algorithm is the most widely used fast

algorithm to compute the DFT.

Without loss of generality, we use an 8-point DFT (N=8)

to illustrate the development of the fast algorithm.

))7()5()3()1((

)6()4()2()0(

)7()5()3()1(

)6()4()2()0(

)()(

642

642

753

642

7

0

kN

kN

kN

kN

kN

kN

kN

kN

kN

kN

kN

kN

kN

kN

knN

n

WxWxWxxW

WxWxWxx

WxWxWxWx

WxWxWxx

WnxkX

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Fast Fourier Transform (3/9)

Since

8-point DFT => Nearly two 4-point DFT

where represent the DFT of two sequences

kN

kN

jkN

jk

N WeeW 2/)2/(

22

2

2

1,...2,1,0 where),()(

))7()5()3()1((

)6()4()2()0()(

21

32/

22/2/

32/

22/2/

NkkFWkF

WxWxWxxW

WxWxWxxkX

kN

kN

kN

kN

kN

kN

kN

kN

)()( 21 kFandkF

)12()()2()( 21 nxnfandnxnf

Page 32: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

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Fast Fourier Transform (4/9)

One step further: (=>Two 4-point DFT)

An N-point DFT requires N2 complex multiplications. The

number of complex multiplications required by the above

algorithm is as follows.

An 8-point DFT requires 64 complex multiplications.

12/,...,1,0 ),()()( 21 NkkFWkFkX kN

12/,...,1,0 ),()()2/( 21 NkkFWkFNkX kN

kN

jk

NjNk

Nj

NkN WeeeW

2)2/(

2

2/

)8( 40)2/(2 2 NNN

kN

NkN WW 2/

2/2/ and

Page 33: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

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Fast Fourier Transform (5/9)

The 4-point DFT can be decomposed into two 2-point

DFT in a similar way.

where V11(k) and V12(k) represent the DFT of two

sequences.

As before,

)()(

))6()2(()4()0(

)6()2()4()0()(

122/11

4/2/4/

32/2/

22/1

kVWkV

WxxWWxx

WxWxWxxkF

kN

kN

kN

kN

kN

kN

kN

)12()( )2()( 112111 nfnvandnfnv

14/,...,1,0),()()( 122/111 NkkVWkVkF kN

14/,...,1,0),()()2/( 122/111 NkkVWkVNkF kN

Page 34: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

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Fast Fourier Transform (6/9)

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Fast Fourier Transform (7/9)

A 2-point FFT, such as involves only

real addition

)()( 1211 kVandkV

1,1),4()0()( 12

0211 2

WWxWxkV k

V x W x

V x W x

N

N

110

110

0 0 4

1 0 4

( ) ( ) ( )

( ) ( ) ( )

a

b

A

B-1

WN

Each butterfly requires one complex multiplication and two complex addition

Page 36: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

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Fast Fourier Transform (8/9)

After decimation, the sequence is in a bit-reversed

order

original order decimation1 decimation 2

n2n1n0 n0n2n1 n0n1n2

0 000 0 000 0 000

1 001 2 010 4 100

2 010 4 100 2 010

3 011 6 110 6 110

4 100 1 001 1 001

5 101 3 011 5 101

6 110 5 101 3 011

7 111 7 111 7 111

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Fast Fourier Transform (9/9)

This FFT algorithm is generally true for any data

sequence of

There are N/2 butterflies per stage and

stages

The number of operations required for an FFT:

(Before simplifying)

Complex multiplication:

Complex addition:

vN 2

NN 2log

NN 2log

N2log

Page 38: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

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Image/Video Compression

Where coding? Source coding

Channel coding

Source coding benefits Lower bit rate

Less transmission time

Fewer storage data

What kind of loss? Lossless data compression

Lossy data compression

Why can we do compression? Coding redundancy

Inter-sample redundancy (Spatial redundancy)

Inter-frame redundancy (Temporal redundancy)

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Source Coding Spectrum

Image Compression

Lossless Loss

Huffman Coding

Shannon Coding

ArithmeticCoding

Predictive Coding

Transform Coding

VQ Coding

Subband Coding

Page 40: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

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Image Measurement and Evaluation

)/(log10SNR(dB) 2210 nx

)/255(log10PSNR(dB) 2210 n

ly.respective valules,image tedreconstruc and

image orignal thedenote ˆ and where (i,j)xx(i,j)

2

1 1

2]),(),([

1

N

i

N

j

n jixjixN

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Discrete Cosine Transform (DCTII)

10 , ]2

)12(cos[)()()(

1

0

N-kN

knnxkkX

N

n

N

1)0( 1 1for ,

2 )( Nk

Nk

Page 42: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

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2-D DCT-II and IDCT-II

)2

)12(cos()

2

)12(cos(),()()(

2),(

1

0

1

0N

ln

N

kmlkZlk

Nnmx

N

k

N

l

)2

)12(cos()

2

)12(cos(),()()(

2),(

1

0

1

0N

ln

N

kmnmxlk

NlkZ

N

m

N

n

DCT-II

IDCT-II

.0for 1 and 210

and 1 to0 from ranges and , where

jα(j)/)α(

N-nk, l, m

TAXAZ

ZAAX T

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-43

How to Decide the Coefficients?

Orthogonal Property

IAAAA TT Parseval’s Theorem: Energy Conservation

1

0

21

0

2)(

1)(

N

k

N

n

kXN

nx

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-44

2-D DCT/IDCT Processor

1D DCT/

IDCT

Unit

Transpose

Memory

1D DCT/

IDCT

UnitX

YZ

Transpose

Memory

1D DCT/

IDCT

Unit

DMUX

1:2

MUX

2:1X

Z

Y

(a)

(b)

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-45

Block-Matching Algorithm

1

0

1

0

),(),(),(N

i

N

j

njmiyjixnms pnmpfor ,

)},({min ),( nmsu nm pnmpfor ,

unmv ),(

Rule:

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-46

Huffman Coding (1/3)

Entropy Information Measurement

Uncertainty Measurement

Surprise Measurement

bits coding

bits uncodingCr

q

i

ii ppP

1

2 )/1(log)H(

Compression Ratio

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-47

Huffman Coding (2/3)

1x

2x

6x

5x

4x

3x

8x

7x

Input Probability

2

1

1

64

1

16

1

8

1

4

1

64

1

64

1

64

1 0

1

0

1

0

1

0

1

0

1

0

1

0

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-48

Huffman Coding (3/3)

Data Huffman Code Natural Code

1x 1 000

2x 01 001

3x 001 010

4x 0001 011

5x 000001 100

6x 000000 101

7x 000011 110

8x 000010 111

bit 2(4x6)64

1x4

16

1x3

8

1x2

4

1x1

2

1

AvLen deHuffman_Co

bit 3AvLen deNatural_Co

bit 264)(4xlog64

116log

16

18log

8

14log

4

12log

2

1

)(

22222

EntropyxH

bits coding

bits uncodingCr

5.12

3

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-49

Vector Quantization

1

0

22)(),(

k

i

ii yxyxyxd

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-50

Outlines

Features:

DSP Algorithms

DSP Applications and CMOS IC’s

Representations of DSP Algorithms

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-51

Moore’s Law

Microns

Source: Sematech

Tr. # (Complexity) Tr. # (Productivity)

10

1

0.01

0.1

10G

100M

10M

1M

100K

10K

1K

1G

1980 1985 1990 20001995 20102005

10

100M

10M

1M

100K

10K

1K

100x

xx

xx x

x

x

Gate Length

Device Complexity

Design Productivity

21%/ year

58% / year

Gap

Increases

The number of transistors per chip doubles every 18 months.

* Cordon Moore: One of the founders of Intel

Page 52: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-52

Common DSP Algorithms and Their Applications

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-53

Evolution of Applications

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-54

Chronological Table of Video Coding Standards

H.261

(1990)

MPEG-1

(1993)

H.263

(1995/96) H.263+

(1997/98)

H.263++

(2000)

H.264

( MPEG-4

Part 10 )

(2002) MPEG-4 v1

(1998/99)

MPEG-4 v2

(1999/00)

MPEG-4 v3

(2001)

1990 1992 1994 1996 1998 2000 2002 2003

MPEG-2

(H.262)

(1994/95) ISO/IEC

MPEG

ITU-T VCEG

Page 55: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Source: http://www.hd.club.tw/thread-153165-1-1.html

Chronological Table of Video Coding Standards

Page 56: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-56

Position of H.264

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-57

Comparison of Video Standards

Source: http://140.117.156.238/%E5%A4%9A%E5%AA%92%E9%AB%94%E6%A6%82%E8%AB%96_1.pdf

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-58

Block Diagram of H.264/AVC Encoder

Entropy

Coding

Scaling & Inv.

Transform

Motion-

Compensation

Control

Data

Quant.

Transf. coeffs

Motion

Data

Intra/Inter

Coder

Control

Decoder

Motion

Estimation

Transform/

Scal./Quant. -

Input

Video

Signal

Split into

Macroblocks

16x16 pixels

Intra-frame

Prediction

De-blocking

Filter

Output

Video

Signal

Page 59: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-59

New Features of H.264

Multi-mode, multi-reference MC

Motion vector can point out of image border

1/4-, 1/8-pixel motion vector precision

B-frame prediction weighting

44 integer transform

Multi-mode intra-prediction

In-loop de-blocking filter

UVLC (Uniform Variable Length Coding)

NAL (Network Abstraction Layer)

SP-slices

Page 60: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-60

3D Graphics System

Geometry Engine

Raster Engine

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-61

Shading Algorithms (1/2)

Gouraud shading

Per-vertex lighting

Low computation

Not good shading quality

Phong shading

Per-pixel lighting

Huge computation

Smooth and more realistic highlight

Page 62: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-62

Shading Algorithms (2/2)

Existing Approximate Phong Shading Algorithms

Taylor expansion based approximate algorithms

Spherical interpolation based approximate algorithms

Quadratic interpolation based approximate algorithms

Mixed shading

Subdivision based approximate algorithms

2015/9/18 62

A B

NA NB

N(t)

Spherical interpolation Quadratic interpolation Mixed shading Subdivision

No pass

Pass

Source: ACM/IEEE

Page 63: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Four Area Networks

From small to big: Personal area network

Local area network

Metro area network

Wide area network

Corresponding IEEE standard in each area network

資料來源:無線都會網路新貴 WiMAX標準介紹,

http://tech.digitimes.com.tw/ShowNews.aspx?zCatId=134&zNotesDocId=E88A9E150386245D48256F5B00128CAC Lan-Da Van VLSI-DSP-1-63

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VLSI Digital Signal Processing Systems

Source: UMTS Forum

WAN

LAN

PAN

Low data rate High data rate

Lo

w M

ob

ility

H

igh M

obili

ty

GSM/GPRS

802.11a/g

ZigBee 802.15.4

Bluetooth 802.15.1

WiMedia 802.15.3a

WiMAX 802.16d

MAN

10 Mbps 0.1 Mbps 100 Mbps

WCDMA

RFID

802.11n

1 Mbps 1000 Mbps

802.11b

HSPA 3GPP LTE

WiMAX 802.16e

WiMAX 802.16m

Lan-Da Van VLSI-DSP-1-64

Communication Standards Evolution (1/4)

Page 65: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Communication Standards Evolution (2/4)

Lan-Da Van VLSI-DSP-1-65

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VLSI Digital Signal Processing Systems

Communication Standards Evolution (3/4)

Lan-Da Van VLSI-DSP-1-66

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VLSI Digital Signal Processing Systems

Communication Standards Evolution (4/4)

Lan-Da Van VLSI-DSP-1-67

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-68

Comparisons of Various Cellular Standards

行動通信技術發展(資料來源: Agilent Technologies)

Page 69: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Comparison of LTE and WiMax

Lan-Da Van VLSI-DSP-1-69

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VLSI Digital Signal Processing Systems

HSDPA WiMAX / 802.16e

Architecture

Licensed

Circuit switched, evolved to

packet on data downlink

Spectrum

Packet Oriented

Licensed/Unlicensed

Frequency Bands Below 2.7 GHz 2-11 GHz

Channel Conditions NLOS NLOS

Bandwidth 5 MHz 1.75 to 20 MHz

Symmetric/Asymmetric Asymmetric Symmetric

Moving Speed Allowed Mobile (up to 250 km/h) Portable (up to 100 km/h)

Multiple Access TDMA+CDMA FDMA+TDMA

ModulationCDMA with SF=16

QPSK, 16QAM

OFDMA with 128 to 2048 FFT

QPSK, 16QAM, 64QAM

Channel Coding Turbo code Convolutional code

Bit Rate Up to 14.4 Mbps in 5 MHz Up to 15 Mbps in 5 MHz

Roaming Local / regionalGlobal

Source: Chunghwa Telcom Co. Ltd. Lan-Da Van VLSI-DSP-1-70

Comparison of HSDPA and WiMax

Page 71: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

http://t17.techbang.com/topics/20299-d-link-11-ac-cloud-of-the-worlds-fastest-route-to-experience-carry-out-d-will-overlord-netcom-equipment-d-link-corp?mode=print&page=1

Comparison of 802.xx

Page 72: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-72

Error Control

Decoder

Digital Communications System

Enabling the transmitted signal to withstand the effects of

various channel impairments, such as noise, interference,

and fading.

Information

Source Source

Encoder Encrypter

Error Control

Encoder Modulator

Channel

Demodula

tor Information

Sink Decrypter

Source

Decoder

Page 73: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-73

Multiple Access Techniques

Source: IEEE Spectrum

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-74

ODFM System

Source: Prof. Wen, NCCU.

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-75

Outlines

Features:

DSP Algorithms

DSP Applications and CMOS IC’s

Representations of DSP Algorithms

Block Diagrams

Signal-Flow Graph

Data-Flow Graph

Dependence Graph

Page 76: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-76

DG of a 3-Tap FIR Filter

Def: A dependence graph is

a direct graph that shows

the dependence of the

computations in an

algorithm. The node in a

DG represent computations

and the edges represent

precedence constraints

among nodes. DG contains

computations for all

iterations in an algorithm

and does not contain delay

elements.

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-77

DFG of a 3-Tap FIR Filter

Def: A data flow graph

(DFG) is a collection of

nodes and directed edges.

The nodes represent

computations (or functions

or subtasks) and the

directed edges represent

data path and each edge

has a nonnegative number

of delays associated with it.

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VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-78

SFG of a 3-Tap FIR Filter

Def: A signal flow graph

(SGF) is a collection of

nodes and directed edges.

The nodes represent

computations or tasks. In

digital networks, the

edges are usually

restricted to constant gain

multipliers or delay

elements.

Page 79: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-79

Block Diagram of a 3-Tap FIR Filter

Def: A block

diagram consists of

functional blocks

connected with

directed edges.

Page 80: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-80

Conclusions

Briefly introduced the following:

DSP design issue and design view

DSP algorithms

Overview of DSP applications

Representations of DSP algorithms

Page 81: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2015_Fall/VLSIDSP_CHAP1.pdf · VLSI Digital Signal Processing Systems Lan-Da Van VLSI-DSP-1-7 VLSI Signal Processing

VLSI Digital Signal Processing Systems

Lan-Da Van VLSI-DSP-1-81

References

[1] K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. NY: Wiley, 1999. [2] P. Pirsch, Architectures for Digital Signal Processing. NY: Wiley, 1998. [3] A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1989. [4] S. Haykin, Adaptive Filter Theory, 3rd ed. Englewood Cliffs, NJ: Prentice-Hall, 1996. [5] 連國珍,數位影像處理, 1992.


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