6: ADC

ARCHITECTURES

6: ADC

ARCHITECTURES

There are mainly four types of ADC architectures:

Flash-type,

Pipeline,

Successive approximation,

Oversampled ADCs.

There are mainly four types of ADC architectures:

Flash-type,

Pipeline,

Successive approximation,

Oversampled ADCs.

The ADC has a continuous, infinite-valued signal as its

input. The input transitions determine the amount of

INL and DNL associated with the converter.

Flash-type

Figure : Block diagram of a Flash ADC

Flash or parallel converters have the highest speed of any

type of ADC. As shown in Fig., they utilize one comparator

per quantization level (2N - 1) and 2N resistors (a resistor

string DAC). The reference voltage is divided into 2N

values, each of which is fed into a comparator. The input

voltage is compared with each reference value and results

in a thermometer code at the output of the comparators. A

thermometer code will exhibit all zeros for each resistor

level if the value of VIN is less than the value on the

resistor string, and ones if VIN is greater than or equal to

voltage on the resistor string.

Flash or parallel converters have the highest speed of any

type of ADC. As shown in Fig., they utilize one comparator

per quantization level (2N - 1) and 2N resistors (a resistor

string DAC). The reference voltage is divided into 2N

values, each of which is fed into a comparator. The input

voltage is compared with each reference value and results

in a thermometer code at the output of the comparators. A

thermometer code will exhibit all zeros for each resistor

level if the value of VIN is less than the value on the

resistor string, and ones if VIN is greater than or equal to

voltage on the resistor string.

A simple 2N-1, N digital thermometer decoder circuit

converts the compared data into an N-bit digital word.

The obvious advantage of this converter is the speed

with which one conversion can take place. Each clock

pulse generates an output digital word.

The disadvantage of this is doubling of area with each

bit of increased resolution.

For example, an 8-bit converter requires 255

comparators, but a 9-bit ADC requires 511. Flash

converters have traditionally been limited to 8-bit

resolution

A simple 2N-1, N digital thermometer decoder circuit

converts the compared data into an N-bit digital word.

The obvious advantage of this converter is the speed

with which one conversion can take place. Each clock

pulse generates an output digital word.

The disadvantage of this is doubling of area with each

bit of increased resolution.

For example, an 8-bit converter requires 255

comparators, but a 9-bit ADC requires 511. Flash

converters have traditionally been limited to 8-bit

resolution

Another disadvantages of the Flash ADC are the power

requirements of the 2N-1 comparators. The speed is

limited by the switching of the comparators and the

digital logic.

Problem: Design a 3-bit Flash converter, listing the values

of the voltages at each resistor tap, and draw the transfer

curve for VIN = 0 to 5 V. Assume VREF = 5 V. Construct a

table listing the values of the thermometer code and the

output of the decoder for VIN =1.5, 3.0, and 4.5 V.

Problem: Design a 3-bit Flash converter, listing the values

of the voltages at each resistor tap, and draw the transfer

curve for VIN = 0 to 5 V. Assume VREF = 5 V. Construct a

table listing the values of the thermometer code and the

output of the decoder for VIN =1.5, 3.0, and 4.5 V.

Accuracy Issues for the Flash ADC

Accuracy is dependent on the matching of the resistor

string and the input offset voltage of the comparators.

The voltage on the i-th tap of the resistor string was found

to be

where VI ideal is the voltage at the i-th tap if all the resistors

had an ideal value of R. The term, ΔRk is the value of the

resistance error (difference from ideal) due to the

mismatch.

The switching point for the i-th comparator, Vsw,i thenbecomes

where Vos,i, is the input referred offset voltage of the i-th

comparator. The INL for the converter can then be

described as

The worst-case INL will be assumed to be occur at the

middle of the string

where it is assumed that the maximum positive mismatch

occurs in all the resistors in the lower half of the string

and the maximum negative mismatch occurs in the upper

half (or vice versa) and that the comparator at the i-th tap

contains the maximum offset voltage, |Vos,i|max,

where it is assumed that the maximum positive mismatch

occurs in all the resistors in the lower half of the string

and the maximum negative mismatch occurs in the upper

half (or vice versa) and that the comparator at the i-th tap

contains the maximum offset voltage, |Vos,i|max,

Problem: If a 10-bit Flash converter is designed,

determine the maximum offset voltage of the comparators

which will make the INL less than 1/2 LSB. Assume that

the resistor string is perfectly matched and VREF = 5 V.

The offset voltage be equal to 1/2 LSB.(i.e. ½ * Vref/2N) ThereforeThe offset voltage be equal to 1/2 LSB.(i.e. ½ * Vref/2N) Therefore

The DNL calculation for the Flash converter is

calculated Using the definition of DNL,

The maximum DNL will occur assuming ΔRi is at its

maximum, Vos,I is at its maximum positive value, and Vos,i-1is at its maximum negative voltage. Thus,

The maximum DNL will occur assuming ΔRi is at its

maximum, Vos,I is at its maximum positive value, and Vos,i-1is at its maximum negative voltage. Thus,

The Two-Step Flash ADC