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Spartan-3A Evaluation Kit Tutorial

Creating Your First MicroBlaze Design with the Spartan-3A Evaluation Kit

Version 10.1.03


Revision History

Version Description Date 10.1.00 Initial draft release June 8, 2008 10.1.01 Fixed memory requirements for 3S400A design; fixed font to

Arial-10 June 18, 2008

10.1.02 Update to ISE Design Suite 10.1 Service Pack 2. Added block diagram

July 9, 2008

10.1.03 Added location for board forum Sept 5, 2008

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Overview The Xilinx Platform Studio (XPS) includes a wizard to design an embedded processor system. The Base System Builder (BSB) wizard is a software tool that helps users quickly build a working embedded processor system targeted at a specific development board. Based on the user’s board selection, BSB offers the user a number of options for creating a basic system on that board. These options include processor type, debug interface, cache configuration, memory type and size, and peripheral selection. For each option, functional default values are pre-selected in the GUI. Upon exiting BSB, a hardware specification (MHS) file is created and loaded into the user’s XPS project. The user may then further enhance the design in XPS or continue on to implement the design using the Xilinx implementation tools. The Base System Builder also generates sample applications and linker scripts which can be compiled and run with the hardware on the target development board. The Xilinx Board Description (XBD) file defines the features and standard peripherals that are available on a particular hardware platform. The XBD file is used by BSB to determine which hardware options are available to a user for a particular board. This tutorial shows how to make use of XPS, BSB, and an XBD file to create and use a MicroBlaze soft processor system for the Avnet Spartan-3A Evaluation Kit.

Objectives This tutorial will demonstrate how to do the following:

• Install a 3rd-party Xilinx Board Description (XBD) file • Use an IP repository • Define and build a MicroBlaze system using Base System Builder • Run software applications on the MicroBlaze system • Embed the example hardware and software in on-board flash for instant-on operation

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Requirements The following items are required for proper completion of this tutorial.

Software

The following software setup was used to test this reference design: • WindowsXP 32-bit Service Pack 2 • Xilinx ISE software, version 10.1 with Service Pack 21 • Xilinx EDK software, version 10.1 with Service Pack 2 • Avnet Programming Utility (AvProg) v3.3.7

Hardware

The hardware setup used by this reference design includes: • Computer with a minimum of 330-540 MB (depending on O/S) to complete an XC3S400A

design2 • Avnet Spartan-3A Evaluation Kit

o Avnet Spartan-3A Evaluation board o USB cable

Setup

• Install ISE and EDK software. Apply service packs. • Install AvProg software and Sp3A Eval driver

Recommended Reading

• The hardware used on the Spartan-3A Evaluation board is described in detail in Avnet document Spartan-3A Evaluation Kit User’s Guide.

• For more detailed information about Base System Builder, please refer to the Xilinx document titled Embedded System Tools Reference Manual (est_rm.pdf).

• For details on XBD syntax, please see the chapter on XBD Format in the Xilinx document titled Platform Specification Format Reference Manual (psf_rm.pdf).

• Details on the Spartan-3A FPGA family are included in the following Xilinx documents: o Spartan-3A FPGA Family: Data Sheet (DS529) o Spartan-3 Generation FPGA User Guide (UG331) o Spartan-3 Generation Configuration User Guide (UG332)

1 ISE latest Service Pack is available at www.xilinx.com/download 2 Refer to www.xilinx.com/ise/products/memory.htm

http://www.xilinx.com/download

http://www.xilinx.com/ise/products/memory.htm


Getting Started with MicroBlaze Install the XBD file

This section will describe how to install the XBD files so that they are visible to BSB. XBD files are unzipped to a repository. The user can choose one of three different repositories to install the XBD files, as described below.

• EDK Installed Repository This repository is located at <XILINX_EDK>\board. This repository is installed as part of EDK. It is the location for Xilinx XBD files and can be used for 3rd-party boards as well.

Figure 1 – EDK 10.1 XILINX_EDK default repository

• Global Peripheral Repository This is a fixed user peripheral repository for all XPS projects, similar to the EDK-installed repository. One such repository is the <XILINX_EDK>\..\edk_user_repository. However, in 10.1, this repository is deprecated. If used, the following warning is issued:

WARNING:MDT - Use of repository located at c:\xilinx\10.1\edk_user_repository\ (equivalent of $XILINX_EDK/../edk_user_repository) is now deprecated. It is recommended that you use Global Search Path preference to specify search paths that apply to all the projects

The preferred method for setting this repository is to set it in Edit Preferences, Application Preferences, as shown below. Note that XPS must be closed and re-opened for this setting to take affect.

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Figure 2 – Setting the Global Peripheral Repository

• Local Peripheral Repository

This repository is only effective for the current project. It is selected as part of the project properties.

The steps to install the XBD files for use in a Local User Repository are shown below.

1. Download the Avnet XBD archive at www.em.avnet.com/xbd 2. Choose the directory to which you will install the XBD files. In this tutorial, the Local

Peripheral Repository is located at C:\Avnet_Repository. Create that directory now. 3. Open and extract the XBD zip archive to the repository chosen in the previous step. 4. Verify that the directory structure in the peripheral repository is as follows:

<repository_folder> Avnet Memec boards <board_name> data <xbd_file>

This repository folder with several Avnet and Memec boards’ XBD files extracted is shown in Figure 3 (based on avnet_edk10_1_xbd_files_080630.zip).

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http://www.em.avnet.com/xbd


Figure 3 – Avnet XBD File Repository

Create the hardware/software platform

After installing the XBD files, Xilinx Platform Studio’s Base System Builder (BSB) wizard is used to generate a new project for this specific board. BSB accomplishes many things, including:

• Generate the hardware platform o Processor and peripheral instantiations o Clock generation o FPGA pinout o ISE Scripts to build the hardware

• Generate the software platform o Libraries o Drivers o Processor common code blocks o Make files

• Generate example test applications o C code o Linker script

5. Launch Xilinx Platform Studio (XPS) by selecting Start All Programs Xilinx ISE

Design Suite 10.1 EDK Xilinx Platform Studio

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6. Select the radio button for Base System Builder wizard (recommended) then click OK. If the Create new or open existing project dialog does not come up automatically just select File New Project from the XPS tool bar.

Figure 4 – New Base System Builder Project

7. Select a location for your XPS project file (system.xmp) and associated files. You may type in a location or browse to a new or existing directory. Do not choose a directory under the EDK installation directory or a directory with a ‘space’ in the path. Check the box for Set Project Peripheral Repositories. This is the Local Peripheral Repository discussed earlier. Browse to the location of the unzipped XBD archive. Click OK.

Figure 5 – New Project

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8. Select the radio button for I would like to create a new design then press Next>.

Figure 6 – Base System Builder Welcome

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9. Select Avnet as the Board vendor. If Avnet is not an option, then either the XBD files were installed incorrectly or the Local Peripheral Repository was not referenced correctly. Select Spartan-3A Evaluation Board (3S400A) for the Board name. Select B for the the Board revision. Click Next>.

Figure 7 – BSB: Select Board

10. The next screen details the specific device on this board, which BSB extracts from the XBD file. This is not a user-editable option. MicroBlaze is also selected by default since Spartan-3A does not have an embedded PowerPC. Click Next>.

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Figure 8 – BSB: Select Processor

11. The next screen configures the MicroBlaze processor. For this example, keep the default Processor-Bus clock frequency of 66.67 MHz. A lower frequency is also possible. With MicroBlaze designs, the processor and the PLB bus must operate at the same frequency. In a Spartan 3A -4 device, 66.67 MHz is at the upper end of an ‘easily achievable’ operating frequency. As the complexity of the design and the number of peripheral devices attached to the PLB bus increases, the achievable clock frequency decreases. The Base System Builder wizard will generate the necessary clock management logic to generate the processor clock from the input reference clock. As with any FPGA design, ALWAYS check the PAR report and make sure the design meets timing! The on-chip HARDWARE debug module gives the option for hardware breakpoints and hardware read and write address watchpoints and a JTAG debug interface that can be used to connect via the XMD (Xilinx Microprocessor Debug) Engine and the GDB software debugger. A Xilinx JTAG programming cable connection to the board is required to use this interface.

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Since this board does not have any external RAM memory, increase the local memory space to 32 Kbytes. This memory is made up of the FPGA BRAMs. This device has 20 BRAMs and the 32 KB memory will take 16 of those. Enable the cache. Later in the wizard a memory controller for the parallel Flash on this board is added. Since there is limited RAM on this board using the option to execute application programs directly from Flash memory could be useful. Enabling an instruction cache for the Flash memory can make a significant improvement in performance. Click Next> to continue.

Figure 9 – BSB: Configure MicroBlaze Processor

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12. The Base System Builder wizard uses the XBD file to determine which I/O peripherals are available on the board. Select the USB_UART connection and use the XPS UARTLITE peripheral core. There is an option for a 16C550 compatible UART but for this tutorial, the smaller and simpler uartlite interface will do. Set the baudrate to 115200. This value doesn’t really matter as long as the same rate is set in the AvProg comm port or other communication program used. There are 4 LEDs on this eval board. Choose to include a General Purpose I/O (GPIO) peripheral to allow driving those LEDs. There are also 3 general purpose ‘push buttons’ on this board. Choose the GPIO interface to read from them as well. Even though the on-board temp sensor is not used for this tutorial, select to leave it for future use. It could be de-selected without impact on this tutorial. Click Next>.

Figure 10 – BSB: Configure I/O Interfaces (1 of 2)

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13. The parallel Flash memory controller is similar to the IIC Temp Sensor in that it is not used in this demo but could be useful for later experiments. Leave the SPI Flash memory controller off. At this time the Base System Builder cannot configure controllers for both the parallel Flash and SPI Flash in the same design. Click Next>.

Figure 11 – BSB: Configure I/O Interfaces (2 of 2)

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14. The next dialog allows specification of ‘internal peripherals’ such as timers, additional BRAM memory controllers, etc. that are not connected to external FPGA pins. No internal peripherals are used for this tutorial. Click Next>.

Figure 12 – BSB: Add Internal Peripherals

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15. The next screen configures the cache that was enabled during processor configuration. In this system, the only cacheable memory is the parallel flash. Parallel flash can be used directly for instructions but not for data. Therefore, change the Data Cache (DCache) Size to 0 KB. Click the checkbox to enable the Icache for the FLASH_2Mx16 peripheral. This cache consumes more BRAM on the FPGA. Click Next>.

Figure 13 – BSB: Cache Setup

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16. Accept the default STDIN and STDOUT. The other choice for the STDIN and STDOUT console device is the debug module ‘JTAG UART’. Since a Xilinx programming cable to the JTAG port is not connected for this tutorial, there is no access to this port. The ILMB (Internal Local Memory Bus) memory controller to the BRAM is the only RAM memory interface so accept the default Boot Memory. The Base System Builder will generate a memory test and a peripheral test application. The memory test app won’t really do much since it is a destructive test and there is no external RAM to test, but the Peripheral selftest application is used to demonstrate the tool flow. In general it is a good idea to use these auto generated applications to verify our hardware and connectivity before starting custom hardware and application development and debug. Click Next>.

Figure 14 – BSB: Software Setup

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17. Executing an application once the FPGA is configured requires that application to be linked to execute from the BRAM memory. For the simple test applications, target both applications to be executed from BRAM memory. If a program is too large to fit into the available BRAM memory to execute on startup, then a ‘bootloader’ program would be loaded into BRAM memory during FPGA configuration. This program would typically copy the larger program from non volatile memory into a larger external RAM memory and then jump to the application. However, that would not work with this board as there is no external RAM memory. The initial program startup section can be targeted to the BRAM memory while the remainder is designated to execute from Flash memory. The build process for this scenario is a little more complicated and beyond the scope of this tutorial. Clicking Next> on the two screens to configure the applications.

Figure 15 – BSB: Configure Memory Test Application

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Figure 16 – BSB: Configure Peripheral Test Application

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18. Review the System Summary, then click Generate.

Figure 17 – BSB: System Summary

19. The Base System Builder is done. Take a look at some of the files the BSB has generated. The system.mhs (Microprocessor Hardware Specification) file is the hardware description of our MicroBlaze design. The system.mss (Microprocessor Software Specification) file lists the software drivers for each of our peripherals. A User Constraint File (UCF) is also generated, which contains the FPGA pinout and timing constraints. The fast_runtime.opt file contains the parameters to be used by ISE to implement our design while the download.cmd is an iMPACT script. The source ‘C’ files for the auto generated test applications are also generated. Click Finish to continue on to the XPS GUI.

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Figure 18 – BSB: System Generation Finished

20. Select the radio button to Start using Platform Studio then click OK.

Figure 19 – BSB: Start using Platform Studio

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Modifying and building the system

The MicroBlaze hardware and software platforms are now generated. Examine the MicroBlaze design. A block diagram of the hardware platform is shown below.

FPGA

JTAG Header

MicroBlazeProcessor Core

GPIOOutput

Port

PLB

GPIOIntputPort

LEDsPush Buttons

UART

PSoC USB/UART Bridge

BRAM(32K)

Memory Controller

Microprocessor Debug Module

BRAM Controller

BRAM Controller

Flash

OSC@16 MHz

Clock Control

66.67 MHz

I2C

Temp Sensor

Reset Switch

Reset Control

Figure 20 – Hardware Platform Block Diagram

The System Assembly View is a graphical representation of the system.mhs specification file. Select the System Assembly View tab near the center of the screen to see this view.

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Figure 21 – System Assembly View

Feel free to explore the GUI if you have time. Select any of the components in the System Assembly View and right mouse click to see configuration, data sheet and software API options.

Figure 22 – Right-click example for USB_UART

At this point we need to select the option to Generate Netlist which runs synthesis on the design. Doing this calls the ISE – XST synthesis tools under the covers.

21. Select Hardware Generate Netlist. 22. During the Generate Netlist process a Bitgen Options File, bitgen.ut, is copied to the /etc

subdirectory. Select the Project tab to display the Project Files window. Double click the file to open.

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The default StartUpClk is JTAGCLK. This works fine when downloading via the Xilinx programming cable since iMPACT auto-corrects the StartUpClk. However, AvProg does not auto-correct the StartUpClk. Since Slave Serial Configuration mode is used, the StartUpClk must be changed to CCLK. Additionally, the default bitgen.ut file does not specify options for Unused I/Os and the Configuration Rate, which means the default options are used during bitstream generation. This can have adverse affects in some projects. Therefore, explicit settings are given for these options at this time.

23. Edit bitgen.ut to change the StartUpClk to CCLK. Add the following two lines to the file. Save and close the file.

-g UnusedPin:Pullnone -g ConfigRate:6

Once complete, the bitgen.ut file contents appear as follows:

-g CclkPin:PULLUP -g TdoPin:PULLNONE -g DonePin:PULLUP -g StartUpClk:CCLK -g ProgPin:PULLUP -g TckPin:PULLUP -g TdiPin:PULLUP -g TmsPin:PULLUP -g LCK_cycle:NoWait -g Security:NONE -g UnusedPin:Pullnone -g ConfigRate:6 #-m -g Persist:No

24. Select Hardware Generate Bitstream.

At this point the hardware design is complete.

25. Either with the XPS ‘File’ ‘Open’ command or Windows Explorer navigate to the /implementation subdirectory inside the project directory and open the ‘system.par’ (Place and Route Report) file. Scroll down to the bottom of the report and make sure all timing constraints were met before proceeding. This check should always be made before continuing on with development.

Now the software application to run on MicroBlaze is reviewed.

26. Select the Applications tab to display the Software Projects in the left GUI window.

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Figure 23 – XPS-generated Software Applications

Two auto-generated test applications exist. To create a new software application, double-click on Add Software Application Project. The Xilinx Software Development Kit (SDK) (an Eclipse based GUI) is another option for more advanced software development. For this tutorial, the TestApp_Peripheral application is modified.

27. Expand the Sources under Project: TestApp_Peripheral. Double click on the TestApp_Peripheral.c source file to open it up. Edit the text in the print command line to personalize this program. For example, change the text to say “Entering MY TEST PROGRAM”. Scroll around the program and see the selftests generated for the peripherals. Open the selftest example c files. There are examples for both selftest and driver code for most peripherals in the EDK installation directory. After editing the TestApp_Peripheral.C source save the file. Go to File Save to save the file. There is already a linker script that has been generated to map this executable to the BRAM memory. This selection was made in the Base System Builder wizard.

28. Only one software application can be designated or ‘marked’ to be loaded into BRAM during FPGA configuration. Right mouse click on the TestApp_Peripheral application and make sure the ‘Mark to Initialize BRAMs’ option is checked. If not, click to toggle. The ‘BRAM’ symbol to the left of the Project should not have a red ‘X’. When the Update Bitstream process is run later, the Data2mem utility will be run in the background to merge the software application executable with the FPGA ‘hardware’ bitstream. If the software application is changed and Update Bitstream re-run, XPS will compile the software application and re-run Data2Mem, but it will not have to repeat the synthesis and implementation steps.

29. The next step is to compile and link the application. Right click on the TestApp_Peripheral Project again and this time select Build Project. If an error appears on this step, re-check and make sure 32KB was selected as the local memory size. If it is smaller there might not be enough room in the memory for the application to fit.

30. As was mentioned earlier, the Data2Mem utility is run to merge the software executable with the hardware bitstream. The /implementation subdirectory of the project directory contains the system.bit file which is the hardware bitstream without initialized BRAMs. Once Update Bitstream is run, download.bit is created, which is system.bit with the software application initialized to the BRAM. Select Device Configuration Update Bitstream to perform this function now.

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Testing the system

For those using a Xilinx programming cable attached to the target board, the menu option Device Configuration Download Bitstream could be used directly from XPS to download the configuration to the FPGA via JTAG. However, this tutorial makes use of the Avnet AvProg utility and the USB to PSoC interface to configure the FPGA using Slave Serial mode.

31. Set the jumpers on the Avnet Spartan-3A Evaluation board as follows: • JP2:USB • JP4:M1 • JP5:SUSPEND OFF • JP6 • JP7:PWR

32. Attach the USB cable to the Avnet Spartan-3A evaluation board and the computer. 33. Launch AvProg. To do this, select Start All Programs Avnet AvProg. A GUI

similar to the following appears.

Figure 24 – AvProg

34. Select Options Comm. Configure the USB to Serial comm link to the eval board. Set the Comm Port to match the Spartan-3A Evaluation board port (in this example, COM3). Select the remaining parameters as shown below. Click OK when finished.

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Figure 25 – Comm Properties

35. Click ‘Connect to COMxx’ – if successful the button will change to ‘Disconnect from Comxx’.

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36. To verify the link to the board, download an example bit file, ‘blink4.bit’ that is included with the AvProg utility. Click Browse and navigate to C:\Program Files\Avnet\AvProg (default installation directory) and select blink4.bit.

37. Now click Configure FPGA to download bit file to the eval board. Click ‘Yes’ to verify device type. If things work correctly, an ‘FPGA programmed successfully!’ message is received in the AvProg Receive Console and the LED’s on the eval board should be blinking away.

Figure 26 – AvProg Configuration Test Successful

38. Browse to the FPGA bitstream built in XPS that includes the MicroBlaze design and modified TestApp_Peripheral test program. This is in the project directory at ./implementation/download.bit.

39. Click the Clear button in the lower right hand corner to refresh the Receive Console. 40. Now click Configure FPGA to download the new bit file to the eval board. Click OK to

verify device type as before.

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If everything worked correctly, the following message is displayed in the Receive Console. Additionally, the LEDs will blink in sequence once as part of the peripheral test.

FPGA programmed successfully! -- Entering MY TEST PROGRAM -- Running GpioOutputExample() for LEDS_4BIT... GpioOutputExample PASSED. Running GpioInputExample() for CS_PUSH_3BIT... GpioInputExample PASSED. Read data:0x0 Runnning IicSelfTestExample() for TEMP_SENSOR... IicSelfTestExample PASSED Running UartLiteSelfTestExample() for debug_module... UartLiteSelfTestExample PASSED -- Exiting main() --

Figure 27 – MicroBlaze TestApp_Peripheral Application Configured to FPGA

Scroll up and down in the AvProg Receive Console to see all of the messages. To repeat the test to see the LEDs again or values on EF1, EF2, or EF3, press EF4 to reset the FPGA and restart the MicroBlaze program from the beginning. Congratulations! You have completed a MicroBlaze hardware and software design and downloaded it to the Spartan 3A evaluation board.

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Additional Support For additional support, please review the discussions and post your questions to the Spartan-3A Evaluation Forum at http://groups.google.com/group/avnet-spartan-3a-eval-kit. You can also contact your local Avnet/Silica FAE.

http://groups.google.com/group/avnet-spartan-3a-eval-kit