Agile Condor: Scalable High Performance Embedded Computing Architecture
Objectives • Enable scalable real-time processing for
intelligence surveillance and reconnaissance (ISR) missions
• Fast technical refresh rate
• Design to support Group 3-5 DoD unmanned aerial systems (UAS)
• Weigh less than 60 pounds
• Consume less than 500 Watts of power
• Deliver over 15 GFLOPS/Watt (enabled by GPUs)
• Develop a rugged pod-based external payload
Operations Concept Overview
Vision Increase warfighter effectiveness by enhancing remotely piloted systems capabilities and expanding their capacity to create effects in the battlespace.
• Base on open industry standards
Pod and Chassis Details
• ISR missions face elevated demands in order to effectively operate in contested and challenged environments
• Agile Condor will support a rapid response to unexpected challenges
Future: Secure Bio-Inspired Computing Flight Tests • Agile Condor predecessor (6U VPX HPEC)
flight tested in July 2015
Greater system resilience, adaptability, autonomy and intelligence
• Oct. 2016 planned flight test for Agile Condor
• 12.8 GFLOPS/Watt (90% from GPUs)
• Embedded real-time experiments performed
Mark Barnell, Courtney Raymond Air Force Research Laboratory, Rome, NY
[email protected], [email protected]
DJ Isereau, Chris Capraro SRC, Inc., North Syracuse, NY
[email protected], [email protected]
14 slot 3U VPX conduction cooled chassis
• Existing pod baseline flight certified • MIL-STD-8591 design for aircraft interface and
aerodynamics • Ambient air cooling thermal management
Agile Condor brings distributed high-performance computing closer to the sensor
DISTRIBUTION A. Approved for public release; distribution unlimited (88ABW-2016-0194)
• Patent applied for
Latest generation Intel® Core™ i7 SBC 2 - NVIDIA® Maxwell™ GM107 GPUs • CUDA Compute Capability v5.0 • 1096 GFLOPS each • Delivers 88% of total processing
COTS upgradable
Presented at IEEE HPEC 2015
contact name
Mark Barnell: [email protected]
P6292
category: aerosPace & Defense - aD01
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