Chameleonic Radio

Technical Memo No. 10

A Candidate RF Architecture for aMultiband Public Safety Radio

S.M. Shajedul Hasan and S.W. Ellingson

September 28, 2006

Bradley Dept. of Electrical & Computer EngineeringVirginia Polytechnic Institute & State University

Blacksburg, VA 24061

A Candidate RF Architecture for aMultiband Public Safety Radio

S.M. Shajedul Hasan, S.W. Ellingson∗

September 28, 2006

Contents

1 Introduction 2

2 Architecture 22.1 RF Downconverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2 RF Upconverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Detailed Design for Receiver Section 5

∗Bradley Dept. of Electrical & Computer Engineering, 302 Whittemore Hall, Virginia PolytechnicInstitute & State University, Blacksburg VA 24061 USA. E-mail: ellingson@vt.edu

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1 Introduction

This report describes a candidate architecture for the radio frequency (RF) sectionof a multiband radio for public safety applications. This work is performed as partof the project “A Low Cost All-Band All-Mode Radio for Public Safety,” Grant2005-IJ-CX-K018, from the National Institute of Justice of the U.S. Dept. of Justice.The architecture described here accommodates public safety frequencies ranging from138 MHz to 894 MHz as described in [1]. Although frequencies greater than 894 MHzare also potentially of interest, the issue of how to tackle the remaining bands poten-tially of interest (i.e., PCS, 2.4 GHz, and 4.9 GHz) is not addressed in this report.

The candidate architecture is presented in Section 2. Note that in this phase ofthe project, cost is not a consideration. Rather, the emphasis is proof of concept.However, to demonstrate the efficacy of this architecture, Section 3 presents a de-tailed component-level and printed circuit board design for a section of the receivechain.

2 Architecture

The transceiver architecture proposed for this radio, described in [2] and shown inFigure 1, requires that the RF downconverter (RFDC) move a 40 MHz swath ofspectrum from RF to an intermediate frequency (IF) centered at 78 MHz, where it isdigitized. The RF upconverter (RFUC) is required to do the opposite.

2.1 RF Downconverter

A block diagram of the proposed RFDC is shown in Figure 2. The first stage of theRFDC is a switched preselector, which routes the RF through one of three filter paths.The three bands provided by the preselector are 138–222 MHz, 450–512 MHz, and764–894 MHz. The purpose of preselection is to improve dynamic range by isolatingstrong signals which are outside the band of interest.

Following the preselector is an “up-down” frequency converter. The RF is mixedup to a first IF of 1250 MHz using a high-side local oscillator (LO). Here it is bandpass-filtered, and most of the selectivity occurs here. The resulting undesired sidebandis 2638–3394 MHz, and is easily rejected since the desired bandpass is only about40 MHz around 1250 MHz. The IF frequency of 1250 MHz was selected due to theavailability of suitable surface mount filters. In this case, a Lark Engineering1 “MC”Series filter is a candidate; specifically Part No. MC1250-60-3MM, which provides60 MHz 3 dB bandwidth, 3 dB insertion loss, S12 < −60 dB across the image band,and S12 < −40 dB against the local oscillator (LO). 60 MHz bandwidth is appropriate

1http://www.larkengineering.com

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Figure 1: Proposed transceiver architecture (from [2]).

so as to ensure that the central 40 MHz of interest remain spectrally relatively flat,and free of distortion induced by the filter band edges. A diplexer is used to absorbas much LO power as possible, so as to reduce reflection into the mixer and also toimprove the rejection through the 1250 MHz IF strip. A local oscillator which tunesfrom 1388 MHz to 2144 MHz is required.

The second frequency conversion moves the IF from 1250 MHz to 78 MHz. Again,a diplexer is employed to mitigate reflection into the mixer and to provide some addi-tional suppression of the 1328 MHz LO. It is assumed that an antialiasing filter andA/D driver appropriate to the A/D component and sample rate are used, but theseare not considered here.

This design yields a cascade gain, input third-order intercept (IP3), and noisefigure of +38.3 dB, −13.5 dBm, and 9.1 dB, respectively. The noise figure correspondsto a sensitivity of −115.3 dBm with respect to the TIA-603 criterion of 12 dB SINADwith 20 dB quieting [3]. The TIA-603 standard is −116 dBm, thus this design isalready quite close to meeting this specification. The ultimate design will probablyincorporate some additional low-noise gain following the preselector, which is certainto improve the sensitivity significantly.

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2.2 RF Upconverter

A block diagram of the proposed RFUC is shown in Figure 3. The architecture mirrorsthat of the RFDC so as to allow the use of common LOs. Thus, the first stage is anupconversion from 78 MHz to 1250 MHz, and the second stage is a downconversionfrom 1250 MHz to the desired RF. In lieu of a preselector, a single bandpass filterwith a passband from 138 MHz to 894 MHz is used, and exists primarily to suppressspurious signals including the strong LO feedthrough above 1388 MHz. Additionalrejection above 1 GHz is provided by the diplexer following the second mixer.

This design yields a cascade gain and output (IP3) of +49.2 dB and +28.3 dBmrespectively. Thus, a −30 dBm input provided by a digital IF section will resultin a output of +19.2 dBm (approximately 100 mW), with good linearity. A poweramplifier (PA) with 17.8 dB gain is required to achieve 5 W output power; this isprobably best implemented using separate PAs to cover different parts of the tuningrange. This is probably not a limitation as it will be extremely difficult to develop anantenna which is sufficiently well-matched to handle 5 W across this tuning range.

3 Detailed Design for Receiver Section

To provide some additional insight into the performance of this design, the RFDCshown in Figure 2, minus the preselector, is currently being constructed and evaluated.The detailed design is shown in Figure 4. Two options for the 78 MHz IF filter areshown: One using a single plug-in filter, and a second using discrete surface mountcomponents. One or the other would be used, but not both. Figure 5 shows the toplayer of the associated printed circuit board (PCB). The PCB is FR4, 6 in × 3.45 in,and contains 4 layers: top (component side), ground, power, and bottom. The PCBwas designed using the CadSoft2 Eagle Layout Editor. The design files, including theschematic and a bill of materials, is available via the project web site [4].

References

[1] S.W. Ellingson, “Requirements for an Experimental Public Safety Multi-band/Multimode Radio: Analog FM Modes,” Technical Memo No. 8, July 27,2006, http://www.ece.vt.edu/swe/chamrad/.

[2] S. Ellingson and J. Reed, “Multi-Band Multi-Mode Radio for Public Safety,”International Wireless Communications Expo (IWCE), Las Vegas, NV, May 19,2006. Available at http://www.ece.vt.edu/swe/chamrad/.

2http://www.cadsoft.de

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Figure 4: A possible implementation of the RFDC architecture shown in Figure 2,minus preselector.

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Figure 5: Top (component) side of the PCB implementing the partial RFDC designshown in Figure 4.

[3] Telecommunications Industry Association, “TIA Standard: Land Mobile FM orPM – Communications Equipment – Measurement and Performance Standards,”TIA-603-C, December 2004.

[4] Project web site, http://www.ece.vt.edu/swe/chamrad/.

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