XRC Mentor

Calibre® xRC™ Parasitic ExtractionLab Workbook

Software Version 2010.2

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Calibre xRC Parasitic Extraction, 3

Table of Contents

Lab 1Extraction Basics Quiz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Lab 2Calibre xRC Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Exercise 1:Creating a PEX Runset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Exercise 2:Running Calibre xRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Exercise 3:Displaying the 3-Stages in the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Exercise 4:Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Lab 3Running Calibre xRC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Exercise 1:Extracting Parasitic Resistors Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Exercise 2:Extracting Parasitic Capacitors Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Exercise 3:Extracting All Parasitic Capacitors and Resistors . . . . . . . . . . . . . . . . . . . . . . 27Exercise 4:Inspecting Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Lab 4Leveraging Design Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Exercise 1:Flat Transistor-Level Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Exercise 2:Gate-Level Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Exercise 3:Full Hierarchical Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Exercise 4:Hybrid Hierarchical Extraction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Lab 5Generating Extracted Netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Exercise 1:Extracting Selected Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Exercise 2:Generating Layout Based Netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Exercise 3:Generating a Source-Based Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Lab 6Reduction Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Exercise 1:Simulation for the Ideal Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Exercise 2:Simulation With RCC Parasitic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Exercise 3:TICER Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table of Contents

4 Calibre xRC Parasitic Extraction,

Lab 7Extraction in Your Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Exercise 1:Design 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Exercise 2:Design 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Exercise 3:Design 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Exercise 4:Design 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Lab 8Working With PEX Rule Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Exercise 1:Mapping Layer Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Exercise 2:Exploring Device Interconnect Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Exercise 3:Adjusting Extraction Within the Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Answer Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84


Lab 1Extraction Basics Quiz

Q. 1. Name four or more factors you should consider when choosing a parasitic extraction strategy.

• ________________________________________________________

• ________________________________________________________

• ________________________________________________________

• ________________________________________________________

• ________________________________________________________

• ________________________________________________________

• ________________________________________________________

Q. 2. List four or more terms that can have different meanings depending on the context within the physical verification flow.

• ________________________________________________________

• ________________________________________________________

• ________________________________________________________

• ________________________________________________________

• ________________________________________________________

• ________________________________________________________

• ________________________________________________________

Q. 3. What is the goal of parasitic extraction? ___________________________

_____________________________________________________________

Q. 4. List three types of analysis that require extraction.

• ________________________________________________________

• ________________________________________________________

• ________________________________________________________

Q. 5. What are the inputs for extraction?

Calibre xRC Parasitic Extraction,6

Extraction Basics Quiz

• ________________________________________________________

• ________________________________________________________

Q. 6. What are the two basic types of extracted netlists?

• ________________________________________________________

• ________________________________________________________

Q. 7. List three or more prerequisites for performing extraction with Calibre xRC.

• ________________________________________________________

• ________________________________________________________

• ________________________________________________________

• ________________________________________________________

• ________________________________________________________

Q. 8. What portions of a layout are extracted? ___________________________

_____________________________________________________________

_____________________________________________________________

Q. 9. Which of the following is not a type of parasitic network available from Calibre xRC:

• R

• RC

• RCC

• C

• CC

• Simple


Lab 2Calibre xRC Basics

IntroductionThe objective of this lab is to familiarize you with Calibre xRC through the use of its graphical user interface.

In this lab, all procedural steps contain detailed step-by-step instructions and information. As you gain experience in performing these common procedures, the subsequent labs will provide fewer instructions on these low level tasks so as to focus on new procedures.


Calibre xRC Basics Creating a PEX Runset

Exercise 1: Creating a PEX RunsetIn this exercise, you will launch graphical user interface for Calibre xRC from the UNIX command line. You will enter paths and select options in this GUI. You will save these settings in a runset.

1. Log in to the workstation following the instructor’s login instructions.

2. Open a shell window and navigate $MGC_LAB/lab2.

cd $MGC_LAB/lab2

3. List the content of this directory.

ls -l

There are at least 7 files in this lab2 directory:

If any file is missing, contact your instructor at once.

4. Launch Calibre GUI for xRC:

calibre -gui -pex

Table 2-1. Lab2 Files and Directories

File Description

adder_4.gds GDS of the design

adder_4.gds.layerprops Layer properties file

adder_4.sp SPICE netlist of the design

cap.rule Rule file with parasitic capacitance statement

drc.rule Rule file for DRC

lvs.rule Rule file for LVS

pex.rule Rule file for parasitic extraction

template Templates directory



The Calibre Interactive - PEX window appears with the Load Runset File dialog box in front of it, similar to the picture below:

5. Click Cancel on the Load Runset File dialog box.

Notice the first 3 buttons on the left-hand side of the Calibre Interactive - PEX window are red.

Their red color indicates that Calibre xRC is not ready to run due to insufficient information.

6. Click Rules.

7. In the PEX Rules File field, edit the default entry to read “pex.rule”.

Note the text first appears as red as you start typing, then changes to green once the file name is typed in correctly. If it stays red, there is a typographical error, which you must correct before continuing.

Q. What color is the Rules button now? ________________________________

_____________________________________________________________



8. Click Inputs.

9. With the Layout tab selected, click the Browse ( ) button at the far right-hand side. This action opens the Choose layout file dialog box.

10. Highlight adder_4.gds and click the OK button near the bottom right-hand corner.

These actions populate the Layout File field with the layout file name.

11. Make sure the Format is GDSII and “Export from layout viewer” is unselected.



12. In the Top Cell field, enter “adder_4”. The completed Inputs > Layout tab should look as follows:

Q. What color is the Inputs button now? _______________________________

_____________________________________________________________

Q. Why? ________________________________________________________

_____________________________________________________________

13. Click the Netlist tab.

14. Type “adder_4.sp” in the Files field.

Note the down-arrow to the right of this field. Clicking on the down-arrow expands the field, allowing you to enter multiple netlist file names. This feature makes it possible to run extraction using a multi-file circuit netlist.

15. Make sure the Format is SPICE and “Export from schematic viewer” is unselected.

16. In the Top Cell field, type “adder_4”. The completed Inputs > Netlist tab should look as follows:



Notice the Inputs button is now green. (If it is still red, compare your entries against those in this lab workbook. Correct any typographical error before continuing.)

17. Click Outputs.

18. Verify that in the Extraction Mode area, xRC is selected.

19. In the Extraction Type area, make sure Transistor, Level, R + C + CC, and No Inductance are selected.

20. Click the Netlist tab.

21. In the Format field, select HSPICE.

22. In the Use Names From field, select SCHEMATIC.

23. In the File field, type in “adder_4.pex.hspice” and select “View netlist after PEX finishes”.

Note the Outputs button is now green. There is now enough information in the Calibre Interactive - PEX GUI for Calibre xRC to run.

24. In the Calibre Interactive - PEX window, choose Transcript > Echo to File.

The Set PEX Transcript Echo File dialog box appears.



25. In the Set PEX Transcript Echo File dialog box, select “Echo transcript to file” and type “log.xrc” in the Path field.

26. Click OK to close this dialog box.

27. Choose File > Save Runset As to open the Save PEX Runset dialog box:

28. In the Save PEX Runset dialog box, type “runset1” and click OK.

This action saves all entries and selections in the Calibre Interactive - PEX to the runset1 file.

You have just created & saved a runset for Calibre xRC. This runset is a record of your entries, option selections and settings for Calibre xRC, which can be used in later runs. In subsequent labs, whenever appropriate, runsets will be made available to you.

Do NOT close the Calibre Interactive - PEX window.


Calibre xRC Basics Running Calibre xRC

Exercise 2: Running Calibre xRCThe purpose of this exercise is to run Calibre xRC from the GUI. You will examine the transcript, also known as the log file, after the run.

1. In the Calibre Interactive - PEX window, click Run Pex to launch Calibre xRC.

When Calibre xRC completes, a window containing the extracted netlist appears. The contents of this window will be covered in later lectures. You can examine it now if you like. Close this window when you are finished.

2. In the Calibre Interactive - PEX main menu, choose File > View Text File.

3. In the View Text File dialog box, type “log.xrc” then click OK.

This opens the new log file in an ASCII text viewer and editor.

Q. What does the first line in the log.xrc tell you?

_____________________________________________________________

Q. Identify the 3 command lines necessary to produce a netlist with extracted parasitic elements: (Hint: They all begin with $MGC_HOME/bin/calibre.)

• calibre_________________________________________________

• calibre_________________________________________________

• calibre_________________________________________________

If you wanted to, you could create a script for running Calibre parasitic extraction by copying these 3 command lines into a new file.

Q. Which rule file do these commands use?_____________________________

_____________________________________________________________

Note that this is a control file, generated by the GUI. It contains all the settings you defined in the user interface and uses INCLUDE to reference the rule file you specified in the Rules pane.

4. Close the text editor when you are finished reviewing this file.

Calibre xRC Basics Displaying the 3-Stages in the GUI


Exercise 3: Displaying the 3-Stages in the GUIThe purpose of this exercise is to show you the 3-stage process of Calibre parasitic extraction explicitly displayed in the GUI.

1. In Calibre Interactive - PEX window, click Run Control, then click the Advanced tab.

Note the 3 buttons, each of which begins with the word Run. These are the 3 stages of Calibre parasitic extraction.

2. Select “Show PEX steps in task button bar”.

Notice that three buttons are now added below the Transcript button on the left-hand side of the GUI.

You can now specify which stage or stages of Calibre parasitic extraction to run using the buttons on this left-hand panel.


Calibre xRC Basics Getting Help

Exercise 4: Getting HelpIn this exercise, you will learn the basics of where and how to find help about Calibre Interactive, Calibre xRC, or any other Calibre products. Within the Calibre Interactive GUI, there are two types of help: Tool Tips, and Help through product manuals. Tool Tips give you brief descriptions of most buttons or fields as you hover your cursor over them. Manuals give you detailed information about the tools.

1. Make the Calibre Interactive - PEX window is active.

2. From the menu, choose Setup. Make sure Show Tool Tips is selected.

3. In the main Calibre Interactive window, place the cursor over a button or field. If a Tool Tip is available, after a few seconds a brief description of the button or field is displayed.

4. Click Inputs, then make sure the Netlist tab is selected.

5. Put the cursor over the Files field. A small yellow box will appear after a few seconds.

Q. What is the tool tip for this Files field? ______________________________

_____________________________________________________________

Q. What interesting piece of information did you learn about this field from the Tool Tip? _________________________________________________________

_____________________________________________________________

6. Try the Tool Tip for the button at the end of the Files field.

Q. What is the tool tip for the Browse button?___________________________

_____________________________________________________________



7. In the Calibre Interactive - PEX menu, choose Help > Help and Manuals to open a web browser window.



8. Click the Parasitic Extraction (PEX) button on the left-hand side of the browser.

The main panel of the InfoHub browser now displays the manuals related to parasitic extraction. As shown in the picture above, there are three tabs in this InfoHub. Click each one to view the functions available:

• Help & Manuals — displays the manuals available with your Calibre installation.

• Support & Training — provides links to the Mentor Graphics SupportNet website, if Internet access is available on your workstation.

• System Admin — displays Release Notes and Installation Guides for Calibre.

Return to the Help & Manuals tab.

9. Highlight the Calibre xRC User’s Manual.

You can open this manual in either HTML or PDF format. The content is the same.

10. Click the Open HTML to open the content of the Calibre xRC User’s Manual.



The content of the Calibre xRC User’s Manual is displayed in a separate browser window.

11. Click the Search tab.

12. Enter “hspice” in the field at the top left-hand corner of browser, then click Go!.

13. In the left-hand panel of the browser, click “HSPICE and Spectre Output Files”.



The right-hand panel presents its findings:

If time permits, perform more searches until you are comfortable with this function.

14. Close all InfoHub windows.

15. Close the Calibre Interactive- PEX window from the main menu, File > Exit.

16. When prompted, do not save the runset.


Lab 3Running Calibre xRC

IntroductionThe first goal of this lab is to practice running Calibre xRC to create netlists representing various parasitic networks. You will apply knowledge gained from previous labs to launch Calibre xRC runs. You will build a transistor-level netlist with parasitic resistors, then progress to a transistor-level netlist with parasitic resistors and capacitors. To make it easy to compare the resulting netlists, you will use as the same format for all: HSPICE.

The second goal is to practice inspecting the results of parasitic extraction in a layout tool using Calibre RVE. This lab uses Calibre DESIGNrev as the layout viewing tool, because of its quick load time and seamless integration with the other Calibre tools.


Running Calibre xRCExtracting Parasitic Resistors Only

Exercise 1: Extracting Parasitic Resistors OnlyIn this exercise, you will run Calibre xRC to extract only parasitic resistors and produce a flat transistor-level HSPICE netlist.

1. Change directories to $MGC_LAB/lab3.

2. Launch the Calibre Interactive - PEX:

calibre -gui -pex

3. Click Cancel on the Load Runset File dialog box.

4. Input the following files & settings in the Calibre Interactive - PEX window:

Table 3-1.

Pane Tab Field Setting

Rules PEX Rules File pex.rule

Inputs Layout File adder_4.gds

Inputs Layout Format GDSII

Inputs Layout Export from layout viewer unselected

Inputs Layout Top Cell adder_4

Inputs Netlist Files adder_4.sp

Inputs Netlist Format SPICE

Inputs Netlist Export from schematic viewer unselected

Inputs Netlist Top Cell adder_4

Outputs Extraction Type Transistor Level

Outputs Extraction Type R

Outputs Extraction Type No Inductance

Outputs Netlist Format HSPICE

Outputs Netlist Use Names From SCHEMATIC

Outputs Netlist File adder_4.hspice.R

Outputs Netlist View netlist after PEX finishes selected



After all entries, your Calibre Interactive - PEX window look as follows:

5. Echo the transcript to file log.pex.R.

6. Save the runset to file runset.R.

7. Run PEX.

When Calibre xRC completes, a window containing the netlist adder_4.hspice.R opens.

8. Examine the content of this netlist & answer the following questions:

Q. How many subckt statements are there in this netlist? __________________

_____________________________________________________________

(Hint: In the PEX Netlist File window, choose Options > Search to look for “subckt.”)

Q. How many files are referenced by this netlist? ________________________

_____________________________________________________________

(Hint: Search for the “include” statement)

These files are necessary for successful post-layout simulations. Next we will look at one of the included files.

9. From the PEX Netlist File window, choose File > Open.

This opens the Open a Text File dialog box.



10. In the Open a Text File dialog box, select adder_4.hspice.R.pex file and click Open.

11. In the Open File dialog box, click New Window.

Q. What does this file contain?_______________________________________

_____________________________________________________________

Q. Are there any parasitic element other than resistors? ___________________

12. Leave the Calibre Interactive - PEX and shell window open, but close all other windows and dialog boxes.

Running Calibre xRCExtracting Parasitic Capacitors Only


Exercise 2: Extracting Parasitic Capacitors OnlyThe goal of this exercise is to extract only parasitic capacitors from the interconnect wires in the GDS, and then build a flat transistor-level HSPICE netlist. You will use a runset to achieve this goal.

1. In the Calibre Interactive - PEX window, select File > Load Runset.

This selection opens the Load Runset File dialog box.

2. In the Load Runset File dialog box, either select the runset.C file, if shown, or use the Browse button to search for this runset. Then click OK to load this runset.

Verify that all buttons on the left-hand side of the Calibre Interactive - PEX window are green. You can click any or all these buttons and look at the entries and selections.

3. In the Calibre Interactive - PEX window, click Outputs, and then click Reports tab.

4. In the Reports tab, click the Net Summary report tab.

Q. What is the name of the file to which the net summary report will be written?

_____________________________________________________________

5. Click Run PEX.

When Calibre xRC completes, a file window opens displaying the adder_4.hspice.C netlist.

6. From this window, use the File menu options to open the pex_rep_sumry.C file in a new window.

Q. What type of information do you see?_______________________________

_____________________________________________________________

Q. What types of parasitic effects are represented?


Running Calibre xRCExtracting Parasitic Capacitors Only

_____________________________________________________________

7. In the pex_rep_sumry.C file, find the answers to the following questions about source net INB13.

Q. What is its total parasitic capacitance?

_____________________________________________________________

Q. What is its total coupled capacitance of net INB13?

_____________________________________________________________

8. Close all windows except the shell windows.

Running Calibre xRCExtracting All Parasitic Capacitors and Resistors


Exercise 3: Extracting All Parasitic Capacitors and Resistors

This exercise has many goals:

• Launch Calibre xRC from a layout tool. For this exercise, the layout tool will be Calibre DESIGNrev.

• Run Calibre xRC to extract all parasitic capacitance and resistance elements and build a flat transistor-level HSPICE netlist.

• Launch Calibre RVE and display these parasitic elements.

1. In a UNIX shell window, open the adder_4.gds physical design file in Calibre DESIGNrev.

calibredrv -m adder_4.gds

NoteRun Calibre DESIGNrev (calibredrv) in foreground mode only. Do NOT put it in background mode.

This command launches Calibre DESIGNrev to display the layout adder_4.



2. On your keyboard, press the number 3 key. This increases the view depth, allowing you to see the contents of the cells within your design.

3. In Calibre DESIGNrev menu, choose Verification > Run PEX.

This menu selection launches Calibre Interactive - PEX window.



4. Load runset.RCC.

5. Run PEX.

6. When Calibre xRC run completes, two windows will open:

• PEX Netlist File - adder_4.hspice.RCC

• Calibre - RVE

7. Use the Pex Netlist File to answer the following questions:

Q. What netlist files are INCLUDEd in this one? ________________________

_____________________________________________________________

Q. How man files are required to fully represent the netlist?________________

_____________________________________________________________

Q. Why? ________________________________________________________

_____________________________________________________________

_____________________________________________________________

_____________________________________________________________

8. Close the PEX Netlist File window and minimize the Calibre Interactive - PEX window by clicking on Minimize button in the upper right-hand corner.

9. Arrange the Calibre DESIGNrev and RVE windows so that both are visible and easily accessible, then proceed to the next exercise.


Running Calibre xRCInspecting Parasitics

Exercise 4: Inspecting ParasiticsIn this exercise you will use the highlight and cross-probing features available through Calibre RVE to get a deeper understanding of the parasitics in this chip. Note that highlighting and cross-probing requires functioning socket communication between the layout viewer and Calibre RVE. Socket communication is automatically set up for you when you invoke Calibre Interactive or Calibre RVE from within the layout viewer, as described in the previous labs.

1. Click anywhere in the Calibre - RVE window to give it focus.

Q. What type of information do you see?_______________________________

_____________________________________________________________

2. In the adder_4 table of nets displayed in the Calibre - RVE window, click on the C+CC Total(F) column header to sort its entries from high to low. (You may need to extend the window or use the horizontal scroll bar to display this column.)

Clicking on any column header will sort its entries from low to high (or in alphabetical order). Clicking it again will reverse its order.



3. Open the net summary report within Calibre - RVE by choosing File > Open Text File, then selecting pex_rep_sumry.RCC in the Open Text File dialog box.

The tool creates a new tabbed window to display this file.

4. Configure the tabs so you can view the report summary and the adder_4 table of nets side by side by right-clicking the pex_rep_sumry.RCC tab and choose New Tab Group from the pop-up menu.

Q. What information can you find in the adder_4 table of nets but not in pex_rep_sumry.RCC? ___________________________________________

_____________________________________________________________

Q. What information can you find in pex_rep_sumry.RCC but not in the adder_4 table of nets?

_____________________________________________________________



Q. How do you explain the differences between C Total (F) in the adder_4 table of nets and TotalC in the pex_rep_sumry.RCC?

_____________________________________________________________

_____________________________________________________________

_____________________________________________________________

5. Click the x in the upper right of the Navigator tab to close that tab and make more space for the adder_4 and pex_rep_sumry.RCC tabs.

6. Resize the Calibre RVE window and tabs as needed to display the entire Find Nets and Coupling Capacitance bar at the bottom of the adder_4 tab.

7. Calculate the coupling capacitance between the gnd! net and all other nets:

a. On the Find Nets and Coupling Capacitance bar, click the button to the right of All Nets.

This deselects All Nets and enables a text box into which you can type the names of one or more nets.

b. Type “vdd!” in the text box you just enabled, then press Enter.

The tool updates the values in the table of nets.

c. Compare the values in the adder_4 table of nets to the values in the pex_rep_sumry.RCC file to answer the following questions:

Q. How does coupling capacitance to vdd! differ from the total coupling capacitance?

_____________________________________________________________

Q. What information was added to the CC Total (F) column in the table of nets?

_____________________________________________________________

Q. What do they represent? _________________________________________

_____________________________________________________________

_____________________________________________________________

8. Close the pex_rep_sumry.RCC file by clicking the x in the upper corner of that tab.

NoteYou must give the tab focus to see the x.



9. In the table of nets, right-click on the row for the layout net INB1(3), then choose Show Net Info off the popup menu.

The tool displays net information in the Info tab in the left side of the window.



10. Explore the net information in the Into tab by clicking on any “+” icon of interest.

Q. What kind of information can you find in the Info tab? _________________

_____________________________________________________________

Q. Is this where you would look to see the parasitics for the net? ____________

_____________________________________________________________

11. In the table of nets, double-click on the row for the layout net INB1(3).



The tool adds a new area to the adder-4 tab to display the parasitics for this net.

Q. What types of information do you think you will find in this tab? _________

_____________________________________________________________

12. On the top row of this new tab, click the small blue box containing the letter R.

Q. What happened?________________________________________________

_____________________________________________________________

Q. What do you think you could do if you wanted to highlight only the resistors on a specific layer? _________________________________________________

_____________________________________________________________

_____________________________________________________________

Test your answer.

13. Experiment by clicking the other blue boxes in the Info tab and in the Detailed Parasitics View.



In the window shown above, clicking any lettered blue boxes will highlight that item in the layout editor.

Q. One of the blue boxes containing an R does not highlight anything. Which one is it?

_____________________________________________________________

Q. What does it do? _______________________________________________

_____________________________________________________________



Highlighting the parasitic resistor of MT2 geometry of net INB13 produces the following:

14. In the Calibre RVE, click the Erase button( ) to erase all highlights.

15. Experiment with the blue boxes containing squares rather than letters.

Q. What happens?_________________________________________________

_____________________________________________________________

_____________________________________________________________

_____________________________________________________________

16. In the Calibre RVE, click the Erase button( ) to erase any highlights.

17. Calculate resistance between specified points:

a. In the Detailed Parasitics View, click the row for Pt-to-Pt Res.



The tool opens the Point-to-Point Resistance Calculator.

b. Notice the default values, which instruct the tool to calculate point-to-point resistance between all pins, with pin names specified using layout names.

c. Click the down-arrow for the To: Pin entry field (just left of the Delete All button) and select pin g on X0/M7.

d. Click Calculate.

Q. How many resistance values does the tool calculate? ___________________

_____________________________________________________________

Q. Where is the most resistance? _____________________________________

_____________________________________________________________

e. Double-click on the largest resistance value in the Point-to-Point Resistance Calculator to highlight the associated devices in the layout.

f. In the Calibre RVE, click the Erase button( ) to erase the highlights.

g. If time permits, practice with calculating point-to-point resistance between ports, between specified coordinates, and between various combinations of pins, ports, and coordinates. If you get stuck, refer to the Calibre Interactive User’s Manual for help.

18. Close all Calibre windows to conclude this exercise and lab.


Lab 4Leveraging Design Hierarchy

The primary goal of this lab is to build and compare the different styles of netlists, from flat transistor-level to full hierarchical. The format of choice for the output netlists is HSPICE.


Leveraging Design HierarchyFlat Transistor-Level Extraction

Exercise 1: Flat Transistor-Level ExtractionIn this exercise, you will run Calibre xRC to construct a flat transistor-level netlist.


2. Launch Calibre Interactive GUI for xRC.

calibre -gui -pex

3. Load the runset runset.RCC.transistor, which is in the lab4 directory.

4. In the Calibre Interactive - PEX window, click Run PEX.

5. When Calibre xRC run completes, its output netlist appears in a window. The name of this netlist is adder_4.RCC.transistor.

Q. How many subckts are there in this output netlist?

_____________________________________________________________

Q. What are the primitive devices shown in this main output netlist?

_____________________________________________________________

Q. Is this transistor-level netlist flat or hierarchical? ______________________

_____________________________________________________________

Q. How many other files are 'included' in this output netlist?

_____________________________________________________________

Q. Why does it take three files to represent this flat netlist? ________________

_____________________________________________________________

6. From the menu, choose Options > Line Numbers to display the line numbers on the left-hand side of the window.

Q. How many lines are there in this file?

Leveraging Design HierarchyFlat Transistor-Level Extraction


_____________________________________________________________

7. Close the output netlist window when done. Do NOT close the Calibre Interactive - PEX window or any shell windows.


Leveraging Design HierarchyGate-Level Extraction

Exercise 2: Gate-Level ExtractionThe goal of this exercise is to produce a gate-level netlist from Calibre xRC and compare it to the flat transistor-level netlist from the previous exercise.

1. In the Calibre Interactive - PEX window, load runset.RCC.gate. (You do not have to save previous runset.)

2. Click Inputs then select the H-Cells tab.

Q. What is the name of the h-cell file? _________________________________

_____________________________________________________________

Q. What is the name of the x-cell file? _________________________________

_____________________________________________________________

3. Click the View button to the right of the PEX x-Cells file field.

A text editor window opens displaying the xcell.adder_4 file.

Q. How many cells are in this file?

_____________________________________________________________

Close this window when done.

4. Run PEX.

At the completion of the Calibre xRC run, a window opens displaying the adder_4.RCC.gate netlist file.

Q. How many subckts are there in the output netlist adder_4.RCC.gate? ______

_____________________________________________________________

Q. What are the primitive devices shown in this main output netlist? ________

_____________________________________________________________

Q. How many other files are 'included' in this output netlist?

_____________________________________________________________

Q. Is this gate-level netlist flat or hierarchical? __________________________

_____________________________________________________________

Q. How many lines are there in this file?

_____________________________________________________________



Another way to compare the size of this gate-level netlist to the one from the previous exercise is to list the file size in UNIX.

5. In a second UNIX shell window, navigate to the $MGC_LAB/lab4 directory and issue the following command:

ls -l | grep adder_4.RCC.

Q.Enter the file sizes for each of the files listed below:

• adder_4.RCC.transistor ____________________________________

• adder_4.RCC.transistor.pex _________________________________

• adder_4.RCC.transistor.adder_4.pxi __________________________

• adder_4.RCC.gate_________________________________________

• adder_4.RCC.gate.pex _____________________________________

• adder_4.RCC.gate.adder_4.pxi ______________________________

6. In the File Viewer containing the netlist, choose File > Open and open the file adder_4.RCC.gate.pex in a new window.

Q. What kind of information does this file contain? ______________________

_____________________________________________________________

Q. How many subcircuits does it contain? ______________________________

_____________________________________________________________

Q. What do you notice about the subcircuits in this file?___________________

_____________________________________________________________

7. In the File Viewer containing the netlist, choose File > Open and open the file adder_4.RCC.transistor.pex in a new window.

Q. How many subcircuits does it contain? ______________________________

_____________________________________________________________

Q. What do you notice about the subcircuits in this file?___________________

_____________________________________________________________

8. In the File Viewer containing adder_4.RCC.gate.pex choose File > Open and open the file adder_4.RCC.gate.adder_4.pxi,

Q. What kind of information does this file contain? ______________________

_____________________________________________________________

Q. How many lines does it contain? ___________________________________



_____________________________________________________________

Q. What do you notice about the nets in this file? ________________________

_____________________________________________________________

_____________________________________________________________

9. In the File Viewer containing adder_4.RCC.transistor.pex, choose File > Open File and open the file adder_4.RCC.transistor.adder_4.pxi.

Q. How many lines does it contain? ___________________________________

_____________________________________________________________

Q. What do you notice about the nets in this file? ________________________

_____________________________________________________________

_____________________________________________________________

Q. Why are the files adder_4.RCC.gate.* smaller than their transistor-level equivalents? ___________________________________________________

_____________________________________________________________

10. Close all File Viewer windows. Do not close the Calibre Interactive - PEX and shell windows.

Leveraging Design HierarchyFull Hierarchical Extraction


Exercise 3: Full Hierarchical ExtractionIn this exercise, you will produce a full hierarchy. After you have generated this output file, you will compare it to the previous two.

1. In the Calibre Interactive - PEX window, load the runset runset.RCC.hier_full.

2. Click the Outputs button.

Q. What extraction type is selected? __________________________________

_____________________________________________________________

3. Run PEX.

A new window displays the adder_4.RCC.hier_full at the successful completion of the Calibre xRC run.

Q. How many 'subckt' are there in adder_4.RCC.hier_full? ________________

_____________________________________________________________

Q. Why is this number higher than then number of cells in xcell.adder_4? ____

_____________________________________________________________

Q. What type of element is instantiated within the primary subckt? __________

_____________________________________________________________

Q. What is its name?_______________________________________________

_____________________________________________________________

Q. What types of elements are instantiated within the other subckts?

. ____________________________________________________________

Q. What are the sizes of the netlist files?

adder_4.RCC.transistor__________________________________________

adder_4.RCC.gate ______________________________________________

adder_4.RCC.hier_full___________________________________________

Q. How many pxi files are there for the each of these extractions?

adder_4.RCC.transistor__________________________________________

adder_4.RCC.gate ______________________________________________

adder_4.RCC.hier_full___________________________________________

(Hint: there must be one pxi file for each 'subckt' in the main output netlist.)


Leveraging Design HierarchyFull Hierarchical Extraction

4. Close all windows.

Leveraging Design HierarchyHybrid Hierarchical Extraction


Exercise 4: Hybrid Hierarchical ExtractionThe goal of this exercise is to practice constructing a hierarchical netlist with a sub-circuit as a primitive element. Let's pretend design engineering wants to use a behavioral model of the sub-circuit inv_x2; this behavioral model will be supplied to the simulation engine at simulation time. Our job is to extract parasitic elements for the remainder of the adder circuit.

1. In a shell window, use any available ASCII editor to open the file xcell.adder_4.

2. At the end of the line of inv_x2 sub-circuit, add a blank space and the -p flag, which instructs Calibre to treat the cell as a primitive.

3. Save the xcell.adder_4 file.

4. Close the ASCII editor.

5. In the Calibre Interactive - PEX window, load the runset named runset.RCC.hier_P.

6. Click the Outputs button.

Q. What extraction type is selected?

_____________________________________________________________

7. Run PEX.

8. When the window containing adder_4.RCC.hier_P opens after a successful Calibre xRC run, answer the following questions:

Q. Is there a subckt named inv_x2? ___________________________________

_____________________________________________________________

Q. Where is inv_x2 found and how is it used (as a subckt or as a primitive element)?

_____________________________________________________________

Q. In UNIX, can you find a pxi file for inv_x2 for the hybrid extraction? _____

_____________________________________________________________

9. Close all windows to conclude this lab.


Leveraging Design HierarchyHybrid Hierarchical Extraction


Lab 5Generating Extracted Netlists

IntroductionThe PDB is a database containing all the parasitics extracted during stage 2 of the PEX process. Putting this data in a useful format involves generating netlists that reflect these parasitics. The primary goals of this lab are:

• Provide experience extracting only selected nets.

• Show how you can take advantage of the flexibility provided by the three step PEX process to produce the types of extracted netlist you require.

• Illustrate how the data available for inclusion in the extracted netlist depend on the data that was extracted in Stage 2.


Generating Extracted NetlistsExtracting Selected Nets

Exercise 1: Extracting Selected Nets In this exercise, you will run two extractions. The first is a standard gate-level extraction. The second is a gate-level extraction of only the supply nets. After extraction, you'll compare the resulting netlists.


2. Invoke Calibre Interactive - PEX and load the runset runset.RCC.gate from the lab5 directory.

3. Review the Inputs and Outputs panes and notice that the tool is configured for a standard gate-level RCC run. Netlist format is ELDO.

4. Click Run PEX.

At the successful completion of the Calibre xRC run, Calibre RVE opens, displaying the results of extraction.

Q. How many nets are displayed?

____________________________________________________________

5. Close Calibre RVE. Do not close the Calibre Interactive - PEX or UNIX shell windows.

6. In the Calibre Interactive - PEX, in the Transcript pane, scroll up to the top of the transcript.

Q. What switches were used in the Calibre -xrc invocation for stage 2? _______

_____________________________________________________________


_____________________________________________________________

7. Click the Outputs button, then click the Nets tab.

8. Click Specified Nets. Notice that the Top-Level Nets tab becomes active.

Generating Extracted NetlistsExtracting Selected Nets


9. Deselect Exclude.

10. Select Include:

a. Assuming you only want to extract parasitics for the supply nets, what net names would you enter here?

_____________________________________________________________

(Hint: The PEX Netlist File window should still be open.)

11. Enter the names of the supply nets in the Include field.

12. Still in the Outputs pane, click the SVDB tab and edit the SVDB Directory to read “svdb_selectNets”.

13. Click the Netlist tab and change the name of the netlist File to “adder_4.gate.selectNets”.

14. Click Run PEX.


Q. How many nets are displayed this time?

_____________________________________________________________

15. Close Calibre RVE. In the Calibre Interactive - PEX, in the Transcript pane, scroll up to the top of the transcript.


_____________________________________________________________


_____________________________________________________________

16. Close the Pex Netlist File windows. Do not close the Calibre Interactive - PEX or shell windows.


Generating Extracted NetlistsGenerating Layout Based Netlists

Exercise 2: Generating Layout Based NetlistsIn this exercise, you will run PEX to generate two ELDO netlists: one with names reflecting the names in the layout, the other with names reflecting the names in the schematic.

1. Load the runset runset.layoutNetlist.

2. Click the Outputs button and make sure the settings are as follows:

3. Click Run PEX.


4. In the Transcript pane in Calibre Interactive - PEX, scroll up to the top of the transcript.

Q. What switches were used in the Calibre invocation for stage 1?___________

_____________________________________________________________

5. Compare the parasitics displayed in Calibre RVE with the netlist in the SourceNames.netlist window.

Q. What do you notice about the net names you see in the netlist? ___________

_____________________________________________________________

6. From the Calibre Interactive -PEX GUI menu, choose File > Control File > View.

The control file is the rule file generated by Calibre Interactive to translate the information you entered in the GUI into SVRF statements and operations. This rule file takes precedence over the rule file listed in the Rules pane.

Q. What options were used in the PEX NETLIST command?_______________

_____________________________________________________________

Q. What PEX EXTRACT command was used?__________________________

Tab Field Value

Netlist Format ELDO

Netlist Use Names From SCHEMATIC

Netlist File SourcetNames.netlist

Netlist View netlist after PEX finishes selected

Nets Specified Nets select

Nets Exclude gnd! vdd!

SVDB SVDB Directory SourceNames_svdb

SVDB Start RVE after PEX selected



_____________________________________________________________

7. Close the control file.

8. In the Transcript pane for Calibre Interactive - PEX, scroll up to the top of the transcript.


_____________________________________________________________

9. Exit Calibre RVE but leave all other windows open.

10. In the Calibre Interactive - PEX main window, click the Outputs button and edit the settings to match those in the table below

11. From the Calibre Interactive -PEX GUI menu, choose File > Control File > View.

Q. What options are shown for the PEX NETLIST command?______________

_____________________________________________________________

Q. How do you explain this? ________________________________________

_____________________________________________________________

12. Close the control file.

13. Click Run PEX.

14. In the Transcript pane of the Calibre Interactive - PEX, scroll up to the top of the transcript.


_____________________________________________________________

Q. What difference does it make whether the phdb was created by LVS or this method? ______________________________________________________

Tab Field Value

Netlist Format ELDO

Netlist Use Names From LAYOUT

Netlist File LayoutNames.netlist

Netlist View netlist after PEX finishes

selected

Nets Specified Nets selected

Nets Exclude gnd! vdd!

SVDB SVDB Directory LayoutNames_svdb

SVDB Start RVE after PEX selected



_____________________________________________________________

15. Without closing any windows, open a second shell window and navigate to the directory $MGC_LAB/lab5.

16. Invoke Calibre RVE.

calibre -rve

17. In the Open Calibre Database dialog box, make sure Database Type is set to PEX, and navigate to the database SourceNames_svdb to open it

This second RVE window displays the LVS results from the previous run. Arrange the two RVE windows so you can see both at the same time.

18. Compare the two sets of net parasitics.

Q. What differences do you notice? ___________________________________

_____________________________________________________________

Q. What similarities do you notice? ___________________________________

_____________________________________________________________

19. In the first RVE window, double-click on the row for a net of your choice to display the detailed parasitics for that net.

20. In the second RVE window double-click on the row for that same net.

Q. What do you notice? ____________________________________________

_____________________________________________________________

21. Exit both Calibre RVE sessions. Leave Calibre Interactive and both netlists open.

Generating Extracted NetlistsGenerating a Source-Based Netlist


Exercise 3: Generating a Source-Based Netlist In this exercise, you will generate a source-based netlist.

1. In Calibre Interactive PEX graphical user interface, load the runset runset.SourceNetlist.

2. In the Calibre Interactive - PEX main window, click the Outputs button and verify that the settings match those in the table below

3. Click Run PEX.

4. Upon completion of the run, compare SourceNames.netlist with SourceNames.netlist_SB.

Q. What differences do you see? _____________________________________

_____________________________________________________________

5. Close all Calibre windows.

6. In either of the shell windows, invoke Calibre DESIGNrev and load the layout:

calibredrv -m adder_4.gds

7. Review the cell names shown in the Cells pane on the left of the window.

Q. What does this tell you about the two netlists you compared in step 6? _____

_____________________________________________________________

8. Exit Calibre DESIGNrev to conclude this exercise and lab.

Tab Field Value

Netlist User Names From SOURCEBASED

Netlist File SourceNames.netlist_SB

SVDB SVDB Directory SourceNames_SB_svdb


Generating Extracted NetlistsGenerating a Source-Based Netlist


Lab 6Reduction Techniques

The primary goal of this portion of the lab is to show parasitic reduction and its minimal impact on accuracy. In this lab, you will run AC simulations of an Op-Amp circuit, configured as a low pass filter. The SPICE simulator of choice is ELDO®, a tool by Mentor Graphics. The frequency response of the Op-Amp will be displayed in EZwave™.

Below is diagram of the Op-Amp in a low pass filter configuration, followed by the schematic of the internal intentional component of the Op-Amp.


Reduction Techniques

The layout of the Op-Amp is available. You can load this GDS of this Op-Amp into Calibre DESIGNrev, using the calbrdrv.layerprops to set the appearances of the layers. You can also invoke Caliber Interactive - PEX from DESIGNrev if you so choose.

Your job is to first run simulation with the ideal circuit, then extract parasitic elements from the layout of the Op-Amp and rerun simulation to see their impact on the performance of the Op-Amp. The next part of this lab is to run Calibre xRC with TICER, then rerun simulation and compare its result with the previous two. Because a small circuit is used in this lab, the benefits of reductions will not be fully visible.

Eldo run scripts are available to facilitate simulation invocations, executions, and to display results.

Reduction TechniquesSimulation for the Ideal Case


Exercise 1: Simulation for the Ideal CaseIn this exercise, you will run an ELDO simulation of the Op-Amp circuit in its ideal state. The results of this simulation will serve as basis for subsequent comparison with other simulations when parasitic elements are added to the Op-Amp.


2. Execute the ELDO_sim.ideal script

./ELDO_sim.ideal

At the end of the ELDO simulation, the EZwave window opens with the ELDO.test_opamp.ideal.wdb wave database loaded.

3. Click the + sign to the left of the database name ELDO.test_opamp.ideal.wdb.

4. Click AC to list the frequency response curves in this database.


Reduction TechniquesSimulation for the Ideal Case

5. In the bottom left-hand panel of the EZwave window, right click VDB(OP) and choose Plot.

The plot showing the frequency response of the ideal Op-Amp of your simulation should look like the one below:

Q. What is the largest magnitude shown?

_____________________________________________________________

Q. At what point does the magnitude start to drop off?

_____________________________________________________________

6. In the EZwave window, choose File > Exit.

You now know the performance of the Op-Amp the circuit designer is looking for.

Reduction TechniquesSimulation With RCC Parasitic Elements


Exercise 2: Simulation With RCC Parasitic ElementsFor this exercise, you will use Calibre xRC to extract RCC parasitic elements and build an ELDO netlist for simulation. You will run an ELDO simulation and compare its result with the one from the ideal case.

A runset file is available for use with Calibre xRC. It sets the GUI to produce an RCC netlist with a specific name so the script to run ELDO can pick it up and use.

1. Invoke the Calibre Interactive - PEX and load runset.RCC. Feel free to explore the settings of this window.

Q. What is the name of the output netlist the run will produce? _____________

_____________________________________________________________

2. Run PEX.

You will see a few warnings, which you can ignore. If you see any errors, contact the instructor. At the end of the successful Calibre xRC run, look through the output netlist.

3. Exit Calibre Interactive.

4. In the UNIX shell window, execute the ELDO_sim.RCC script.

./ELDO_sim.RCC

The script runs ELDO on your new netlist, then opens 2 wave databases - one from the current simulation, the other from the previous exercise. In the steps that follow you will compare these two wave databases.

5. From the RCC wave database, plot the VDB(OP) curve as you did in the previous exercise.

a. Click the + sign to the left of the database named ELDO.test_opamp.RCC.wdb.

b. Click AC to list the simulation curves in this database.

c. In the list of curves, right click VDB(OP) and choose Plot.

6. Overlay the VDB(OP) plot for the ideal wave database on top of this one:

a. Click the + sign to the left of the database named ELDO.test_opamp.ideal.wdb.

b. Click AC to list the simulation curves in this database.

c. From the list of curves, click and drag the VDB(OP) of the ideal case and drop it in the same plot panel as the VDB(OP) of the RCC simulation.



This action puts the 2 frequency response curves in the same plot for ease of comparison. The right-hand side of the plot area shows the color legend of the plot. The frequency responses of the 2 simulations ought to look like the plot below:

Q. What can you conclude from looking at these 2 curves? ________________

_____________________________________________________________

_____________________________________________________________

Q. If the Op-Amp were released to wafer fabrication, will it work as a low-pass filter?

_____________________________________________________________

_____________________________________________________________

7. Close the EZwave window when done.

The steps below are optional.



8. If desired, open the GDS of the Op-Amp in Calibre DESIGNrev from the beginning of this lab or this exercise.

calibredrv -m opamp.gds

9. Start RVE (Verification > Start RVE), select the database type PEX, and open the database svdb.

10. Using knowledge gained from previous labs and exercises highlight various parasitic elements of the Op-Amp layout.

11. Close RVE when done.


Reduction TechniquesTICER Reduction

Exercise 3: TICER Reduction In this exercise, you will apply TICER reduction technique to parasitic extraction. Using the output netlist from this Calibre xRC run, you will launch an ELDO simulation, plot the resulting frequency response and compare it to the previous ones.

1. Launch Calibre Interactive - PEX and load the runset runset.TICER.

2. Examine the different switches and fields of the GUI, especially the TICER field on the Reduction and CC tab of the PEX Options pane.

Q. What is the frequency for the TICER reduction set to?__________________

_____________________________________________________________

3. Run PEX.

4. Once Calibre xRC run completes, exit Calibre Interactive.

5. Run the ELDO simulation with the TICER netlist, using the ELDO_sim.TICER script.

./ELDO_sim.TICER

This script opens 3 wave databases - one from the current simulation and the ones from the previous exercises.

6. When ELDO completes successfully and opens the EZwave viewer, use the skills learned from the previous exercises to display the VDB(OP) frequency response curves from all 3 wave databases in the same plot.

Q. Record your observation below:

_____________________________________________________________

_____________________________________________________________

7. In the plot window, use your cursor to zoom into the bottom right portion of the RCC and TICER curves to see the differences between the two.

a. Draw a zoom window by pressing and holding the left mouse button as you dragging to draw box over the combined RCC/TICER plot.

b. Repeat as needed until you are zoomed in close enough to see two distinct curves.

c. If you “lose” the curve by zooming, use click the Zoom All or Undo Most Recent Zoom buttons in the toolbar and start over, or use the following settings to orient the view to one of many reasonable views:

o y axis values between -37.6 and -37.4.

o x axis values between 1.2 and 1.3 meg.



When zoomed sufficiently, the view will look something like this:

Q. From you plot, what conclusion can you draw about the difference between RCC and TICER? ___________________________________________________

_____________________________________________________________

_____________________________________________________________

If time permits, explore the plot using the skills learned so far.

8. Close the EZwave window, when done. This concludes this lab.




Lab 7Extraction in Your Design Flow

IntroductionThe goal of this lab is to provide you with an opportunity to apply your knowledge of the parasitic extraction process to actual designs. After completing the lab, the class will come together as a whole to discuss their recommended strategies and explore other approaches.

For each design presented, write down what you believe is the best approach for parasitic extraction. Be prepared to justify your answers!


Extraction in Your Design FlowDesign 1

Exercise 1: Design 1

1. Type of design:________________________________________________

2. Type of parasitic extraction recommended:

____________________________________________________________

3. Reason for this recommendation:

____________________________________________________________

____________________________________________________________




1. Type of design:________________________________________________


____________________________________________________________


____________________________________________________________

____________________________________________________________




1. Type of design:________________________________________________


____________________________________________________________


____________________________________________________________

____________________________________________________________




1. Type of design:________________________________________________


____________________________________________________________


____________________________________________________________

____________________________________________________________




Lab 8Working With PEX Rule Files

IntroductionThe primary goal of this lab is to acquaint you with some of the more common modifications you may be asked to make to foundry-supplied rule files.


Working With PEX Rule FilesMapping Layer Names

Exercise 1: Mapping Layer Names In this exercise, you will apply compare the LVS rules to the PEX rules and correct any discrepancies you find in the layer names.

1. Change directories to $MGC_LAB/lab8/LayerNames.

2. Invoke the Calibre Interactive - PEX GUI and load the runset layerNames.runset.

3. Use File > View Text File to open cap.rules.

4. Scan through the file.

Q. What do encrypted rules look like? _________________________________

_____________________________________________________________

_____________________________________________________________

5. Up near the top of the file, find the LAYER INFORMATION section.

6. Open a second text file window and view lvs.rule.

7. Scroll down to the CONNECT statements.

8. Study the layer information in the two files.

Q. Which PEX layer names do not match the LVS layer names.

PEX (cap.rules) layer name : LVS (lvs.rule) layer name

• ________________________________

• ________________________________

• ________________________________

• ________________________________

(Hint: Look only at the six layers in the cap.rules file described as needing to be in the Capacitance Order statement.)

Explanation: In order for the two rule files to work together, the names must match. Since they do not match, you must resolve the problem before running extraction.

o You cannot edit the SVRF layer statements in the cap.rules file because they are encrypted.

o You could change the names in the LVS rule file, but that is risky, and is not recommended.

Q. What method should you use to resolve this problem? (Hint: Refer to the slides for Module 11.) ___________________________________________________

_____________________________________________________________

Working With PEX Rule FilesMapping Layer Names


9. Find the rule file that contains the CAPACITANCE ORDER statement, and open it.

Q. What is it?

_____________________________________________________________

Since you will need to modify the CAPACITANCE ORDER statement, this rule file is a logical place to add the PEX ALIAS statements, along with other statements required.

10. Following the steps described in slides 8-10 through 8-12, correct the problem in this rule file.

Q. What statements did you add to your rule file? ________________________

_____________________________________________________________

_____________________________________________________________

_____________________________________________________________

_____________________________________________________________

_____________________________________________________________

_____________________________________________________________

_____________________________________________________________

_____________________________________________________________

_____________________________________________________________

_____________________________________________________________

_____________________________________________________________

_____________________________________________________________

Q. What changes do you need to make to the CAPACITANCE ORDER statement?

_____________________________________________________________

11. In the Rules pane, click Load to load the user.rule. If this file loads with errors, you know you have supplied the correct syntax. If you receive any errors, fix them now.

12. Exit Calibre Interactive - PEX.


Working With PEX Rule FilesExploring Device Interconnect Boundaries

Exercise 2: Exploring Device Interconnect Boundaries In this exercise, you will create a pseudo-device that you will use in exercise 9-3 as you explore device/interconnect boundaries.

1. Change directories to $MGC_LAB/lab8/Boundaries.

2. Invoke Calibre DESIGNrev and load the design adder_4.gds.

3. In the cells hierarchy, expand the cell one_bit, then click on inv_x1.

In this exercise you will be running extraction on a single cell. This will allow you to focus on the low level devices.

4. From the menu, invoke Calibre Interactive: Verification > Run PEX.

5. Load the runset runset.invA.

6. Notice that the Inputs button is red, indicating that something is not set properly. Review the contents of each tab.

Q. Which fields contain red pathnames? _______________________________

_____________________________________________________________

Q. Why:_________________________________________________________

_____________________________________________________________

____________________________________________________________

Explanation: When you invoke Calibre Interactive from a layout viewer, it pre-populates the inputs to match the current cell in the layout viewer. Because the current cell is not the top-level, the name it used for the source netlist is incorrect.

7. Change the name of the source netlist to adder_4.sp.

Also notice that the Top Cell field on the Layout tab displays name of the lower level cell, not the top cell. The top-level cell for extraction can be any cell in a layout. Any hierarchical extractions are relative to the top-level for extraction, not the top-level for the layout. In this case, the cell inv_x1 is to be the top-level for extraction.

8. Click Run PEX.

Ignore any warnings that result from this lower-level cell not containing any top-level ports.



9. In the inv_x1 table of nets displayed in the Calibre - RVE window, double-click on net A to display the detailed parasitics for this net.



10. Click on blue box to the right of the CC to highlight these coupling capacitors in Calibre DESIGNrev.

Tip: If the text is too large, adjust the text size in Calibre DESIGNrev by choosing Options > Objects, then in the Text area, select Height Fixed (no text attributes), and click Apply.

This cell is a single device. For the purposes of this lab, you will create two pseudo-devices by drawing a marker polygon that will identify the device extents. In the next few steps you will create a device marker layer and draw markers indicating device boundaries.



11. First, create a new layer, layer 50, named dev_marker:

12. In Calibre RVE, click the eraser icon to clear all highlights.

a. In Calibre DESIGNrev, right click in the layer pane and choose Add off the pop-up menu.

b. In the Add Layers dialog box, set Number to 50 and Layer name to dev_marker, then click OK.

The tool adds the new layer to the layer pane.

13. In the toolbar, click Z-All to display the entire cell.

The image below shows the two pseudo devices. Note the capacitance between MT1 and PO1 reported inside the pseudo devices. The goal will be to extract all capacitance between MT1 and PO1 except within the pseudo devices.



14. In the layer pallet, click on layer 50 to select it, then click the Box icon in the toolbar to enable draw mode.

15. Draw a rectangle around the top pseudo-device, forming a device boundary.

16. Draw a rectangle around the bottom pseudo-device, forming a second device boundary.

17. The cell should now look as follows:

18. Leave all the applications open for the next exercise.

Working With PEX Rule FilesAdjusting Extraction Within the Device


Exercise 3: Adjusting Extraction Within the Device You will now use the device boundary created in exercise 8-2 as a marker layer for extraction. This will allow you to use the PEX Ignore statement to control exactly which parasitics you extract relative to devices. You will begin by finding the device layers, then use PEX IGNORE CAPACITANCE to control whether or not parasitics within the device are extracted.

1. Review the slides for Module 8 to answer the following questions:

Q. What PEX IGNORE statement must you use to instruct Calibre to not extract any capacitance inside a device?

_____________________________________________________________

Q. What layers must you use with this statement?

_____________________________________________________________

Q. Assuming that the device is comprised of PO1 and MT1 geometries, what statement must you add to the rule file to instruct the tool to ignore capacitance inside these two devices?___________________________________________________

_____________________________________________________________

Resources available to you for this task include: the design itself, data available through Calibre RVE, documentation available through the Help menu item, the LVS rule file, and Module 8.Remember, the name of the marker layer is dev_marker.

2. In the Rules pane of the Calibre Interactive - PEX GUI, click View to open user.rule.

3. Click Edit to enable editing.

4. Scroll down to the end of the file and add a new LAYER statement instructing Calibre to load in layer 50.

5. In the file editor, save the modified rules file: File > Save (needed).

6. In Calibre Interactive, click the Load button on the Rules pane. If the code you wrote contains any syntactical errors, the tool displays them for you now. Fix any errors you see before continuing.

7. Click Run PEX.

8. When prompted, click OK in the Overwrite file dialog box.



9. After the run completes successfully, use Calibre RVE to highlight the coupling for Net A.

Notice that capacitance within our pseudo-device is no longer extracted.

10. Close all windows and celebrate successfully completing this course!




Answer Key

Lab 1Extraction Basics Quiz

Q. 1. Name four or more factors you should consider when choosing a parasitic extraction strategy.• Target tool• Workflow• Process node• Foundry• Design type• CAD tools (design environment)• Analysis needs

Q. 2. List four or more terms that can have different meanings depending on the context within the physical verification flow.• Flow• Backannotation• Pins• Ports• Model• Runset• Extraction

Q. 3. What is the goal of parasitic extraction?Identify and characterize parasitic devices within a layout so youcan simulate the behavior of the circuit as drawn.

Q. 4. List three types of analysis that require extraction. • IR Drop• RC Delay• Coupling/Noise

Q. 5. What are the inputs for extraction?• Layout• Circuit netlist (optional)

Q. 6. What are the two basic types of extracted netlists?• Layout-Based• Source-Based

Q. 7. List three or more prerequisites for performing extraction with Calibre xRC.• Layout is DRC and LVS clean.


• You have a process profile and calibrated rules.• You know the simulator you will use for post-layout simulation.• You have specifications for the library of device models used for simulation.• You have the proper Calibre licenses.

Q. 8. What portions of a layout are extracted?Nets on interconnect layers, up to the boundary of the intentional devices,as defined by the user.

Q. 9. Which of the following is not a type of parasitic network available from Calibre xRC:• CC

Lab 2Calibre xRC Basics

Exercise 1: Creating a PEX Runset

Q. What color is the Rules button now?Green

Q. What color is the Inputs button now?Red

Q. Why?More information is required on the other tabs.

Exercise 2: Running Calibre xRC

Q. What does the first line in the log.xrc tell you?The path to MGC_HOME

Q. Identify the 3 command lines necessary to produce a netlist with extracted parasitic ele-ments: (Hint: They all begin with $MGC_HOME/bin/calibre.)• calibre -lvs -hier…• calibre-xrc -pdb -rcc…• calibre -xrc -fmt -all …

Q. Which rule file do these commands use?_pex.rule_

Exercise 3: Displaying the 3-Stages in the GUI

Exercise 4: Getting Help

Q. What is the tool tip for this Files field?“Type in the paths to the netlist files, one path per line.”

Q. What interesting piece of information did you learn about this field from the Tool Tip?That there can be multiple netlist files.

Q. What is the tool tip for the Browse button?


“Click to browse for netlist files.”

Lab 3Running Calibre xRC

Exercise 1: Extracting Parasitic Resistors Only

Q. How many subckt statements are there in this netlist?One(Hint: In the PEX Netlist File window, choose Options > Search to look for “subckt.”)

Q. How many files are referenced by this netlist?Two

Q. What does this file contain?The parasitic devices in adder_4

Q. Are there any parasitic element other than resistors?No

Exercise 2: Extracting Parasitic Capacitors Only

Q. What is the name of the file to which the net summary report will be written?pex_rep_sumry.C

Q. What type of information do you see?Net-by-net summary of parasitics.

Q. What types of parasitic effects are represented?Capacitance to ground and coupling capacitance.

Q. What is its total parasitic capacitance?3.87e-12

Q. What is its total coupled capacitance of net INB13?2.40e-12

Exercise 3: Extracting All Parasitic Capacitors and Resistors

Q. What netlist files are INCLUDEd in this one?adder_4.hspice.RCC .pex and adder_4.hspice.RCC.pxi

Q. How man files are required to fully represent the netlist?3

Q. Why?HSPICE was designed specifically to represent hierarchical netlists.It uses separated files for the topcell, the parasitic network, and eachsubcircuit.

Exercise 4: Inspecting Parasitics


Q. What type of information do you see?Net-by-net summary of parasitics.

Q. What information can you find in the adder_4 table of nets but not in pex_rep_sumry.RCC?Number of resistors

Q. What information can you find in pex_rep_sumry.RCC but not in the adder_4 table of nets?The ratio of coupling capacitance to total capacitance.

Q. How do you explain the differences between C Total (F) in the adder_4 table of nets and TotalC in the pex_rep_sumry.RCC?C Total (F) in the adder_4 table of nets reports the total capacitance to ground..TotalC in the pex_rep_sumry.RCC reports the capacitance to groundplus coupling capacitance.

Q. How does coupling capacitance to vdd! differ from the total coupling capacitance?It is smaller.

Q. What information was added to the CC Total (F) column in the table of nets?Percentages.

Q. What do they represent?The fraction/percentage of the total coupling capacitance for the net thatcomes from coupling to the power net.

Q. What kind of information can you find in the Info tab?Layers, instances, and devices

Q. Is this where you would look to see the parasitics for the net?No. It only shows intentional devices.

Q. What types of information do you think you will find in this tab?Parasitic devices

Q. What happened?All the parasitic resistors are highlighted in the layout viewer.

Q. What do you think you could do if you wanted to highlight only the resistors on a specific layer?Click the “+” next to the R, then click the blue box to the leftof a layer name.

Q. One of the blue boxes containing an R does not highlight anything. Which one is it?The one to the left of the words “Pt-to-Pet Res.”

Q. What does it do?Changes the contents of the right side of the tab.

Q. What happens?


The tool prompts you to draw a rectangle in the layout viewer.After drawing the rectangle, the tool highlights parasitic devicesin that area.

Q. How many resistance values does the tool calculate?5

Q. Where is the most resistance?Between X0/M7 g and X0/X10/M1 g.

Lab 4Leveraging Design Hierarchy

Exercise 1: Flat Transistor-Level Extraction

Q. How many subckts are there in this output netlist?one

Q. What are the primitive devices shown in this main output netlist?N-MOS devices…. MP0, MP1, MN0, MN1

Q. Is this transistor-level netlist flat or hierarchical?Flat

Q. How many other files are 'included' in this output netlist?Two

Q. Why does it take three files to represent this flat netlist?Because this is the HSPICE format.

Q. How many lines are there in this file?About 300

Exercise 2: Gate-Level Extraction

Q. What is the name of the h-cell file?hcell.adder_4

Q. What is the name of the x-cell file?xcell.adder_4

Q. How many cells are in this file?six

Q. How many subckts are there in the output netlist adder_4.RCC.gate?one

Q. What are the primitive devices shown in this main output netlist?Cell instances (for example, INB0(2)_X0_B0)

Q. How many other files are 'included' in this output netlist?Two


Q. Is this gate-level netlist flat or hierarchical?Hierarchical

Q. How many lines are there in this file?About 40

Q. Enter the file sizes for each of the files listed below:• adder_4.RCC.transistor__17781• adder_4.RCC.transistor.pex__42598• adder_4.RCC.transistor.adder_4.pxi__99381• adder_4.RCC.gate__1297• adder_4.RCC.gate.pex__2872• adder_4.RCC.gate.adder_4.pxi__2564

Q. What kind of information does this file contain?One subcircuit for each parasitic network

Q. How many subcircuits does it contain?18

Q. What do you notice about the subcircuits in this file?Most are pretty small (contain few resistors and capacitors)

Q. How many subcircuits does it contain?50

Q. What do you notice about the subcircuits in this file?Most are larger than those in the gate-level netlist

Q. What kind of information does this file contain?One parasitic network for each net.

Q. How many lines does it contain?52

Q. What do you notice about the nets in this file?There are not a lot of them andThey are written in terms of cell instances

Q. How many lines does it contain?About 1700

Q. What do you notice about the nets in this file?There are lots, both top level and lower level.They are written in terms of other nets and pin/ports

Q. Why are the files adder_4.RCC.gate.* smaller than their transistor-level equivalents?Each cell is represented only once in the gate files.

Exercise 3: Full Hierarchical Extraction


Q. What extraction type is selected?R+C+CC

Q. How many 'subckt' are there in adder_4.RCC.hier_full?7

Q. Why is this number higher than then number of cells in xcell.adder_4?Because there is one subckt for the top-level and one for each cell.

Q. What type of element is instantiated within the primary subckt?A cell

Q. What is its name?one_bit.

Q. What types of elements are instantiated within the other subckts?N-Mos and P-MOS devices plus instance calls to other cells.

Q. What are the sizes of the netlist files?adder_4.RCC.transistor_17781adder_4.RCC.gate_1297adder_4.RCC.hier_full_4123

Q. How many pxi files are there for the each of these extractions?adder_4.RCC.transistor_1adder_4.RCC.gate_1adder_4.RCC.hier_full_7

Exercise 4: Hybrid Hierarchical Extraction

Q. What extraction type is selected?Hierarchical R + C + CC

Q. Is there a subckt named inv_x2?no

Q. Where is inv_x2 found and how is it used (as a subckt or as a primitive element)?It is a primitive element in the one_bit subckt.

Q. In UNIX, can you find a pxi file for inv_x2 for the hybrid extraction?No

Lab 5Generating Extracted Netlists

Exercise 1: Extracting Selected Nets

Q. How many nets are displayed?18____________________________________________________________

Q. What switches were used in the Calibre -xrc invocation for stage 2?


-xrc -pdb -rcc -turbo 1 -xcell

Q. What switches were used in the Calibre -xrc invocation for stage 3?-xrc -fmt -all -xcellvdd! gnd!

Q. How many nets are displayed this time?2_

Q. What switches were used in the Calibre -xrc invocation for stage 2?-xrc -pdb -rcd -turbo 1 -xcell <xcell file> -select

Q. What switches were used in the Calibre -xrc invocation for stage 3?-xrc -fmt -all -xcell

Exercise 2: Generating Layout Based Netlists

Q. What switches were used in the Calibre invocation for stage 1?-lvs -hier -hcell

Q. What do you notice about the net names you see in the netlist?Net names match the names in the schematic.

Q. What options were used in the PEX NETLIST command?PEX NETLIST “SourceNames.netlist” ELDO 1 SOURCENAMES

Q. What PEX EXTRACT command was used?PEX EXTRACT EXCLUDE SOURCENAMES TOPLEVEL “gnd! vdd!”

Q. What switches were used in the Calibre invocation for stage 1?-lvs -hier -hcell.....

Q. What options are shown for the PEX NETLIST command?PEX NETLIST “LayoutNames.netlist” ELDO 1 LAYOUTNAMES

Q. How do you explain this?The control file reflects the current GUI settings.

Q. What switches were used in the Calibre invocation for stage 1?-xrc -phdb -hcell

Q. What difference does it make whether the phdb was created by LVS or this method?When it is created this way, there is no cross reference data.

Q. What differences do you notice?No column for Source Nets in the Layout Names version.

Q. What similarities do you notice?Values are the same. Layout Net names are the same.

Q. What do you notice?


In the Layout Names version, there is still no source net names.

Exercise 3: Generating a Source-Based Netlist

Q. What differences do you see?The layout-based netlist shows the cell “single_bit” and the source-based netlist shows the cell “one_bit”.

Q. What does this tell you about the two netlists you compared in step 6?The source-based netlist reflects the schematic hierarchy.

Lab 6Reduction Techniques

Exercise 1: Simulation for the Ideal Case

Q. What is the largest magnitude shown?Almost 60 dB

Q. At what point does the magnitude start to drop off?About 1.0K Hz

Exercise 2: Simulation With RCC Parasitic Elements

Q. What is the name of the output netlist the run will produce?opamp.RCC

Q. What can you conclude from looking at these 2 curves?The curve for the RCC simulation drops off a little sooner butbasically follows the ideal curve.

Q. If the Op-Amp were released to wafer fabrication, will it work as a low-pass filter?Yes, this Op-Amp will work as a low-pass filter.

Exercise 3: TICER Reduction

Q. What is the frequency for the TICER reduction set to?100e6

Q. Record your observation below:At this resolution, there is no obvious difference between the TICER and RCCfrequency response curves.

Q. From you plot, what conclusion can you draw about the difference between RCC and TICER?The difference between RCC and TICER is very small. TICERshould be used whenever possible.

Lab 7


Extraction in Your Design Flow





Lab 8Working With PEX Rule Files

Exercise 1: Mapping Layer Names

Q. What do encrypted rules look like?A bunch of random letters, numbers,and other characters.

Q. Which PEX layer names do not match the LVS layer names.PEX (cap.rules) layer name : LVS (lvs.rule) layer name• m1 MT1• m2 MT2• m3 MT3• p1 PO1

Q. What method should you use to resolve this problem? (Hint: Refer to the slides for Mod-ule 11.)PEX ALIAS

Q. What is it?user.rule

Q. What statements did you add to your rule file?LAYER pl 1000CONNECT plPEX ALIAS pl PO1LAYER m1 1001CONNECT m1PEX ALIAS m1 MT1LAYER m2 1002CONNECT m2PEX ALIAS m2 MT2LAYER m3 1003CONNECT m3PEX ALIAS m3 MT3

Q. What changes do you need to make to the CAPACITANCE ORDER statement?CAP ORDER p1 m1 m2 m3 ........


Exercise 2: Exploring Device Interconnect Boundaries

Q. Which fields contain red pathnames?In the Netlist tab, the Files: field is red.

Q. Why:The name in the file is based on the current cell,which is inv_x1. That netlist does not exist.

Exercise 3: Adjusting Extraction Within the Device

Q. What PEX IGNORE statement must you use to instruct Calibre to not extract any capac-itance inside a device?PEX IGNORE CAPACITANCE DEVICE

Q. What layers must you use with this statement?The layers used to create the device and the device layer itself.

Q. Assuming that the device is comprised of PO1 and MT1 geometries, what statement must you add to the rule file to instruct the tool to ignore capacitance inside these two devices?PEX IGNORE CAPACITANCE DEVICE PO1 MT1 dev_marker


NOTES:


Part Number: 071781

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