XilinxSpartan3DevelopmentKit User'SGuide

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    users guide

    XilinxSpartan-3Development Kit

    Copyright 2004 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. AVNET AVENUE and AVNET AVENUE & Design are trademarks of Avnet, Inc. All other trademarks are property of theirrespective owners.

    Avnet Design Services 1 of 41 Rev 1.0 12/10/2004Released Literature # ADS-005104

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    Table of Contents

    1.0 Introduction..................................................................................................................................................................................... 41.1 Description.................................................................................................................................................................................. 4

    1.2 Features........................................................................................................................................................................................41.3 Demo Applications....................................................................................................................................................................51.4 Ordering Information: .............................................................................................................................................................. 5

    2.0 Hardware.......................................................................................................................................................................................... 72.1 Spartan-3 FPGA......................................................................................................................................................................... 72.2 Configuration.............................................................................................................................................................................. 82.3 Jumper Settings ........................................................................................................................................................................132.4 Clocks.........................................................................................................................................................................................172.5 On Board Displays (2x20 LCD & 128x64 OLED)............................................................................................................182.6 VGA (DB15 & Video DAC) .................................................................................................................................................212.7 Audio Codec .............................................................................................................................................................................232.8 PS2 Keyboard & Mouse Ports...............................................................................................................................................24

    2.9

    Dip & Push-Button Switches.................................................................................................................................................252.10 LEDs .....................................................................................................................................................................................252.11 Piezo Buzzer.........................................................................................................................................................................262.12 High-speed Serial Communication................................................................................................................................... 262.13 Memory.................................................................................................................................................................................282.14 Communication (RS232, 10/100 Ethernet, USB2.0) ....................................................................................................302.15 I/O Connectors...................................................................................................................................................................352.16 Power .........................................................................................................................................................................................39

    3.0 Software/BSP................................................................................................................................................................................ 403.1 What is included.......................................................................................................................................................................403.2 Hello World ..............................................................................................................................................................................403.3 On-Chip Peripheral Bus (OPB) External Memory Project(s) ..........................................................................................403.4 Web Server................................................................................................................................................................................41

    4.0 List of Partners..............................................................................................................................................................................41

    Copyright 2004 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. AVNET AVENUE and AVNET AVENUE & Design are trademarks of Avnet, Inc. All other trademarks are property of theirrespective owners.

    Avnet Design Services 2 of 41 Rev 1.0 12/10/2004Released Literature # ADS-005104

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    Figures

    Figure 1 - Spartan-3 Dev (Top Side) Figure 2 - Spartan-3 Dev (Bottom Side) ................................................................................5Figure 3 - Spartan-3 Development Board Picture .......................................................................................................................................5Figure 4 - Spartan-3 Development Board Block Diagram......................................................................................................................... 7

    Figure 5 Boundary Scan Mode Selection via JP2 .....................................................................................................................................8Figure 6 - Configuration / Debug Connections Par3 ............................................................................................................................. 9Figure 7 - Configuration / Debug Connections Par IV.......................................................................................................................... 9Figure 8 - JTAG Chain Standalone Mode (Default) .................................................................................................................................10Figure 9 Design Revision BIT SEL Jumpers JP3 ..............................................................................................................................11Figure 10 - Fly Wire Connection J1 .............................................................................................................................................................12Figure 11 - FPGA Configuration Mode Select .......................................................................................................................................... 13Figure 12 - Design Revision Select .............................................................................................................................................................. 13Figure 13 - I/O Voltage Selection Banks 4&5...........................................................................................................................................14Figure 14 - I/O Voltage Selection Banks 1&2...........................................................................................................................................14Figure 15 - I/O Voltage Selection Banks 2&3...........................................................................................................................................15Figure 16 - Default Jumper Placement........................................................................................................................................................16

    Figure 17 - Resistor Jumper Pin-out ............................................................................................................................................................31Figure 18 - Barrel Power Connector "J7" ...................................................................................................................................................39

    Tables

    Table 1: Ordering Information....................................................................................................................................................................... 6Table 2 - Spartan-3 Attributes by Density .................................................................................................................................................... 8Table 3 - JTAG Headers (Par-3 & Par-4) Pin-Out .....................................................................................................................................8Table 4 - JTAG Chain Selection "JP6"...............

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