35
of Sheet Date: Title: Ver: A B C D 1 2 3 4 D C B A 4 3 2 1 Sheet Size: B Rev: Drawn By Disclaimer: THE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS")ARE SUBJECT TO THE AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY OR PROPER OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Linear Regulator 1.8V@500mA max Jack Power Supply 12V Linear Regulator [email protected] max 1.5V@20A max 3.3V@20A max Sink/Source DDR Regulator Power Controller 1 PWR Switching Module Switching Module Switching Module FMC LPC TDO U1 FPGA TDI TSTTDI CFGTDO CFGTDI TSTTDO JTAG Chain TDO System ACE CF 3.3V 2.5V U1 SCHEM, ROHS COMPLIANT FMC LPC Expansion Connector GMII Differential Clock Clock Socket SMA Clock LEDs DIP Switches MODE DIP Switch Push Buttons USB UART SSPI Header EEPROM: External Config Other Devices: Parallel Flash USB JTAG Connector IIC EEPROM and Header SPI X4 or 0b1010010 0bXXXXX10 Spartan-6 XC6SLX45T PCB P/N: 0431534 SCH P/N: 0381305 ART P/N: 1280473 Test P/N: TSS0123 DDR3 TDI BUFFER PCIe Finger SP605 Block Diagram 10/100/1000 Ethernet U4 J2 Page 9 Page 10 Page 11 Page 14 Page 14 Page 14 Page 14 Page 15 Page 18 Page 15 Page 32 Page 12 Page 18 Page 18 Page 19 USB HDR J4 J2 J19 U17 VCCINT@10A max Power Controller 2 0b1010100 Linear Regulator 1.2V @ 3A max VCCAUX@10A max Switching Module 2.5V@10A max Switching Module Linear Regulator 3.0V@500mA max System ACE CF Page 20 0.75V VTT / VREF @ 3A max SFP Module Page 12 SP605 EVALUATION PLATFORM IIC Addressing BF 04 1 35 9-25-2009_10:32 D

Xilinx XTP067 - SP605 Schematics

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Page 1: Xilinx XTP067 - SP605 Schematics

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

Disclaimer:

THE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS")ARE SUBJECT TO THE TERMS

AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT

http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE

OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED

ON THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION

REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS,

OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY OR PROPERTY

OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS

IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. ALL

SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

Linear Regulator1.8V@500mA max

Jack

Power Supply12V

Linear [email protected] max

1.5V@20A max

3.3V@20A max

Sink/Source DDR Regulator

Power Controller 1

PWR

Switching Module

Switching Module

Switching Module

FMC LPC

TDO

U1

FPGA

TDITSTTDI CFGTDO

CFGTDITSTTDO

JTAG Chain

TDO

System ACE CF

3.3V 2.5V

U1

SCHEM, ROHS COMPLIANT

FMC LPC ExpansionConnector GMII

Differential ClockClock SocketSMA Clock

LEDs

DIP Switches

MODE DIP Switch

Push Buttons

USB UART

SSPI Header

EEPROM:

External Config

Other Devices:

Parallel Flash

USB JTAG ConnectorIIC EEPROMand Header

SPI X4 or

0b1010010

0bXXXXX10

Spartan-6

XC6SLX45T

PCB P/N: 0431534SCH P/N: 0381305

ART P/N: 1280473Test P/N: TSS0123

DDR3

TDIBUFFER

PCIe Finger

SP605 Block Diagram

10/100/1000 Ethernet

U4

J2

Page 9Page 10 Page 11

Page 14

Page 14

Page 14

Page 14

Page 15Page 18 Page 15 Page 32

Page 12

Page 18

Page 18

Page 19

USB HDR

J4

J2

J19

U17

VCCINT@10A max

Power Controller 2

0b1010100

Linear Regulator1.2V @ 3A max

VCCAUX@10A maxSwitching Module

2.5V@10A maxSwitching Module

Linear Regulator3.0V@500mA max

System ACE CF

Page 20

0.75V VTT / VREF @ 3A max

SFP Module

Page 12

SP605 EVALUATION PLATFORM

IIC Addressing

BF

04

1 35

9-25-2009_10:32 D

Page 2: Xilinx XTP067 - SP605 Schematics

VCC2V5_FPGA

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

IO_L1P_HSWAPEN_0_C3IO_L1N_VREF_0_D3

IO_L2P_0_D4IO_L2N_0_D5IO_L3P_0_B2IO_L3N_0_A2IO_L4P_0_E5IO_L4N_0_E6IO_L5P_0_B3IO_L5N_0_A3IO_L6P_0_C4IO_L6N_0_A4IO_L7P_0_F7IO_L7N_0_F8IO_L8P_0_C5

IO_L8N_VREF_0_A5IO_L32P_0_G8IO_L32N_0_F9IO_L33P_0_H10IO_L33N_0_H11

IO_L34P_GCLK19_0_G9IO_L34N_GCLK18_0_F10IO_L35P_GCLK17_0_H12IO_L35N_GCLK16_0_G11IO_L36P_GCLK15_0_F14IO_L36N_GCLK14_0_F15IO_L37P_GCLK13_0_E16IO_L37N_GCLK12_0_F16

IO_L38P_0_H13IO_L38N_VREF_0_G13

IO_L49P_0_H14IO_L49N_0_G15IO_L50P_0_C17IO_L50N_0_A17IO_L51P_0_G16IO_L51N_0_F17IO_L62P_0_D18

IO_L62N_VREF_0_D19IO_L63P_SCP7_0_B18IO_L63N_SCP6_0_A18IO_L64P_SCP5_0_C19IO_L64N_SCP4_0_A19IO_L65P_SCP3_0_B20IO_L65N_SCP2_0_A20IO_L66P_SCP1_0_D17IO_L66N_SCP0_0_C18

VCCO_0_B19VCCO_0_B4VCCO_0_E17VCCO_0_F6VCCO_0_G10VCCO_0_G14

6slx45tfg484BANK 0DUT

PCB P/N: 0431534SCH P/N: 0381305

ART P/N: 1280473Test P/N: TSS0123

SCHEM, ROHS COMPLIANTSP605 EVALUATION PLATFORM

FPGA Bank 0

FPGA Bank 0

D

2 35

9-18-2009_15:04

04

BF

C3D3D4D5B2A2E5E6B3A3C4A4F7F8C5A5G8F9H10H11G9F10H12G11F14F15E16F16H13G13H14G15C17A17G16F17D18D19B18A18C19A19B20A20D17C18

B19B4

E17F6

G10G14

U1

10FMC_LA07_N10FMC_LA07_P

10FMC_LA05_P10FMC_LA05_N

FMC_LA02_P 1010FMC_LA02_N

FMC_LA10_P 10FMC_LA10_N 10

10FMC_LA12_P10FMC_LA12_N

FMC_LA11_P 1010FMC_LA11_N

FMC_LA16_P 10FMC_LA16_N 10

10FMC_LA13_P10FMC_LA13_N10FMC_LA15_P10FMC_LA15_N

FMC_LA14_P 10FMC_LA14_N 10

10FMC_LA03_P10FMC_LA03_N

10FMC_LA04_N10FMC_LA04_P

FMC_CLK1_M2C_P 10FMC_CLK1_M2C_N 10

1

2

R125100

1/16W5%

USER_SMA_GPIO_P 13USER_SMA_GPIO_N 13

14GPIO_SWITCH_014GPIO_LED_0

FMC_LA01_CC_P 10FMC_LA01_CC_N 10

21,26PMBUS_ALERTFPGA_HSWAPEN

10FMC_LA00_CC_N10FMC_LA00_CC_P

FMC_CLK0_M2C_P 10FMC_CLK0_M2C_N 10

IIC_SCL_SFP 12IIC_SDA_SFP 12

10FMC_LA08_P10FMC_LA08_N

FMC_LA09_P 10FMC_LA09_N 10

FMC_LA06_P 10FMC_LA06_N 10

Page 3: Xilinx XTP067 - SP605 Schematics

VCC2V5_FPGA

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

IO_L1P_A25_1_F18IO_L1N_A24_VREF_1_F19

IO_L9P_1_H16IO_L9N_1_H17

IO_L10P_1_B21IO_L10N_1_B22IO_L19P_1_J16IO_L19N_1_J17IO_L20P_1_C20IO_L20N_1_C22IO_L21P_1_L15IO_L21N_1_K16IO_L28P_1_D21

IO_L28N_VREF_1_D22IO_L29P_A23_M1A13_1_G19IO_L29N_A22_M1A14_1_F20

IO_L30P_A21_M1RESET_1_H18IO_L30N_A20_M1A11_1_H19IO_L31P_A19_M1CKE_1_F21IO_L31N_A18_M1A12_1_F22IO_L32P_A17_M1A8_1_E20IO_L32N_A16_M1A9_1_E22

IO_L33P_A15_M1A10_1_J19IO_L33N_A14_M1A4_1_H20IO_L34P_A13_M1WE_1_K19

IO_L34N_A12_M1BA2_1_K18IO_L35P_A11_M1A7_1_G20IO_L35N_A10_M1A2_1_G22IO_L36P_A9_M1BA0_1_K17IO_L36N_A8_M1BA1_1_L17IO_L37P_A7_M1A0_1_H21IO_L37N_A6_M1A1_1_H22

IO_L38P_A5_M1CLK_1_K20IO_L38N_A4_M1CLKN_1_L19

IO_L39P_M1A3_1_J20IO_L39N_M1ODT_1_J22

IO_L40P_GCLK11_M1A5_1_M20IO_L40N_GCLK10_M1A6_1_M19IO_L41P_GCLK9_M1RASN_1_K21IO_L41N_GCLK8_M1CASN_1_K22IO_L42P_GCLK7_M1UDM_1_P20IO_L42N_GCLK6_M1LDM_1_N19IO_L43P_GCLK5_M1DQ4_1_L20IO_L43N_GCLK4_M1DQ5_1_L22

IO_L44P_A3_M1DQ6_1_M21IO_L44N_A2_M1DQ7_1_M22

IO_L45P_A1_M1LDQS_1_N20IO_L45N_A0_M1LDQSN_1_N22

IO_L46P_FCS_B_M1DQ2_1_P21IO_L46N_FOE_B_M1DQ3_1_P22IO_L47P_FWE_B_M1DQ0_1_R20IO_L47N_LDC_M1DQ1_1_R22IO_L48P_HDC_M1DQ8_1_T21

IO_L48N_M1DQ9_1_T22IO_L49P_M1DQ10_1_U20IO_L49N_M1DQ11_1_U22IO_L50P_M1UDQS_1_V21

IO_L50N_M1UDQSN_1_V22IO_L51P_M1DQ12_1_W20IO_L51N_M1DQ13_1_W22IO_L52P_M1DQ14_1_Y21IO_L52N_M1DQ15_1_Y22

IO_L53P_1_P19IO_L53N_VREF_1_R19

IO_L58P_1_M16IO_L58N_1_N15IO_L59P_1_U19IO_L59N_1_T20IO_L60P_1_N16IO_L60N_1_P16IO_L61P_1_M17IO_L61N_1_M18IO_L70P_1_R15IO_L70N_1_R16IO_L71P_1_P17IO_L71N_1_P18IO_L72P_1_R17IO_L72N_1_T17IO_L73P_1_T19IO_L73N_1_T18

IO_L74P_AWAKE_1_V19IO_L74N_DOUT_BUSY_1_V20

VCCO_1_C21VCCO_1_E19VCCO_1_G21VCCO_1_J18VCCO_1_L16VCCO_1_L21VCCO_1_N18VCCO_1_R21VCCO_1_U18VCCO_1_W21

6slx45tfg484BANK 1DUT

Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

SCHEM, ROHS COMPLIANTSP605 EVALUATION PLATFORM

FPGA Bank 1

FPGA Bank 1

04

BF

9-18-2009_15:04

353

D

NC

CLK_33MHZ_SYSACE 20

F18F19H16H17B21B22J16J17C20C22L15K16D21D22G19F20H18H19F21F22E20E22J19H20K19K18G20G22K17L17H21H22K20L19J20J22M20M19K21K22P20N19L20L22M21M22N20N22P21P22R20R22T21T22U20U22V21V22W20W22Y21Y22P19R19M16N15U19T20N16P16M17M18R15R16P17P18R17T17T19T18V19V20

C21E19G21J18L16L21N18R21U18W21

U1

SFP_LOS 12

PHY_RESET 11

USER_SMA_CLOCK_N 13USER_SMA_CLOCK_P 13

SYSCLK_P 14SYSCLK_N 14PHY_RXCLK 11

14GPIO_LED_2

FLASH_ADV_B 19FLASH_WAIT 19

DVI_D1 1711PHY_CRS

DVI_D2 17

DVI_D11 1717DVI_D10

PHY_MDIO 11

17DVI_D6

DVI_D4 17

DVI_H 17

DVI_D0 17

17DVI_XCLK_P

17DVI_RESET_B

21,26PMBUS_CTRL

DVI_D7 17DVI_D8 17

DVI_D3 17

DVI_D5 17

DVI_D9 17

DVI_V 17

DVI_DE 17

17DVI_XCLK_N

DVI_GPIO1 17FLASH_A23 19FLASH_A22 19FLASH_A21 19FLASH_A20 19FLASH_A19 19

FLASH_A14 19

FLASH_A10 19FLASH_A9 19FLASH_A8 19FLASH_A7 19FLASH_A6 19FLASH_A5 19FLASH_A4 19PHY_INT 11

FLASH_A3 19FLASH_A2 19FLASH_A1 19FLASH_A0 19FLASH_CE_B 19

11PHY_COL

18FPGA_AWAKE

PHY_MDC 11PHY_RXD0 11PHY_RXD1 11PHY_RXD2 11PHY_RXD3 11PHY_RXD4 11PHY_RXD5 11PHY_RXD6 11PHY_RXD7 11PHY_RXER 11

11PHY_RXCTL_RXDV

FLASH_WE_B 19FLASH_OE_B 19

FLASH_A11 19FLASH_A12 19FLASH_A13 19

FLASH_A15 19FLASH_A16 19FLASH_A17 19FLASH_A18 19

15USB_1_TX15USB_1_RX

IIC_SDA_MAIN 10,15IIC_SCL_MAIN 10,15

USB_1_CTS 15USB_1_RTS 15

PHY_TXCLK 11

Page 4: Xilinx XTP067 - SP605 Schematics

VCC2V5

VCC2V5_FPGA

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

IO_L1P_CCLK_2_Y20IO_L1N_M0_CMPMISO_2_AA21

IO_L2P_CMPCLK_2_V17IO_L2N_CMPMOSI_2_W18

IO_L3P_D0_DIN_MISO1_2_AA20IO_L3N_MOSI_CSI_B_MISO0_2_AB20

IO_L4P_2_U16IO_L4N_VREF_2_V15

IO_L5P_2_W17IO_L5N_2_Y18IO_L6P_2_AA14IO_L6N_2_AB14

IO_L12P_D1_MISO2_2_R13IO_L12N_D2_MISO3_2_T14

IO_L13P_M1_2_Y19IO_L13N_D10_2_AB19IO_L14P_D11_2_AA18IO_L14N_D12_2_AB18

IO_L15P_2_Y17IO_L15N_2_AB17IO_L16P_2_U14

IO_L16N_VREF_2_U13IO_L17P_2_Y16IO_L17N_2_W15IO_L18P_2_V13IO_L18N_2_W13

IO_L19P_2_AA16IO_L19N_2_AB16IO_L20P_2_W14IO_L20N_2_Y14IO_L21P_2_Y15

IO_L21N_2_AB15IO_L22P_2_R11IO_L22N_2_T11IO_L23P_2_T15IO_L23N_2_U15

IO_L29P_GCLK3_2_T12IO_L29N_GCLK2_2_U12

IO_L30P_GCLK1_D13_2_Y13IO_L30N_GCLK0_USERCCLK_2_AB13

IO_L31P_GCLK31_D14_2_AA12IO_L31N_GCLK30_D15_2_AB12

IO_L32P_GCLK29_2_Y11IO_L32N_GCLK28_2_AB11

IO_L40P_2_W12IO_L40N_2_Y12

IO_L41P_2_AA10IO_L41N_VREF_2_AB10

IO_L42P_2_V11IO_L42N_2_W11IO_L43P_2_Y9IO_L43N_2_AB9IO_L44P_2_W10IO_L44N_2_Y10IO_L45P_2_AA8IO_L45N_2_AB8IO_L46P_2_T10IO_L46N_2_U10IO_L47P_2_Y7IO_L47N_2_AB7

IO_L48P_D7_2_W9IO_L48N_RDWR_B_VREF_2_Y8

IO_L49P_D3_2_AA6IO_L49N_D4_2_AB6

IO_L50P_2_U9IO_L50N_2_V9IO_L57P_2_T8IO_L57N_2_U8IO_L58P_2_V7IO_L58N_2_W8IO_L59P_2_R9IO_L59N_2_R8IO_L60P_2_W6IO_L60N_2_Y6

IO_L62P_D5_2_Y5IO_L62N_D6_2_AB5

IO_L63P_2_AA4IO_L63N_2_AB4

IO_L64P_D8_2_T7IO_L64N_D9_2_U6

IO_L65P_INIT_B_2_Y4IO_L65N_CSO_B_2_AA3

VCCO_2_AA11VCCO_2_AA15VCCO_2_AA19VCCO_2_AA7VCCO_2_AB3VCCO_2_T13VCCO_2_T9VCCO_2_V12VCCO_2_V16VCCO_2_V8VCCO_2_W5

6slx45tfg484BANK 2DUT

PCB P/N: 0431534SCH P/N: 0381305

ART P/N: 1280473Test P/N: TSS0123

SCHEM, ROHS COMPLIANTSP605 EVALUATION PLATFORM

FPGA Bank 2

FPGA Bank 2

BF

D

4 35

9-18-2009_15:04

04

PHY_TXC_GTXCLK 11

Y20AA21V17W18AA20AB20U16V15W17Y18AA14AB14R13T14Y19AB19AA18AB18Y17AB17U14U13Y16W15V13W13AA16AB16W14Y14Y15AB15R11T11T15U15T12U12Y13AB13AA12AB12Y11AB11W12Y12AA10AB10V11W11Y9AB9W10Y10AA8AB8T10U10Y7AB7W9Y8AA6AB6U9V9T8U8V7W8R9R8W6Y6Y5AB5AA4AB4T7U6Y4AA3

AA11AA15AA19AA7AB3T13T9

V12V16V8W5

U1

FPGA_CMP_MOSI 18FPGA_CMP_CLK 18

FMC_LA30_P 10FMC_LA30_N 10

10FMC_LA25_P10FMC_LA25_N

10FMC_LA29_P10FMC_LA29_N

FMC_LA28_P 10FMC_LA28_N 10

10FMC_LA33_N10FMC_LA33_P

FMC_LA32_N 10FMC_LA32_P 10

10FMC_LA27_P10FMC_LA27_N

FMC_LA21_P 10FMC_LA21_N 10

FMC_LA22_P 10FMC_LA22_N 10

10FMC_LA19_N10FMC_LA19_P

10FMC_LA20_N10FMC_LA20_P

PMBUS_CLK 21,2621,26PMBUS_DATA

2

1 C260

120PF50VNPO

1

2

R285140

1/16W1%

1

2

R104.7K

1/16W5%

19FLASH_D8

14GPIO_SWITCH_2

GPIO_LED_3 14

10FMC_LA17_CC_P10FMC_LA17_CC_N

12SFP_TX_DISABLE_FPGA

16,17IIC_SCL_DVI

USER_CLOCK 14

18,19FPGA_D0_DIN_MISO_MISO1

18,19FPGA_D1_MISO218,19FPGA_D2_MISO3

19FLASH_D1019FLASH_D1119FLASH_D12

19FLASH_D13

19FLASH_D1519FLASH_D14

FLASH_D7 19

FLASH_D3 19FLASH_D4 19

FLASH_D5 19FLASH_D6 19

19FLASH_D9

PHY_TXCTL_TXEN 11PHY_TXER 11

16,17IIC_SDA_DVI

SPI_CS_B 18FPGA_INIT_B 14,20

PHY_TXD0 11PHY_TXD1 11PHY_TXD2 11PHY_TXD3 11

PHY_TXD4 11PHY_TXD5 11

PHY_TXD6 1111PHY_TXD7

7,10,19FMC_PWR_GOOD_FLASH_RST_B

FPGA_M1 18

FPGA_MOSI_CSI_B_MISO0 18

18FPGA_M0_CMP_MISO

FMC_PRSNT_M2C_L 10

18FPGA_CCLK

14GPIO_SWITCH_1

14GPIO_LED_1

10FMC_LA18_CC_P10FMC_LA18_CC_N

FMC_LA24_N 10FMC_LA24_P 10

10FMC_LA26_P10FMC_LA26_N

10FMC_LA31_P10FMC_LA31_N

10FMC_LA23_P10FMC_LA23_N

NC

Page 5: Xilinx XTP067 - SP605 Schematics

VTTVREF

VCC1V5_FPGA

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

IO_L1P_3_R7IO_L1N_VREF_3_P8

IO_L2P_3_W4IO_L2N_3_Y3IO_L7P_3_T6IO_L7N_3_T5IO_L8P_3_V5IO_L8N_3_V3IO_L9P_3_P5IO_L9N_3_P4

IO_L10P_3_AA2IO_L10N_3_AA1IO_L23P_3_N6IO_L23N_3_N7IO_L24P_3_U4IO_L24N_3_T4IO_L25P_3_P6IO_L25N_3_P7IO_L26P_3_T3IO_L26N_3_R4IO_L31P_3_M7

IO_L31N_VREF_3_M8IO_L32P_M3DQ14_3_Y2IO_L32N_M3DQ15_3_Y1IO_L33P_M3DQ12_3_W3IO_L33N_M3DQ13_3_W1IO_L34P_M3UDQS_3_V2

IO_L34N_M3UDQSN_3_V1IO_L35P_M3DQ10_3_U3IO_L35N_M3DQ11_3_U1IO_L36P_M3DQ8_3_T2IO_L36N_M3DQ9_3_T1IO_L37P_M3DQ0_3_R3IO_L37N_M3DQ1_3_R1IO_L38P_M3DQ2_3_P2IO_L38N_M3DQ3_3_P1IO_L39P_M3LDQS_3_N3

IO_L39N_M3LDQSN_3_N1IO_L40P_M3DQ6_3_M2IO_L40N_M3DQ7_3_M1

IO_L41P_GCLK27_M3DQ4_3_L3IO_L41N_GCLK26_M3DQ5_3_L1IO_L42P_GCLK25_M3UDM_3_P3IO_L42N_GCLK24_M3LDM_3_N4IO_L43P_GCLK23_M3RASN_3_M5IO_L43N_GCLK22_M3CASN_3_M4

IO_L44P_GCLK21_M3A5_3_M3IO_L44N_GCLK20_M3A6_3_L4

IO_L45P_M3A3_3_M6IO_L45N_M3ODT_3_L6IO_L46P_M3CLK_3_K4IO_L46N_M3CLKN_3_K3IO_L47P_M3A0_3_K2IO_L47N_M3A1_3_K1

IO_L48P_M3BA0_3_J3IO_L48N_M3BA1_3_J1IO_L49P_M3A7_3_K6IO_L49N_M3A2_3_K5IO_L50P_M3WE_3_H2

IO_L50N_M3BA2_3_H1IO_L51P_M3A10_3_J4IO_L51N_M3A4_3_H3IO_L52P_M3A8_3_G3IO_L52N_M3A9_3_G1

IO_L53P_M3CKE_3_F2IO_L53N_M3A12_3_F1

IO_L54P_M3RESET_3_E3IO_L54N_M3A11_3_E1IO_L55P_M3A13_3_J6IO_L55N_M3A14_3_H5

IO_L57P_3_K7IO_L57N_VREF_3_K8

IO_L58P_3_H4IO_L58N_3_G4IO_L59P_3_D2IO_L59N_3_D1IO_L60P_3_F3IO_L60N_3_E4IO_L80P_3_H6IO_L80N_3_G7IO_L81P_3_J7IO_L81N_3_H8IO_L82P_3_F5IO_L82N_3_G6IO_L83P_3_C1

IO_L83N_VREF_3_B1

VCCO_3_C2VCCO_3_F4VCCO_3_G2VCCO_3_J5VCCO_3_L2VCCO_3_L7VCCO_3_N5VCCO_3_R2VCCO_3_U5VCCO_3_W2

6slx45tfg484BANK 3DUT

Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

SCHEM, ROHS COMPLIANTSP605 EVALUATION PLATFORM

FPGA Bank 3

FPGA Bank 3

04

BF

9-18-2009_15:04

355

D

2

1

1%1/16W

DNPR124

R7P8W4Y3T6T5V5V3P5P4AA2AA1N6N7U4T4P6P7T3R4M7M8Y2Y1W3W1V2V1U3U1T2T1R3R1P2P1N3N1M2M1L3L1P3N4M5M4M3L4M6L6K4K3K2K1J3J1K6K5H2H1J4H3G3G1F2F1E3E1J6H5K7K8H4G4D2D1F3E4H6G7J7H8F5G6C1B1

C2F4G2J5L2L7N5R2U5W2

U1

35GPIO_HEADER_3_LS

2

1 R207150

1/16W5%

1

2

R126100

1/16W5%

1 2X5R

10V

0.1UF

C1

VCC1V5

FPGA_ONCHIP_TERM2

FPGA_ONCHIP_TERM1

FPGA_VTEMP

14GPIO_BUTTON314GPIO_BUTTON114GPIO_BUTTON214CPU_RESET

PCIE_PERST_B_LS 3535GPIO_HEADER_0_LS

GPIO_HEADER_1_LS 35GPIO_SWITCH_3 14GPIO_BUTTON0 14

35GPIO_HEADER_2_LSSYSACE_MPA06_LS 35SYSACE_MPA05_LS 35SYSACE_MPA04_LS 35

MEM1_A14 9MEM1_A13 9MEM1_A11 9MEM1_RESET_B 9MEM1_A12 9MEM1_CKE 9MEM1_A9 9MEM1_A8 9MEM1_A4 9MEM1_A10 9MEM1_BA2 9MEM1_WE_B 9MEM1_A2 9MEM1_A7 9MEM1_BA1 9MEM1_BA0 9MEM1_A1 9MEM1_A0 9MEM1_CLK_N 9MEM1_CLK_P 9MEM1_ODT 9MEM1_A3 9MEM1_A6 9MEM1_A5 9MEM1_CAS_B 9MEM1_RAS_B 9MEM1_LDM 9MEM1_UDM 9MEM1_DQ5 9MEM1_DQ4 9MEM1_DQ7 9MEM1_DQ6 9MEM1_LDQS_N 9MEM1_LDQS_P 9MEM1_DQ3 9MEM1_DQ2 9MEM1_DQ1 9MEM1_DQ0 9MEM1_DQ9 9MEM1_DQ8 9MEM1_DQ11 9MEM1_DQ10 9MEM1_UDQS_N 9MEM1_UDQS_P 9MEM1_DQ13 9MEM1_DQ12 9MEM1_DQ15 9MEM1_DQ14 9

SYSACE_D7_LS 35SYSACE_D6_LS 35SYSACE_D5_LS 35SYSACE_D4_LS 35SYSACE_D3_LS 35SYSACE_D2_LS 35SYSACE_D1_LS 35SYSACE_D0_LS 35SYSACE_MPBRDY_LS 35SYSACE_MPIRQ_LS 35SYSACE_MPA03_LS 35SYSACE_MPA02_LS 35SYSACE_MPA01_LS 35SYSACE_MPA00_LS 35SYSACE_MPWE_LS 35SYSACE_MPOE_LS 35

SYSACE_MPCE_LS 35

Page 6: Xilinx XTP067 - SP605 Schematics

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

MGTAVTTRX_123_D14MGTAVTTTX_123_A15MGTAVCC_123_E10

MGTAVCCPLL1_123_E13MGTAVCCPLL0_123_B13MGTREFCLK1N_123_F12MGTREFCLK1P_123_E12MGTREFCLK0N_123_B12MGTREFCLK0P_123_A12

MGTRXN1_123_C15MGTRXP1_123_D15MGTTXN1_123_A16MGTTXP1_123_B16MGTRXN0_123_C13MGTRXP0_123_D13MGTTXN0_123_A14MGTTXP0_123_B14

6slx45tfg484BANK 123

DUT

MGTAVTTRX_101_D8MGTAVTTTX_101_A7MGTAVCC_101_C10

MGTAVCCPLL1_101_D12MGTAVCCPLL0_101_B9

MGTREFCLK1N_101_D11MGTREFCLK1P_101_C11MGTREFCLK0N_101_B10MGTREFCLK0P_101_A10

MGTRXN1_101_C9MGTRXP1_101_D9MGTTXN1_101_A8MGTTXP1_101_B8MGTRXN0_101_C7MGTRXP0_101_D7MGTTXN0_101_A6MGTTXP0_101_B6

6slx45tfg484BANK 101

DUT

Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

SCHEM, ROHS COMPLIANTSP605 EVALUATION PLATFORM

MGT Banks

MGT Banks

D

6 35

9-18-2009_15:04

BF

04FMC_GBTCLK0_M2C_C_N 6

FMC_GBTCLK0_M2C_C_P 6

FMC_GBTCLK0_M2C_C_P 6FMC_GBTCLK0_M2C_C_N 6

10 FMC_GBTCLK0_M2C_P

10 FMC_GBTCLK0_M2C_N

1 2X5R

10V

0.1UFC

401

D8A7C10D12B9D11C11B10A10C9D9A8B8C7D7A6B6

U1

D14A15E10E13B13F12E12B12A12C15D15A16B16C13D13A14B14

U1

1

2X5R10V4.7UF

C329

2

1 C328

4.7UF10VX5R

1

2X5R10V4.7UF

C327

MGT_AVCC

2

1 C307

0.22UF10VX7R

MGT_AVCC

SFPCLK_QO_P 28SFPCLK_QO_N 28

PCIE_250M_P 28PCIE_250M_N 28

13SMA_RX_N

PCIE_TX0_P 12

SFP_TX_P 12SFP_TX_N 12SFP_RX_P 12SFP_RX_N 12

10FMC_DP0_C2M_PFMC_DP0_C2M_N 10

10FMC_DP0_M2C_PFMC_DP0_M2C_N 10

PCIE_TX0_N 1212PCIE_RX0_P

PCIE_RX0_N 12SMA_TX_P 13SMA_TX_N 13

13SMA_RX_P

13SMA_REFCLK_P13SMA_REFCLK_N

MGT_AVCC

1

2X7R10V0.22UF

C308

2

1 C309

0.22UF10VX7R

1

2X7R10V0.22UF

C310

2

1 C311

0.22UF10VX7R

1

2X7R10V0.22UF

C316

2

1 C315

0.22UF10VX7R

1

2X7R10V0.22UF

C314

2

1 C313

0.22UF10VX7R

1

2X7R10V0.22UF

C312

2

1 C326

4.7UF10VX5R

21

C400

0.1UF

10V

X5R

Page 7: Xilinx XTP067 - SP605 Schematics

Y8

Y1

Y3Y4Y5Y6Y7

Y2

OE1_NA1

A3A4

A2

A5

A8A7A6

GND

SN74LV541APWR

OE2_NVCC

VCCINT_FPGA

VCCAUX

VCC2V5

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCAUX

VCCINT_J10VCCINT_J12VCCINT_J14VCCINT_J8

VCCINT_K11VCCINT_K13VCCINT_K9

VCCINT_L10VCCINT_L12VCCINT_L14VCCINT_M11VCCINT_M13VCCINT_M9

VCCINT_N10VCCINT_N12VCCINT_N14VCCINT_P11VCCINT_P13VCCINT_P9

VCCINT_R14

6slx45tfg484BANK VCCINT

DUT

TCK_A21TDI_E18TMS_D20TDO_G17

SUSPEND_AA22CMPCS_B_2_V18DONE_2_AB21

PROGRAM_B_2_AB2MGTRREF_101_E9

MGTAVTTRCAL_101_E8NC_U17NC_T16NC_P15

6slx45tfg484BANK DED

DUT

VCCAUX_F11VCCAUX_G12VCCAUX_H15VCCAUX_H9

VCCAUX_K15VCCAUX_L8

VCCAUX_M15VCCAUX_N8

VCCAUX_R10VCCAUX_R12VCCAUX_R6

VCCAUX_U11VCCAUX_V6

6slx45tfg484BANK VCCAUX

DUT

GND_A1GND_A11GND_A13GND_A22GND_A9

GND_AA13GND_AA17GND_AA5GND_AA9GND_AB1

GND_AB22GND_B11GND_B15GND_B17GND_B5GND_B7GND_C12GND_C14GND_C16GND_C6GND_C8GND_D10GND_D16GND_D6GND_E11GND_E14GND_E15GND_E2GND_E21GND_E7GND_F13GND_G18GND_G5GND_H7GND_J11GND_J13GND_J15GND_J2GND_J21GND_J9GND_K10GND_K12GND_K14GND_L11GND_L13GND_L18GND_L5GND_L9GND_M10GND_M12GND_M14GND_N11GND_N13GND_N17GND_N2GND_N21GND_N9GND_P10GND_P12GND_P14GND_R18GND_R5GND_U2GND_U21GND_U7GND_V10GND_V14GND_V4GND_W16GND_W19GND_W7

6slx45tfg484BANK GND

DUT

PCB P/N: 0431534SCH P/N: 0381305

ART P/N: 1280473Test P/N: TSS0123

SCHEM, ROHS COMPLIANTSP605 EVALUATION PLATFORM

Trace length from the resistor

pins to the FPGA pins MGTRREF and MGTVTTRCAL

must be equal in length.

Power, GND, and Dedicated Banks

Power, GND, and Dedicated Banks

Pins not

connected

in LX45T

BF

04

9-24-2009_14:59

357

D

A1A11A13A22A9AA13AA17AA5AA9AB1AB22B11B15B17B5B7C12C14C16C6C8D10D16D6E11E14E15E2E21E7F13G18G5H7J11J13J15J2J21J9K10K12K14L11L13L18L5L9M10M12M14N11N13N17N2N21N9P10P12P14R18R5U2U21U7V10V14V4W16W19W7

U1

F11G12H15H9K15L8M15N8R10R12R6U11V6

U1

A21E18D20G17AA22V18AB21AB2E9E8U17T16P15

U1

J10J12J14J8K11K13K9L10L12L14M11M13M9N10N12N14P11P13P9R14

U1

1

2

R288

DNP

1/16W

1%

1

2 J59

DNP

2

1H-1X2

J58 4,10,19FMC_PWR_GOOD_FLASH_RST_B

2

1

1%1/16W

DNPR260

2

1

1%1/16W

49.9R127

2

1

5%1/16W

4.7KR11

14,18,20FPGA_PROG_BFPGA_DONE 14

18FPGA_CMP_CS_BFPGA_SUSPEND 18SYSACE_CFGTDI 20

20FPGA_TMS

20FPGA_TCK20FPGA_TDI

MGT_AVCC

NCNC

JTAG_TCK32 FMC_TCK_BUF 1020SYSACE_TCK_BUF

JTAG_TDI3210FMC_TMS_BUF

NC NC

JTAG_TMS32

VCC3V3 VCC3V3

2

1 C20.1UF

10VX5R

1

2

R17210K

1/16W5%

NC NC

20SYSACE_TMS_BUF

FMC_TDI_BUF 10

11

18

1615141312

17

12

45

3

6

987

10

1920

U8

15FPGA_VBATT

Page 8: Xilinx XTP067 - SP605 Schematics

VCCAUX

VCCINT_FPGA

VCC1V5_FPGA

VCC2V5_FPGA

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

SCHEM, ROHS COMPLIANTSP605 EVALUATION PLATFORM

VCCO Bank 3 1.5V

VCCO 2.5V

VCCINT 1.2V

VCCAUX 2.5V

FPGA Decoupling

FPGA Decoupling

2

1 C108

2.2UF6.3VX5R

04021

2

0402

X5R6.3V2.2UF

C107

2

1 C106

2.2UF6.3VX5R

04021

2

0402

X5R6.3V2.2UF

C105 1

2

0402

X5R6.3V2.2UF

C103 1

2

0402

X5R6.3V2.2UF

C111

1

2

0402

X5R6.3V2.2UF

C124

2

1 C123

2.2UF6.3VX5R

04021

2

0402

X5R6.3V2.2UF

C122

2

1 C127

2.2UF6.3VX5R

04021

2

0402

X5R6.3V2.2UF

C128

2

1 C125

2.2UF6.3VX5R

0402

2

1 C121

2.2UF6.3VX5R

0402

1

2

0402

X5R6.3V2.2UF

C118

2

1 C117

2.2UF6.3VX5R

04021

2

0402

X5R6.3V2.2UF

C116

2

1 C119

2.2UF6.3VX5R

04021

2

0402

X5R6.3V2.2UF

C112

2

1 C110

2.2UF6.3VX5R

04021

2

0402

X5R6.3V2.2UF

C109

2

1 C104

2.2UF6.3VX5R

0402

2

1 C98

2.2UF6.3VX5R

04021

2

0402

X5R6.3V2.2UF

C114

2

1 C102

2.2UF6.3VX5R

0402

2

1 C113

2.2UF6.3VX5R

04021

2

0402

X5R6.3V2.2UF

C101

2

1 C100

2.2UF6.3VX5R

04021

2

0402

X5R6.3V2.2UF

C99

2

1 C129

2.2UF6.3VX5R

04021

2

0402

X5R6.3V2.2UF

C126 1

2

0402

X5R6.3V2.2UF

C120

1

2

0805

X5R6.3V10UF

C187

2

1 C188

10UF6.3VX5R

08051

2

0805

X5R6.3V10UF

C189

1

2

0805

X5R6.3V10UF

C192

2

1 C390

10UF6.3VX5R

08051

2

0805

X5R6.3V10UF

C389

2

1 C176

10UF6.3VX5R

0805

2

1 C180

10UF6.3VX5R

08051

2

0805

X5R6.3V10UF

C177

2

1 C178

10UF6.3VX5R

08051

2

0805

X5R6.3V10UF

C179

1

2

0805

X5R6.3V10UF

C183

2

1 C182

10UF6.3VX5R

08051

2

0805

X5R6.3V10UF

C181 1

2

0805

X5R6.3V10UF

C175 1

2

0805

X5R6.3V10UF

C173

2

1 C186

10UF6.3VX5R

0805

2

1 C174

10UF6.3VX5R

0805

2

1 C184

10UF6.3VX5R

08051

2

0805

X5R6.3V10UF

C185

04

BF

9-24-2009_15:46

358

D

1

2

0805

X5R6.3V10UF

C172

2

1 C171

10UF6.3VX5R

0805

1

2

C257470UF

6.3VTANT

2

1

TANT6.3V

470UFC254

2

1

TANT6.3V

470UFC256

1

2

C255470UF

6.3VTANT

2

1 C115

2.2UF6.3VX5R

0402

Page 9: Xilinx XTP067 - SP605 Schematics

VTTDDR

VTTDDR

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

FBGA_DDR3_82P_96P

MT41J64M16LA_187E

A0A1

A10/APA11A12/BCN

A2A3A4A5A6A7A8A9

BA0BA1BA2

CK_P

CKE

DQ0DQ1

DQ10DQ11DQ12DQ13DQ14

DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9

LDM

LDQS_P

NC/A13NC/A14

NC1NC2NC3NC4NC5

ODT

UDM

UDQS_P

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDD9

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VREFCA

VREFDQ

VSS1

VSS10

VSS11

VSS12

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

ZQ

CAS_B

CK_N

CS_B

LDQS_NRAS_B

RESET_B

UDQS_N

WE_B

DQ15

VTTVREF

SP605 EVALUATION PLATFORM Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

from here back to (10)VCCOB3 remote sense pair connects

(16)(16)

DDR3 SDRAMFBGA 96

DDR3SCHEM, ROHS COMPLIANT

DDR3

04

D9-24-2009_15:00

359 BF

MEM1_RESET_B5

MEM1_ODT5

1

2

R134.7K

1/16W5%

N3P7

L7R7N7

P3N2P8P2R8R2T8R3

M2N8M3

J7

K9

E3F7

C8C2A7A2B8

F2F8H3H8G2H7D7C3

E7

F3

T3T7

J1J9L1L9M7

K1

D3

C7

B2

D9

G7

K2

K8

N1

N9

R1

R9

A1

A8

C1

C9

D2

E9

F1

H2

H9

M8

H1

A9

P9

T1

T9

B3

E1

G8

J2

J8

M1

M9

P1

B1

B9

D1

D8

E2

E8

F9

G1

G9

L8

K3

K7

L2

G3J3

T2

B7

L3

A3

U42

2

1 C25

0.1UF10VX5R

2

1

5%1/16W

100R129

2

1

5%1/16W

4.7KR12

1 2

R128

100

1/16W

5%

2

1 R199240

1/16W5%

1

2X5R10V0.1UF

C8

2

1 C7

0.1UF10VX5R

MEM1_A115

1

2X5R10V0.1UF

C18

VCC1V5

MEM1_CKE5MEM1_CLK_N5MEM1_CLK_P5

MEM1_BA15MEM1_BA05MEM1_A145MEM1_A135

MEM1_CAS_B5

MEM1_WE_B5MEM1_RAS_B5

MEM1_BA25

MEM1_A125

MEM1_A105MEM1_A95MEM1_A85MEM1_A75MEM1_A65MEM1_A55MEM1_A45MEM1_A35MEM1_A25MEM1_A15MEM1_A05

VCC1V5

VCC1V5

FP

GA

B3_

ME

MR

EF

2

1 C3

0.1UF10VX5R

1

2X5R10V0.1UF

C4

2

1 C5

0.1UF10VX5R

1

2X5R10V0.1UF

C6

1

2

R9849.9

1/16W1%

2

1

1%1/16W

49.9R94

1

2

R7849.9

1/16W1%

1

2

R8049.9

1/16W1%

2

1

1%1/16W

49.9R79

MEM1_LDQS_P 5

MEM1_DQ14 5

MEM1_CS_B

ME

M1_

ZQ

MEM1_DQ9 5

MEM1_DQ15 5

MEM1_DQ13 5

MEM1_DQ12 5

MEM1_DQ10 5

MEM1_DQ11 5

MEM1_DQ8 5

MEM1_DQ5 5

MEM1_DQ2 5

MEM1_DQ3 5

MEM1_DQ0 5

MEM1_DQ1 5

MEM1_DQ6 5

MEM1_DQ7 5

MEM1_DQ4 5

MEM1_LDM 5

NCNCNCNCNC

MEM1_UDM 5

MEM1_UDQS_P 5

MEM1_LDQS_N 5

MEM1_UDQS_N 5

2

1

1%1/16W

49.9R81

1

2

R8549.9

1/16W1%

1

2

R8449.9

1/16W1%

2

1

1%1/16W

49.9R83

2

1

1%1/16W

49.9R82

1

2

R8949.9

1/16W1%

1

2

R8849.9

1/16W1%

2

1

1%1/16W

49.9R87

2

1

1%1/16W

49.9R86

1

2

R9349.9

1/16W1%

1

2

R9249.9

1/16W1%

2

1

1%1/16W

49.9R91

2

1

1%1/16W

49.9R90

1

2

R9749.9

1/16W1%

1

2

R9649.9

1/16W1%

2

1

1%1/16W

49.9R95

1

2X5R10V0.1UF

C12

2

1 C11

0.1UF10VX5R

1

2X5R10V0.1UF

C10

2

1 C9

0.1UF10VX5R

2

1 C17

0.1UF10VX5R

1

2X5R10V0.1UF

C16

2

1 C15

0.1UF10VX5R

1

2X5R10V0.1UF

C14

2

1 C13

0.1UF10VX5R

2

1 C19

0.1UF10VX5R

1

2X5R10V0.1UF

C20

2

1 C21

0.1UF10VX5R

1

2X5R10V0.1UF

C22

2

1 C23

0.1UF10VX5R

1

2X5R10V0.1UF

C24

2

1

5%1/16W

4.7KR289

Page 10: Xilinx XTP067 - SP605 Schematics

VCC12_PVCC3V3

VCC3V3

VCC2V5

VCC3V3

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC2V5

VCC2V5

VCC3V3

VCC12_P

CLK0_M2C_N

CLK0_M2C_P

LA02_N

LA02_P

LA04_N

LA04_P

LA07_N

LA07_P

LA11_N

LA11_P

LA15_N

LA15_P

LA19_N

LA19_P

LA21_N

LA21_P

LA24_N

LA24_P

LA28_N

LA28_P

LA30_N

LA30_P

LA32_N

LA32_P

PRSNT_M2C_L

VADJ_4

VREF_A_M2C

ASP_134603_01

3P3VAUX

3P3V_2

3P3V_3

3P3V_4

GA1

GBTCLK0_M2C_N

GBTCLK0_M2C_P

LA01_N_CC

LA01_P_CC

LA05_N

LA05_P

LA09_N

LA09_P

LA13_N

LA13_P

LA17_N_CC

LA17_P_CC

LA23_N

LA23_P

LA26_N

LA26_P

PG_C2M

TCK

TDI

TDO

TMS

TRST_L

ASP_134603_01

CLK1_M2C_N

CLK1_M2C_P

LA00_N_CC

LA00_P_CC

LA03_N

LA03_P

LA08_N

LA08_P

LA12_N

LA12_P

LA16_N

LA16_P

LA20_N

LA20_P

LA22_N

LA22_P

LA25_N

LA25_P

LA29_N

LA29_P

LA31_N

LA31_P

LA33_N

LA33_P

VADJ_3

ASP_134603_01

GND_103

GND_104

GND_105

GND_106

GND_107

GND_108

GND_109

GND_110

GND_111

GND_112

GND_113

GND_114

GND_115

GND_116

GND_117

GND_118

GND_119

GND_120

GND_121

GND_122

GND_123

GND_124

GND_125

GND_126

GND_127

GND_128

GND_129

GND_130

GND_41

GND_42

GND_43

GND_44

GND_45

GND_46

GND_47

GND_48

GND_49

GND_50

GND_51

GND_52

GND_53

GND_54

GND_55

GND_56

GND_57

GND_58

GND_59

GND_60

GND_61

GND_62

GND_63

GND_64

GND_65

GND_66

GND_67

GND_68

GND_69

GND_70

GND_71

GND_72

GND_73

ASP_134603_01

12P0V_1

12P0V_2

3P3V_1

DP0_C2M_N

DP0_C2M_P

DP0_M2C_N

DP0_M2C_P

GA0

LA06_N

LA06_P

LA10_N

LA10_P

LA14_N

LA14_P

LA18_N_CC

LA18_P_CC

LA27_N

LA27_P

SCL

SDA

ASP_134603_01

in JTAG chainJumper to include FMC

PCB P/N: 0431534SCH P/N: 0381305

ART P/N: 1280473Test P/N: TSS0123

SCHEM, ROHS COMPLIANTSP605 EVALUATION PLATFORM

FMC LPC ConnectorANSI/VITA 57.1-2008 Version 1.1

FMC LPC Connector

FMC Power Good LED

C35

C37

C39

C3

C2

C7

C6

C34

C11

C10

C15

C14

C19

C18

C23

C22

C27

C26

C30

C31

J2

04

9-25-2009_10:32

3510

D

BF

G1

G4

G5

G8

G11

G14

G17

G20

G23

G26

G29

G32

G35

G38

G40

H3

H6

H9

H12

H15

H18

H21

H24

H27

H30

H33

H36

H39

C1

C4

C5

C8

C9

C12

C13

C16

C17

C20

C21

C24

C25

C28

C29

C32

C33

C36

C38

C40

D2

D3

D6

D7

D10

D13

D16

D19

D22

D25

D28

D37

D39

J2

G3

G2

G7

G6

G10

G9

G13

G12

G16

G15

G19

G18

G22

G21

G25

G24

G28

G27

G31

G30

G34

G33

G37

G36

G39

J2

D32

D36

D38

D40

D35

D5

D4

D9

D8

D12

D11

D15

D14

D18

D17

D21

D20

D24

D23

D27

D26

D1

D29

D30

D31

D33

D34

J2

H5

H4

H8

H7

H11

H10

H14

H13

H17

H16

H20

H19

H23

H22

H26

H25

H29

H28

H32

H31

H35

H34

H38

H37

H2

H40

H1

J2

1

32

Q2

NDS331N4,7,10,19 FMC_PWR_GOOD_FLASH_RST_B

4,7,10,19FMC_PWR_GOOD_FLASH_RST_B

21

LED-GRN-SMT

DS1

2

1 R137200

1/16W5%

1

2

3

J19

H-1X3

20SYSACE_TDI

FMC_TCK_BUF 7

6FMC_GBTCLK0_M2C_N

6FMC_GBTCLK0_M2C_P

6FMC_DP0_M2C_N

FMC_DP0_M2C_P 6

6FMC_DP0_C2M_N

FMC_DP0_C2M_P 6

2FMC_LA06_P

1

2

C3881UF

50VELEC

1

2X7R16V1UF

C293

2

1 C292

1UF16VX7R

FMC_TMS_BUF 7

FMC_LA17_CC_N 4

FMC_CLK1_M2C_N 2

FMC_CLK1_M2C_P 2

FMC_PRSNT_M2C_L 4

10FMC_TDO

IIC_SDA_MAIN 3,15

FMC_LA27_N 4

IIC_SCL_MAIN 3,15

NC

FMC_CLK0_M2C_P 2

FMC_CLK0_M2C_N 2

FMC_LA02_P 2

FMC_LA02_N 2

FMC_LA04_P 2

FMC_LA04_N 2

FMC_LA07_P 2

FMC_LA07_N 2

FMC_LA11_P 2

FMC_LA11_N 2

FMC_LA15_P 2

FMC_LA15_N 2

FMC_LA19_P 4

FMC_LA19_N 4

FMC_LA21_P 4

FMC_LA21_N 4

FMC_LA24_P 4

FMC_LA24_N 4

FMC_LA28_P 4

FMC_LA28_N 4

FMC_LA30_P 4

FMC_LA30_N 4

FMC_LA32_P 4

FMC_LA32_N 4

FMC_LA05_N 2

FMC_LA26_N 4

FMC_LA26_P 4

FMC_LA23_N 4

FMC_LA23_P 4

FMC_LA17_CC_P 4

FMC_LA13_N 2

FMC_LA13_P 2

FMC_LA09_N 2

FMC_LA09_P 2

FMC_LA05_P 2

FMC_LA01_CC_N 2

FMC_LA01_CC_P 2

FMC_LA33_N 4

FMC_LA33_P 4

FMC_LA31_N 4

FMC_LA31_P 4

FMC_LA29_N 4

FMC_LA29_P 4

FMC_LA25_N 4

FMC_LA25_P 4

FMC_LA22_N 4

FMC_LA22_P 4

FMC_LA20_N 4

FMC_LA20_P 4

FMC_LA16_N 2

FMC_LA16_P 2

FMC_LA12_N 2

FMC_LA12_P 2

FMC_LA08_N 2

FMC_LA08_P 2

FMC_LA03_N 2

FMC_LA03_P 2

FMC_LA00_CC_N 2

FMC_LA00_CC_P 2

FMC_LA06_N 2

FMC_LA10_P 2

FMC_LA10_N 2

FMC_LA14_P 2

FMC_LA14_N 2

FMC_LA18_CC_P 4

FMC_LA18_CC_N 4

FMC_LA27_P 4

NC

7,10FMC_TDI_BUF

FMC_TDI_BUF 7,10

10FMC_TDO

Page 11: Xilinx XTP067 - SP605 Schematics

VCCINTVCC2V5

VCC2V5

VCC2V5

VCC2V5

VCCINT

VCC2V5VCCINT

VCC2V5

VCC2V5

VCC2V5

VCCINT

TD1_P

TD0_N

TD1_N

TD2_P

TD2_N

TD3_N

TD3_P

VCC

TD0_P

GND

SH2

SH1

10/100/1000

MAGNETICS

RJ45 AND

VSS_127

VDDO_122

DVDD_117

VSS_106

AVDD_104

DVDD_96

VDDOH_97

DVDD_90DVDD_85DVDD_78

VDDOX_71

AVDD_64AVDD_59AVDD_52

VSS_65

VSS_9

CONFIG1

CONFIG3CONFIG4CONFIG5CONFIG6

CRS

HSDAC_N

LED_DPLX

LED_LINK10LED_LINK100

LED_LINK1000

LED_RXLED_TX

MDC

MDI1_N

MDI2_N

MDI3_N

MDIO

RXD1RXD2RXD3

RXD4RXD5RXD6

RXER

SIN_P

SCLK_PSCLK_N

TDI

TDO

TMSTRST_B

TXD0TXD1TXD2TXD3

TXD4TXD5

TXD7

TXER

SOUT_NSOUT_P

TCK

RXCLK

RXD0

RXDV

TXCLK

VSS_43

AVDD_49VDDOX_34

GTXCLK

TXEN

MDI0_P

RSETRESET_BCOMAINT_BCLK125

TXD6

RXD7

COL

SIN_N

CONFIG0

CONFIG2

DVDD_118

VDDOH_73

AVDD_44

DVDD_23DVDD_27

DVDD_17DVDD_12DVDD_6DVDD_2

VDDO_5

VSS_119VSS_116VSS_111VSS_108

VSS_103VSS_102VSS_101

VSS_93VSS_84VSS_83VSS_66

VSS_63VSS_60VSS_58

VSS_1

VSS_15VSS_21VSS_22

VSS_40VSS_38

VSS_45VSS_48VSS_51VSS_55

VDDO_30VDDO_11

SEL_OSC

XTAL1XTAL2

VSSC_74

VSS_94

MDI0_N

MDI1_P

MDI2_P

MDI3_P

HSDAC_P

VDDOH_89

NC_50

VCC2V5

LED_GRN_SMALL_DUAL_STACK

BOT

TOP

LED_GRN_SMALL_DUAL_STACK

BOT

TOP

VCC2V5

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

LED_GRN_SMALL_DUAL_STACK

BOT

TOP

SP605 EVALUATION PLATFORM

"RX"

ASSY P/N: 0431540PCB P/N: 1280479SCH P/N: 0381311

111

111

111

PHYADR[1]

PHYADR[4]

PHYADR[2]

ENA_PAUSE

ANEG[0]

ANEG[3]

ENA_XC

PHYADR[3]

ANEG[2] ANEG[1]

DIS_125

DIS_FC DIS_SLEEP

SEL_BDT INT_POL 75/50 OHM

111

010

advertise the PAUSE bitPHYADR[0]

Bit[0]Pin Bit[2] Bit[1]

VCC2V5

GND

101

100

011

010

001

000

CFG0

CFG1

CFG2

CFG3

CFG4

CFG5

CFG6

HWCFG_MD[0]

HWCFG_MD[3]

HWCFG_MD[1]HWCFG_MD[2]

125 CLK option disabled.Auto crossover enabled.all caps; prefer slave.Auto-Neg en, advertise

GMII to Cu mode.Fiber/copper auto-detect diasabled.Sleep mode disabled.MDC/MDIO selected.Active LOW interrupt50Ohm SERDES option.

Constant MappingPin to

[2:0]Bit

111

110

Pin

LED_LINK10

LED_LINK100

LED_LINK1000

LED_DUPLEX

LED_RX

LED_TX

and are all bidirectional pins.

The PHY MDIP Pins below are

10/100/1000 PHY

Media Dependent Interface Pins (MDIP),

10/100/1000 PHY

000

111 PHYAddr "00111". Don't

"1000"

"TX"

"10"

"DUP"

LED Silkscreen

"100"

SCHEM, ROHS COMPLIANT

1

2

0805

X5R6.3V10UF

C194

2

1 C193

10UF6.3VX5R

0805

1

2

0805

X5R6.3V10UF

C196

2

1 C195

10UF6.3VX5R

0805 9-24-2009_15:30

351104

D

BF

43

1 2DS13

PHY_LED_TX_R

PHY_LED_RX_R

PHY_LED_LINK10_R

PHY_LED_LINK100_R

11PHY_LED_LINK10

11PHY_LED_LINK1000

11PHY_LED_DUPLEX

11PHY_CONFIG0

21

3 4

DS12

43

1 2DS11

XTAL1_25MHZ_ENET 11PHY_LED_TX 11

PHY_LED_LINK100 11

XTAL2_25MHZ_ENET 11XTAL1_25MHZ_ENET 11

PHY_LED_LINK100011

PHY_LED_RX11

PHY_LED_LINK10011

PHY_LED_TX11

PHY_LED_LINK1011

PHY_LED_DUPLEX11

2

1

FERRITE-220

F207

4 PHY_TXD74 PHY_TXD6

PHY_TXD544 PHY_TXD4

4 PHY_TXD34 PHY_TXD24 PHY_TXD14 PHY_TXD0

4 PHY_TXCTL_TXEN

3 PHY_TXCLK4 PHY_TXER

4 PHY_TXC_GTXCLK

3 PHY_RXD73 PHY_RXD63 PHY_RXD53 PHY_RXD4

3 PHY_RXD33 PHY_RXD23 PHY_RXD13 PHY_RXD0

PHY_RXER33 PHY_RXCTL_RXDV

PHY_RXCLK3

PHY_COL3PHY_CRS3PHY_RSET

PHY_COMAPHY_INT3

3 PHY_MDC3 PHY_MDIO

3 2

4 1 X1

25.00MHZ

50PPM

127

122

117

106

104

96

97

908578

71

645952

65

9

87

82818079

115

54

95

1009998

9291

35

47

57

62

33

128126125

124123121

8

113

110109

67

72

6968

18192024

2526

29

13

105107

70

7

3

4

10

43

4934

14

16

41

3936373231

28

120

114

112

88

86

118

73

44

2327

171262

5

119116111108

103102101

93848366

636058

1

152122

4038

45485155

3011

77

7675

50

74

94

42

46

56

61

53

89

U46M88E1111

3

2

6

4

5

8

7

9

1

10 SH1

SH2

P1

RJ45

21

FERRITE-220

F1

1 2 3 4

5678

CP7

0.01UF

16V

X7R

8 7 6 5

4321

X7R

16V

0.01UF

CP8

8 7 6 5

4321 X5R

10V

0.1UF

CP2

1 2 3 4

5678

CP1

0.1UF

10V

X5R

76

5%

4.7K

RP3

1

2

R154.7K

1/16W5%

2

1

5%1/16W

4.7KR14

1

2

R2474.99K1%

10

6

5%

4.7K

RP3

3 PHY_RESET

NCNC

XTAL2_25MHZ_ENET11

PHY_CONFIG0112

1

5%0R214

NC

2

1 C265

22PF50VNPO

1

2NPO50V22PF

C266

NC

PHY_AVDD0

PHY_AVDD0

PHY_AVDD0

PHY_AVDD0

MDIP0_CAP

68

RP3

4.7K

5%

45

5%47

RP2

36

RP2

475%

27

5%47

RP2

18

RP2

475%

96

5%

4.7K

RP3

45

RP1

475%

36

5%47

RP1

27

RP1

475%

18

5%47

RP1

15

RP3

4.7K

5%

41

5%

4.7K

RP3

13

RP3

4.7K

5%

21

5%

4.7K

RP3

NC

MDIP3_CAP MDIP1_CAPMDIP2_CAP

PHY_MDIN0_N

PHY_MDIN1_N

2

1 C1410.01UF

16VX7R

1

2X7R50V

1000PFC2262

1 C2241000PF

50VX7R

1

2X7R50V

1000PFC225

NC

1

2 X7R16V

0.01UFC142

PHY_MDIP0_P

PHY_MDIP1_P

PHY_MDIP2_P

1

2 X7R16V

0.01UFC140

2

1 C1430.01UF

16VX7R

NC

NC

NC

NC

2

1 C2271000PF

50VX7R

2

1 C2281000PF

50VX7R

PHY_MDIN3_NPHY_MDIP3_P

PHY_MDIN2_N

NC

PHY_AVDD0

1 2

R1

1M

1/8W

5%

NCNC

1

2

R47DNP

1/16W1%

215%1/16W150 R213

215%1/16W150 R212

215%1/16W150 R211

1 2

R2101501/16W 5%

1 2

R2091501/16W 5%

1 2

R2081501/16W 5%

PHY_LED_LINK1000_R

PHY_LED_DUPLEX_R

NCNC

NCNC

NCNC

11

PHY_LED_RX

PHY_LED_RX

Page 12: Xilinx XTP067 - SP605 Schematics

VCC2V5VCC3V3

VCC3V3

VCC3V3

VCC3V3

21_GND22_GND23_GND24_GND25_GND26_GND27_GND28_GND29_GND30_GND

TDN_19TDP_18

VCCT_16VCCR_15

RDP_13RDN_12

LOS_8RATE_SELECT_7

MOD_DEF0_6MOD_DEF1_5MOD_DEF2_4TX_DISABLETX_FAULT_2

31_GND

VEET_20VEET_17

VEER_14

VEER_10VEER_11

VEER_9

VEET_1

VCC3V3

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

PCIE_1LANE_EDGE

GND

+3.3V

+3.3V

+12V

GND

+12V

SMCLK

SMDAT

+3.3Vaux

WAKE#

KEY

GND

GND

GND

+12V

PRSNT#1

+12V

GND

+12V

GND

JTAG1/TRST#

JTAG2/TCK

JTAG3/TDI

JTAG4/TDO

JTAG5/TMS+3.3V

PRSNT#2

PERST

KEY

REFCLK+

REFCLK-

GND

PETp0

PETn0

PERp0

PERn0

GND

RESERVED

SP605 EVALUATION PLATFORM

3

Silkscreen:"SFP OK"

"SFP EN"Silkscreen:

"RT_SEL""LOW BW"

"FULL BW"1

Silkscreen:

SFP_LOS

SFP MODULE

Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

SCHEM, ROHS COMPLIANT

PCIe 1X Card Edge, SFP

PCIe 1X Card Edge, SFP

> 50K pullup

BF

D

12 35

9-24-2009_15:00

04

1 2X5R

10V

0.1UF

C27

NC

SFP_TX_DISABLE_FPGA4

2IIC_SCL_SFP

2IIC_SDA_SFP

A1

A10

A11

A14

A15

A16

A17

A2

A3

A4

A5

A6

A7

A8

A9

B10

B11

B15

B16

B17

B18

B2

B3

B5

B6

B7

B8

B9

B1

B4

B14

A18

B12

B13

A12

A13

P4

2

1

1%1/16W

DNPR16

NC 1

2

R48DNP

1/16W1%

28PCIE_CLK_QO_P

28PCIE_CLK_QO_N

PCIE_PRSNT_B12

6PCIE_TX0_P

6PCIE_TX0_N

6 PCIE_RX0_N

PCIE_RX0_P6

PCIE_TX0_C_P

NC

NC

NC

35PCIE_PERST_B

1 2X5R

10V

0.1UF

C26

1 2

R55

15

1/16W

5%

PCIE_TX0_C_N

NC

NC

NC

NC

NC

NC

NC

12PCIE_PRSNT_B

NC

NC

NC

NC

NC

21222324252627282930

1918

16 1312

8765432

31

2017

14

1011

9

1

15

P2

SFP_CONN_CASE

1

2R105

4.75K

1%

2

1

1%

4.75K

R104

1J16

1

2X5R10V

0.1UFC32

1 2 3 4

5678

CP3

0.1UF

10V

X5R

21

FERRITE-220

F4

1 2

F208

FERRITE-220

1 2 3

J22

2 1

J44

2

1 C310.1UF

10VX5R

2

1

X5R10V

10UFC198

2

1

X5R10V

C300.1UF

2

1C19710UF

10VX5R

1J15

1J14

1

2R103

4.75K

1%

2

1

1%

4.75K

R102

2

1

1%

4.75K

R101

1

2R100

4.75K

1%

SFP_TX_FAULT

SFP_LOS

3

SFP_RX_N 6

SFP_TX_N 6SFP_TX_P 6

SFP_RX_P 6

SFP_MOD_DETECT

SFP_VCCRSFP_VCCT

SFP_RT_SEL

NC

Page 13: Xilinx XTP067 - SP605 Schematics

GND1GND2GND3GND4GND5GND6GND7

SIG

GND1GND2GND3GND4GND5GND6GND7

SIG

GND1GND2GND3GND4GND5GND6GND7

SIG

GND1GND2GND3GND4GND5GND6GND7

SIG

GND1GND2GND3GND4GND5GND6GND7

SIG

GND1GND2GND3GND4GND5GND6GND7

SIG

GND1GND2GND3GND4GND5GND6GND7

SIG

GND1GND2GND3GND4GND5GND6GND7

SIG

GND1GND2GND3GND4GND5GND6GND7

SIG

GND1GND2GND3GND4GND5GND6GND7

SIG

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

SP605 EVALUATION PLATFORM Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

SCHEM, ROHS COMPLIANT

SMA MGT Connectors

MGT REFCLK USER SMA CLOCK

USER SMA GPIO

SMA Connectors

SMA Connectors

D

04

3513

9-18-2009_15:04

BF

2345678

1

J35 32K10K-400E3

2345678

1

32K10K-400E3J34

USER_SMA_CLOCK_N3

USER_SMA_GPIO_P2USER_SMA_GPIO_N2

USER_SMA_CLOCK_P3

1

8765432

32K10K-400E3J36

6 SMA_REFCLK_N6 SMA_REFCLK_P

SMA_RX_C_N

SMA_RX_C_P21

0.1UF

C33

10V

X5R

1 2X5R

10VC34

0.1UF

6 SMA_RX_N6 SMA_RX_P

2345678

1

J33 32K10K-400E3

2345678

1

32K10K-400E3J32SMA_TX_P6SMA_TX_N6

SMA_REFCLK_C_N

1

8765432

J37 32K10K-400E3

210.1UF

C36

10V

X5R

1 2X5R

10VC35

0.1UF

SMA_REFCLK_C_P

2345678

1

32K10K-400E3J41

1

8765432

J40 32K10K-400E3

1

8765432

32K10K-400E3J39

2345678

1

J38 32K10K-400E3

Page 14: Xilinx XTP067 - SP605 Schematics

VCC3V3

VCC2V5

VCC1V5_FPGA

VCC1V5_FPGA

VCC1V5_FPGA

VCC1V5_FPGA

VCC1V5_FPGA

VCC2V5

VCC2V5

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC2V5

VCC2V5

P2

P1

P3

P4

Pushbutton

P2

P1

P3

P4

Pushbutton

P2

P1

P3

P4

Pushbutton

VCC2V5

VCC2V5

VCC1V5_FPGA

VCC2V5

GND

OE

OUT

VCC

OSC

P2

P1

P3

P4

Pushbutton

P2

P1

P3

P4

Pushbutton

P2

P1

P3

P4

Pushbutton

VCC3V3

SI500D

NCGND

VCCOUT_BOUT

OE

HDR_1x6

NCGND

VCCOUT_BOUT

OE

Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

NC pins connected

SCHEM, ROHS COMPLIANTSP605 EVALUATION PLATFORM

Single Ended User Clock

Clocks, LEDs, Buttons, Switches

Clocks, LEDs, Buttons, Switches

(Alternate Package)

INIT_B = 0, LED: ONINIT_B = 1, LED: OFF

to line upoverlayed footprints

Differential System Clock

23

654

1U6

200MHZ

BF

04

3-17-2010_9:23

3514

D

1

2

3

4

5

6

J55

HDR_1X6

2

1

5%1/16W

0R215

23

654

1U9

GPIO_HEADER_335

35 GPIO_HEADER_2

GPIO_HEADER_135

GPIO_HEADER_035

21

5%

1/16W

200

R281

1 2

R280

200

1/16W

5%

4

3

1

2

SW8

1

2

R226

1.00K

1/16W

1%

1

2

R7027.4

1/16W1%

1

2

R169332

1/16W1%

21

DS2

LED-GRN-SMT

1

2

R230

1.00K

1/16W

1%

4

3

1

2

SW6

1

2

R174.7K

1/16W5%

2

1

3

4

SW3

4

1

5

8

X2

110880

2

1 C380.1UF

10VX5R

1

2

R69

75.0 1%

21

DS17

LED-RED-SMT

5678

4321

S2

SDMX-4-X

3,14SYSCLK_P3,14SYSCLK_N

3,14SYSCLK_P3,14SYSCLK_N

FPGA_INIT_B4,20

2

1

1%1/16W

27.4R74 1

2

R7327.4

1/16W1%

1

2

R7127.4

1/16W1%

2

1

5%1/16W

4.7KR19

4

3

1

2

SW5

2

1

3

4

SW7

4

3

1

2

SW4

1

2 X5R10V

0.1UFC37

USER_CLOCK 4

FPGA_PROG_B7,18,20

GPIO_LED_34

GPIO_LED_23

GPIO_LED_14

GPIO_LED_02

5 GPIO_BUTTON0

GPIO_BUTTON15

GPIO_BUTTON25

GPIO_BUTTON35

FPGA_DONE7

GPIO_SWITCH_35GPIO_SWITCH_24GPIO_SWITCH_14GPIO_SWITCH_02

21

DS3

LED-GRN-SMT

12

LED-GRN-SMT

DS4

21

DS5

LED-GRN-SMT

12

LED-GRN-SMT

DS6

1

2

R49DNP

1/16W1%

1

2

R184.7K

1/16W5%

CPU_RESET5

1

2

R7227.4

1/16W1%

1

2

R222

1.00K

1/16W

1% 2

1

1%

1/16W

1.00K

R223

1

2

R224

1.00K

1/16W

1% 2

1

1%

1/16W

1.00K

R225

1

2

R227

1.00K

1/16W

1%

1

2

R228

1.00K

1/16W

1%

1

2

R229

1.00K

1/16W

1%

1 2

R282

200

1/16W

5%

21

5%

1/16W

200

R283

Page 15: Xilinx XTP067 - SP605 Schematics

VCC5

VCC3V3

VCC2V5

VCC3V3

VCC3V3

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

REGIN

CN

R_G

ND

RT

S_O

_B

DT

R_O

_B

DC

D_I

_B

NC

1

NC10

NC

2

NC

3NC4

GPIO3

GPIO2

GPIO1

GPIO0

NC9R

ST

_B

RX

D_I

TX

D_O

SU

SP

EN

D

SU

SP

EN

D_B

DS

R_I

_B

VB

US

VDD

CT

R_G

ND

CT

S_I

_B

D+

D-

GND1

VIO

RI_I_B

SCLSDA

A0A1A2

WP

VCCGND

GND

SHLD4

VBUS

D_N

D_P

SHLD1

SHLD2

SHLD3

ID

USB_MINI_B

(Approx 3.1V)

BatteryRechargeable

Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

Bridge

USB to RS232

SCHEM, ROHS COMPLIANTSP605 EVALUATION PLATFORM

Fiducials

CP2103 USB Self-Powered

(26mA max)

CP2103GM

The VIO voltage must match the appropriate bank IO voltage

UART, IIC Header/EEPROM

UART, IIC Header/EEPROM

IIC Address 0b1010100

D

15 35

9-24-2009_15:00

04

BF

2

1

5%0R50

2

1 R216DNP

1/16W1%

1 2

R292 0

1/16W5%

21

5%

1/16W0

R291

2

1

5%1/10W

1.0KR6

IIC_SDA_MAIN3,10,15IIC_SCL_MAIN3,10,15

M4

M3

NC

5

9

1

2

3

678

4

J23

FPGA_VBATT7

12

H-1X2 J45

65

123

7

84

U4

M24C08-WDW6TP

7

29

23

27

28

10

21

13

14

15

16

17

18

19

209

24

25

12

11

26

8

6

30

22

3

4

2

5

1

U30

CP2103GM

M2

1

M6

M1

1

M5

IIC_SCL_MAIN3,10,15 IIC_SDA_MAIN 3,10,15

1

2 X5R10V

0.1UFC39

2

1C163

1UF6.3VX5R

1

2X5R6.3V1UF

C164

2

1C410.1UF

10VX5R

USB_1_DATA_N

NC

1

2 3

4

X3

SP0503BAHT

225MW

NC

2

1

5%1/16W

4.7KR20

2

1 C400.1UF

10VX5R

1

2

R51.0K

1/10W5%

NC NC

NCNCNC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

USB_1_VBUS

USB_1_DATA_P

USB_1_TX 3

3USB_1_RX

3USB_1_RTS

3USB_1_CTS

NC

1

2

R2794.75K1%

1

2

R2781.54K1%

2

1

3D11BAS40-04

40V200MA

2

1

B2

NC

NC

Page 16: Xilinx XTP067 - SP605 Schematics

VCC2V5

VCC5

VCC5

VCC5

VCC5

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

GND_VIDEO

GND_VIDEO

GND_VIDEO

GND_VIDEO

GND_VIDEO

GND_VIDEO

VCC5

SH_GND1SH_GND2

AGND1

BLUEGREENRED

DATA0_NDATA0_P

DATA5_NDATA5_P

CLK_PCLK_N

DATA3_N

DATA1_PDATA1_N

DDC_DATADDC_CLK

DATA4_PDATA4_N

DATA2_PDATA2_N

VS

SHIELD_CLKSHIELD_0/5SHIELD_1/3SHIELD_2/4

HS

DATA3_P

GND0

VCC5

HPDET

AGND0

DVI_CONN

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

To Video Codec

DVI Bus

To IIC

To Video Codec

To Video Codec

DVI VIDEO CONNECTOR

SP605 EVALUATION PLATFORMSCHEM, ROHS COMPLIANTDVI VIDEO CONNECTOR

3516

04

9-18-2009_15:03

BF

D

IIC_SDA_DVI_F

2

1 C42

0.1UF10VX5R

2526

C6

C3C2C1

1718

2021

2324

12

109

76

54

21

8

2219113

C4

13

15

14

16

C5

P3

DVI_CONN

IIC_SCL_DVI4,17

21

3

200MA 40V

BAS40-04

D7

3

12

D6

BAS40-04 40V200MA

21

3

200MA 40V

BAS40-04

D5

21

3

200MA 40V

BAS40-04

D3

3

12

D2

BAS40-04 40V200MA

21

3

200MA 40V

BAS40-04

D1

2

1

1%75

.0

R12

1

DVI_VSYNC17

DVI_CONN_HSYNC

DVI_CONN_HPDET

1 2

F8

FERRITE-220

21

FERRITE-220

F9

DVI_GREEN17

DVI_HSYNC17

DVI_HPDET17

IIC_SDA_DVI4,17

DVI_GRN_TMP

12

R250

1%1.21K

1

2

R602.43K1%

2

1

1%2.43KR59

2

1 C267

22PF50VNPO

3

12

D8

BAS40-04 40V200MA

3

12

D4

BAS40-04 40V200MA

2 3

1NDS331N

Q7

1

32

Q8

NDS331N

21

FERRITE-220

F7

1 2

F6

FERRITE-220

IIC_CLK_DVI_F

1

2X7R50V270PF

C285

2

1 C284

270PF50VX7R

21

5%330MA

82NHL6

1 2

L582NH

330MA 5%

1 2

L182NH

330MA 5%

21

5%330MA

82NHL4

21

5%330MA

82NHL2

1 2

L382NH

330MA 5%

DVI_CONN_BLUE

2

1 C283

33PF50VNPO

1

2NPO50V33PF

C282

2

1 C281

33PF50VNPO

1

2NPO50V22PF

C274

1

2NPO50V22PF

C268

2

1 C269

22PF50VNPO

1

2X5R10V0.1UF

C43

1

2NPO50V22PF

C270

2

1 C272

22PF50VNPO

1

2NPO50V22PF

C271

2

1 C273

22PF50VNPO

DVI_BLUE_TMP

DVI_CONN_RED

DVI_RED_TMP

DVI_CONN_GREEN

NC

DVI_D2_N17 DVI_D2_P17

NCNC

DVI_D1_N17 DVI_D1_P17

NC

DVI_CLK_N17

DVI_CLK_P17

NCNC

DVI_D0_P17

DVI_D0_N17

DVI_RED17

DVI_BLUE17

1

2

R12

2

75.0

1%

2

1

1%75

.0

R12

3

DVI_CONN_VSYNC

Page 17: Xilinx XTP067 - SP605 Schematics

VCC2V5

GND_VIDEO

GND_VIDEO

GND_VIDEO

VCC3V3

VCC5

VCC3V3

VCC2V5

EN

GND

IN

NR_FB

OUT

NC0

TGND3

DVDD1DVDD2

DGND2DGND3

TVDD1TVDD2

TGND1TGND2

G B

D10D11

D1D2D3D4D5D6D7D8D9

XCLK_P

DEHV

SPDSPC

GPIO1GPIO0AS

TDC0_P R

VSYNC

HSYNC

HPDET

TLC_N

TLC_P

TDC2_P

TDC2_N

TDC1_P

VSWING

NC1

NC5

GND2GND1

VDD

AGND2

NC3

NC4

NC2

RESET_B

D0

XCLK_N

ISET

TDC0_N

TDC1_N

DVDD3

AVDD

DGND0

VREFDVDDV

NC6

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

SP605 EVALUATION PLATFORM Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

DVI_AS

IIC Address = 0x76

To DVI Connector

Near DVI IC

(3.3V)

DVI CODEC

Place termination RPs near FPGA

D

BF35

9-18-2009_15:03

1704

SCHEM, ROHS COMPLIANT,DVI CODEC

21R130

100

1/16W

5%

DVI_XCLK_P3

IIC_SCL_DVI4,16

IIC_SDA_DVI4,16

3 DVI_GPIO1

3 DVI_V3 DVI_H3 DVI_DE

DVI_XCLK_N3

DVI_RESET_B3

3 DVI_D03 DVI_D13 DVI_D23 DVI_D3

3 DVI_D43 DVI_D5

DVI_D633 DVI_D7

3 DVI_D83 DVI_D9

DVI_D1033 DVI_D11

2

1

1%2.43KR611

2

R632.43K1%

2

1

1%2.43KR64

1

2

R1921401%

2

1

1%2.43KR62

1

2X5R10V0.1UF

C45 1

2

C202

10UF10VX5R

21

FERRITE-220

F193

1 2

F69

FERRITE-220

21

FERRITE-220

F11

2

1X5R10V10UF

C201

2

1 C44

0.1UF10VX5R

1

2X5R10V0.1UF

C48

2

1 C49

0.1UF10VX5R

1

2

C200

10UF10VX5R

1 2

F10

FERRITE-220

21

FERRITE-220

F192

2

1

1%4.75KR106

1

2

R1074.75K1%

1

2X5R10V0.1UF

C51

2

1 C46

0.1UF10VX5R

1

2X5R10V0.1UF

C47

16

32

112

1164

2329

2026

37

39

5150

626160595855545352

57

245

1415

78

10

22

38

47

48

931

30

28

27

25

19

36

44

4034

33

17

4243

41

13

63

56

35

21

24

49

18

6

345

46U31

CH7301C-TF

2

1 C258

DNP

2

1 C148

0.01UF16VX7R

1

2X5R10V1UF

C1333

2

1

4

5

U10

TPS73633DBVT

1 2

R36

47.5

1/16W

1%

21

1%1/16W

47.5

R32

1 2

R33

47.5

1/16W

1%

21

1%1/16W

47.5

R34

1 2

R28

47.5

1/16W

1%

21

1%1/16W

47.5

R31

1 2

R30

47.5

1/16W

1%

21

1%1/16W

47.5

R29

DVI_VCCA 17DVI_VDD

DVI_AVDD DVI_VCCA 17

DVI_TVDD

DVI_DVDD

DVI_VCCA 17

2

1X5R10V10UF

C199

2

1 C50

0.1UF10VX5R

NC

NC

DVI_D1_N 16

DVI_D0_N 16

NC

NCNC

NCNC

DVI_D1_P 16

DVI_D2_N 16DVI_D2_P 16

DVI_CLK_P 16DVI_CLK_N 16

DVI_HPDET 16

DVI_HSYNC 16DVI_VSYNC 16DVI_RED 16

DVI_D0_P 16

DVI_BLUE 16

DVI_GREEN 16

NC

1 2

R35

47.5

1/16W

1%

21

1%

1/16W

47.5

R39

1 2

R38

47.5

1/16W

1%

21

1%

1/16W

47.5

R37

21

1%

1/16W

47.5

R40

1 2

R41

47.5

1/16W

1%

21

1%

1/16W

47.5

R42

Page 18: Xilinx XTP067 - SP605 Schematics

VCC3V3

VCC3V0

VCC2V5

HDR_1x6VCC2V5

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC3V3

NC7NC6

NC4NC5

NC3NC2

IO0_DINCLK

CS_BIO1_DOUT

VCCIO3_HOLD_B

GNDIO2_WP_B

NC1NC0

SDMX-2-X

Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

SCHEM, ROHS COMPLIANTSP605 EVALUATION PLATFORM

SPI X4

SPI Select Jumper

SPI Selection

Mode pin DIP switches

Suspend Jumper

ON: SPI X4

OFF: SPI External

3V3

SPI Program Header

Silkscreen:

SPI, CMP, Mode, and Suspend

SPI, CMP, Mode, and Suspend

GNDTCKTDOTDITMS

1

2

4

3

SW1

D

04

9-24-2009_15:00

3518 BF

1 2

5%1/16W

100

R132

1413

1112

65

1516

78

21

109

43

U32W25Q64VSFIG

1

2

R7527.4

1/16W1%

12

LED-GRN-SMT

DS7

123456789

J17

H-1X9

1

2

R81.0K

1/10W5%

1

2

R91.0K

1/10W5%

12

H-1X2 J46

1

2

5%1/16W

1.8KR25

4,18,19FPGA_D2_MISO37,14,20FPGA_PROG_B

FPGA_D1_MISO2 4,18,19SPI_CS_B 4,18FPGA_MOSI_CSI_B_MISO0 4,18FPGA_D0_DIN_MISO_MISO1 4,18,19FPGA_CCLK 4,18

12

H-1X2 J47

SPIX4_CS_B18 SPI_CS_B 4,18

FPGA_M0_CMP_MISO 4,18

FPGA_CMP_MOSI 4

1

2

3

4

5

6

J3

DNP

2

1 R231.8K

1/16W5%

SPIX4_CS_B18

1

2

5%1/16W

200R138

1

2

R71.0K

1/10W5%

4,18FPGA_MOSI_CSI_B_MISO0FPGA_CCLK 4,18

FPGA_D0_DIN_MISO_MISO14,18,19

1

2X5R10V0.1UF

C52

4,18,19FPGA_D1_MISO2

21R131

100

1/16W

5%

2

1

1%1/16W

DNPR51

FPGA_M14FPGA_M0_CMP_MISO4,18

7 FPGA_SUSPEND

2

1

5%1/16W

4.7KR21

NC

FPGA_CMP_CS_B 7

FPGA_CMP_CLK 4

NC

3 FPGA_AWAKE

NCNC

NCNCNCNC

2

1R139200

1/16W5%

4,18,19FPGA_D2_MISO3

Page 19: Xilinx XTP067 - SP605 Schematics

VCC2V5

VCC1V8

VCC2V5

A22

VCC0

VSS1

DQ15

DQ9

VSS2

VSS0

VCC1

DQ0DQ1

DQ8

DQ2DQ3

DQ10DQ11

DQ4DQ5DQ6DQ7

DQ14DQ13DQ12

WE_BOE_BRFUCE_BWP_BADV_BWAIT

CLK

A1A2A3A4A5A6

A20

A24

A21

A23

A8A9

A19

A10

A18

A11

A17

A12

A16

A13A14A15

A7

VCCQVPP

RST_B

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

SP605 EVALUATION PLATFORM Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

"Strata FLASH""256 MBit"

Silkscreen:

SCHEM, ROHS COMPLIANT

Synchronous modenot supported

ASYNC. SRAM FLASH

ASYNC. SRAM FLASH

9-18-2009_15:03

3519 BF

D

04

FLASH_CLK

1

2

R108

1.00K

1/16W

1%

2

1 1%

1/16W

1.00K

R113

1

2R112

1.00K

1/16W

1%

2

1 1%

1/16W

1.00K

R111

1

2

R110

1.00K

1/16W

1%

2

1 1%

1/16W

1.00K

R109

10

13

28

54

37

31

12

33

34

36

35

39

41

40

42

47

49

51

53

52

50

48

14

32

27

30

15

46

56

45

29

25

24

23

22

21

16

26

11

9

19

8

17

7

18

6

55

5

1

4

3

2

20

38

43

44

U25JS28F256P30T95

FPGA_D2_MISO34,18

FPGA_D0_DIN_MISO_MISO14,18

3 FLASH_ADV_B

3 FLASH_WAIT

FLASH_CE_B3

FLASH_OE_B3

FLASH_WE_B3

4,7,10 FMC_PWR_GOOD_FLASH_RST_B

1

2X5R10V0.1UF

C53

1

2X5R10V0.1UF

C57

2

1X5R10V10UF

C203

2

1X5R10V10UF

C204

2

1 C54

0.1UF10VX5R

2

1

0.1UF

C55

10VX5R

2

1

10VX5R

0.1UF

C56

3FLASH_A23

FLASH_D74

FLASH_D34 FLASH_D44 FLASH_D54 FLASH_D64

FLASH_A203

FLASH_A193

FLASH_A103

FLASH_A123

FLASH_A143

FLASH_A163

FLASH_A43

FLASH_A63

FLASH_A173 FLASH_A183

FLASH_A03 FLASH_A13 FLASH_A23 FLASH_A33

FLASH_A53

FLASH_A73 FLASH_A83 FLASH_A93

FLASH_A113

FLASH_A133

FLASH_A153

4 FLASH_D9

4 FLASH_D10

4 FLASH_D11

4 FLASH_D12

4 FLASH_D13

4 FLASH_D14

4 FLASH_D15

4 FLASH_D8

NC

FLASH_A2133

FLASH_A22

FPGA_D1_MISO24,18

Page 20: Xilinx XTP067 - SP605 Schematics

VCC2V5

VCC2V5

VCC2V5

VCC2V5

VCC2V5

P2

P1

P3

P4

Pushbutton

3_D0427_D112_D03

49_D1048_D0923_D0247_D0822_D01

20_A0044_REG19_A0118_A0242_WAIT17_A0316_A0415_A0514_A0637_RDY/BSY12_A0736_WE11_A0810_A099_OEI8_A1032_CE27_CE1I31_D156_D0730_D145_D0629_D134_D0528_D12

50_GND

38_VCC13_VCC

46_BVD1

21_D00

45_BVD240_VS2

26_CD1

25_CD2

41_RESET39_CSEL

35_IOWR34_IORD

33_VS124_WP

43_INPACK

1_GND

PARTS=1LEVEL=STD

NC20NC19NC18NC17NC16

NC21NC22NC23NC24NC25

NC11NC12NC13NC14NC15

NC6NC7NC8NC9NC10

NC5NC4NC3NC2

CFD08CFD02CFD09

MPIRQMPCEMPA06MPA05MPA04MPD15MPD14MPD13MPD12MPD11MPD10MPD09MPD08MPD07MPD06MPD05MPD04MPD03MPD02MPD01MPD00MPA03MPA02MPA01MPA00MPWEMPOE

CFGINIT

CFGPROG

CFGADDR0

CFGADDR1

CFGADDR2

CLK

STATLED

ERRLED

TSTTMS

CFA07

CFA05

CFWAITCFA02

91_GND

100_GND

75_GND

83_GND

64_GND

54_GND

46_GND

120_GND

136_GND

129_GND

144_GND

9_GND

18_GND

26_GND

CFCD2CFD10

CFCD1CFD03CFD11CFD04CFD12CFD05CFD13CFD06CFD14CFD07CFD15CFCE1CFCE2CFA10

CFD01

CFA00

CFOECFA09CFA08CFWE

CFA06

CFA03

CFREGCFA01

CFD00

CFA04

CFGRSVD

111_GND

CFGMODEPIN

35_GND

VCCL_126

110_GND

112_GND

TSTTDO

TSTTCK

TSTTDI

CFGTCK

CFGTMS

CFGTDO

CFGTDI

POR_RESET

POR_TEST

POR_BYPASS

RESET_B

VCCH_128

VCCH_109

VCCH_73

VCCH_92

VCCH_55

VCCH_37

VCCH_17

VCCH_1

VCCL_99

VCCL_94

VCCL_84

VCCL_57

VCCL_25

VCCL_15

VCCL_10

MPBRDY

NC1

(DIE DOWN)TQFP144SYSTEMACE

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND OUT

TRI VCC SP605 EVALUATION PLATFORM Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

Failsafe Mode EnabledOR =

FPGA & CPUCombined

"System ACE"

"Status LED""System ACE"

Silkscreen

"Error LED"

PC4 Connector

SysACE Failsafe Mode Jumpers

Silkscreen:"SYSACE RESET"

System ACE CF

Silkscreen

Disable SysACEError LED

41

2 3

U29

33.000MHZ

50PPM

SCHEM, ROHS COMPLIANT,SYSTEM ACE CF

BF35

3-17-2010_9:23

2004

D

2 1

J60H-1X2

12

H-1X2 J48

7140383634

90122124127143

2829303132

2122232427

20191614

7811

414243444547484950515253565859606162636566676869707677

7879

868788

93959698

132

135

140141

91

100

7583645446

120

136

129

14491826

1312

103104105106107113114115116117118119138121

6

4

123125130131

134

139

3142

5

137

133

111

89

35

126

110

112

97

101

102

808582

81

72

74

108

33

128

109

73

92

55

37

17

199

94

84

57

25

15

10

39

2

U17XCCACE-TQ144I

NC

21

5%1/16W

180

R194

1 2

R193

180

1/16W

5% SYSACE_TDI 10

1

2R118

4.75K 1%

1

2R117

4.75K 1%

3272

4948234722

204419184217161514371236111098

327

316

305

294

28

50

3813

46

21

4540

26

25

4139

3534

332443

1

U37

N7E50-7516PG-202

1

1%

4.75K

R115

12

LED-RED-SMT

DS18

12

LED-GRN-SMT

DS8

1

2

C580.1UF

10VX5R

8 7 6 5

4321

X5R

10V

0.1UF

CP4

1 2 3 4

5678

CP5

0.1UF

10V

X5R

8 7 6 5

4321

X5R

10V

0.1UF

CP6

2 1H-1X2

J49

2

1

3

4

SW9

SYSACE_TMS_BUF 7SYSACE_TCK_BUF 7JTAG_TDO 32

7 FPGA_TMS

SYSACE_CFGMODEPIN20

4,14 FPGA_INIT_B

VCC3V3

SYSACE_RESET_B 20

SYSACE_RESET_B 20

FPGA_PROG_B7,14,18 SYSACE_ERR_LED 20

35 SYSACE_MPOE35 SYSACE_MPWE35 SYSACE_MPA0035 SYSACE_MPA0135 SYSACE_MPA0235 SYSACE_MPA0335 SYSACE_D035 SYSACE_D135 SYSACE_D235 SYSACE_D335 SYSACE_D435 SYSACE_D535 SYSACE_D635 SYSACE_D7

35 SYSACE_MPA0435 SYSACE_MPA0535 SYSACE_MPA06

35 SYSACE_MPIRQ35 SYSACE_MPCE

35 SYSACE_MPBRDY

CLK_33MHZ_SYSACE3

SYSACE_CFGADDR020

7 FPGA_TDI

7 FPGA_TCK

SYSACE_CFGTDI7

NC

SYSACE_CFGADDR220SYSACE_CFGADDR120

VCC3V3

1

2R251

1%

1.21K

NCNC

NC 2

1

1.21K

1%

R252

SYSACE_CFA00

SYSACE_CFA06

SYSACE_CFD00

SYSACE_CFD05

SYSACE_CFD10

SYSACE_CFDE

NC

SYSACE_ERR_LED

SA_ERR_RES

SA_STAT_RES SYSACE_STAT_LED

SYSACE_CFRDBSY

NCNCNCNCNCNC

NC

SYSACE_CFCD2

SYSACE_CFD09SYSACE_CFD02SYSACE_CFD08SYSACE_CFD01

SYSACE_CFREGSYSACE_CFA01SYSACE_CFA02SYSACE_CFWAITSYSACE_CFA03SYSACE_CFA04SYSACE_CFA05

SYSACE_CFA07SYSACE_CFWESYSACE_CFA08SYSACE_CFA09

SYSACE_CFA10SYSACE_CFCE2SYSACE_CFCE1SYSACE_CFD15SYSACE_CFD07SYSACE_CFD14SYSACE_CFD06SYSACE_CFD13

SYSACE_CFD12SYSACE_CFD04SYSACE_CFD11SYSACE_CFD03SYSACE_CFCD1

NC

NCNC

NCNC

NC

NC

NC

NCNC

NCNC

NC

NCNC

NCNC

NC

NCNC

VCC3V3

VCC3V3

VCC3V3

NCNCNCNCNCNCNCNC

NC

1

2R116

4.75K 1%

1

2R1194.75K 1%

NC

SYSACE_ERR_LED 20

1

2

R219

1.00K

1/16W

1%

1

2

R221

1.00K

1/16W

1%2

1

1%

1/16W

1.00K

R220

2

1

1%

1/16W

1.00K

R218

1

2

5%

1/16W

200

R136

2

1

R135

200

1/16W

5%

1

2

5%

1/16W

200

R134

2

1

R133

200

1/16W

5%

5678

4321

S1

SDMX-4-X

20 SYSACE_CFGMODEPIN

20 SYSACE_CFGADDR120 SYSACE_CFGADDR0

20 SYSACE_CFGADDR2

Page 21: Xilinx XTP067 - SP605 Schematics

9240AGND1

9240AGND1

9240DGND1

9240DGND1

9240AGND1

9240DGND1

VCC12_P

IN OUT

GNDTAB

GND

SNS_ADJSHDN_B

A4

A6

A

A7

A5

E_B

VEE

GND S2

S1

S0

A3

A0

A1

A2

VCC

VCC12_P

VCC5

/RESET

/TRST

ADC_REF

ADDRSEN0ADDRSEN1

AG

ND

1A

GN

D2

AG

ND

3

AUX-IN_AD13AUX-IN_AD14

BPCAP

CS-1ACS-1B

CS-2ACS-2B

CS-3ACS-3B

CS-4ACS-4B

DG

ND

1D

GN

D2

DG

ND

3

DIAG-LED

DPWM-1ADPWM-1B

DPWM-2ADPWM-2B

DPWM-3ADPWM-3B

DPWM-4ADPWM-4B

EAN1

EAN2

EAN3

EAN4

EAP1

EAP2

EAP3

EAP4

FAN-PWMFAN-TACH

FAULT-1AFAULT-1B

FAULT-2AFAULT-2B

FAULT-3AFAULT-3B

FAULT-4AFAULT-4B

PMBUS_ALERT

PMBUS_CLKPMBUS_CTRL

PMBUS_DATA

PWRGOOD

SRE-1ASRE-1B

SRE-2ASRE-2B

SRE-3ASRE-3B

SRE-4ASRE-4B

SYNC-INSYNC-OUT

TCK

TDITDO

TEMP

TMS

TMUX0TMUX1TMUX2

TRCK

V33

AV

33D

V33

DIO

1V

33D

IO2

V33

FB

VIN

VTRACK

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

0603_SHORT9240AGND1

9240DGND1

9240AGND1

9240DGND1

9240AGND1

9240AGND1

9240AGND1

9240AGND1

9240AGND1

9240AGND1

0603_SHORT

PMBus Address is calculated as follows:

ADDRSENxRPMBusValue

11109876543210Short

Open -

-

Note:

158k115k84.5k63.4k47.5k36.5k

210k

27.4k21.5k16.9k13.0k10.2k

PMBus Address = 12 × Value(ADDRSEN1) + Value(ADDRSEN0)

Example: ADDRSEN1 R=27.4k and ADDRSEN0 R=27.4k

PMBus Address = (12 x 4) + 4 = 52 decimal

Do not use PMBus Addresses 0, 1, 2, 3, 12, 126 or 127

SP605 EVALUATION PLATFORM Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

5V @ 1.5A

VCCxxxx_EAP/N are remote sense

pairs wired back from power plane

PMBus Connector

connections at FPGA

FPGA PMBus Regulator Shutdown(shuts off regulators)

FPGA UCD9240 PMBus Controller

TI UCD9240 Power SystemSCHEM, ROHS COMPLIANT

AGND should be a copper island underneaththe 9240 and every associated module

04

D

BF21 35

9-24-2009_15:00

1

2Y5V16V4.7UF

C393

1

2

5%1/16W

2.0KR201

2

1 R2022.0K

1/16W5%

1 2Z3

VCC3V3A

VCC3V3A

TI_V3P3

1

2X5R10V0.1UF

C63

1

2

R14810.0K

1/16W1%

21 Z1

21

FERRITE-220

F268

1

2X5R10V0.1UF

C3972

1 C61

0.1UF10VX5R

1

2X7R16V0.1UF

C395

2

1 C249

0.1UF16VX7R

1

2X7R16V0.1UF

C153

2

1X5R16V10UF

C130

TI_V3P3

26VCC1B_FLT

VCC3B_FLT26

VCC4B_FLT26

21

5%

1/16W0

R293

21

5%

1/16W0

R294

21

5%

1/16W0

R295

24VCC3A_FLT

1 2

R296 0

1/16W

5%

1 2

R286

1.00K

1/16W

1%

22VCC1A_FLT

2

1X5R10V4.7UF

C286

2

1

1%1/16W

27.4KR1701

2

R9927.4K

1/16W1%

1

2

R15110.0K

1/16W1%

1

2J8 DNP

2

1

J7 DNP

PWR_INH 22,23,24,29,30

1

2

R772.15K

1/16W1%

NC

NC

NCNC

NC

TEMP3 24

1

2X5R10V0.068UF

C219

VCC3A_CS 24VCC3_EA_N 24VCC3_EA_P 24

NC24VCC3A_SRE

NCVCC3A_PWM 24

97

1 235 6

4

810

J1

HDR_BOX_2X5

1

32

Q11

2

1

1%1/16W

10.0KR154

1 2

R141

2.0K

1/16W

5%

4,26 PMBUS_DATA2,26 PMBUS_ALERT

4,26 PMBUS_CLK

25TI_PWRGOOD

25FAN_TACH

13

48

1

7776

616080

7271

59

7579

478

374

273

9 3455

10

2122

2324

2526

2728

63

65

67

69

62

64

66

68

5332

1516

1718

2941

4243

35

1936

20

49

1211

5137

3852

3350

3130

44

4645

7

47

394054

14

58

578

56

70

5

6

U26

UCD9240PFC

VCC2A_FLT 23

VCC2A_SRE 23

23VCC2A_PWM

3,26 PMBUS_CTRL

2

1 C294

0.47UF10VX5R

1 2

R76

6.81K

1/16W

1%

2

1 C250

0.1UF16VX7R

NC

NC

TI_RESET_B

1

2X5R10V0.068UF

C218

1

2J10

1

2

R224.7K

1/16W5%

TI_V3P3

2

1

J9

21C287

4.7UF

10V

X5R

1

2

R15310.0K

1/16W1%

TI_V3P3

2

1

1%1/16W

10.0KR152

21

D12

BZT52C5V1-TP

5.1V

500MW

1 2

R231

1.00K

1/16W

1%

1

2

R2461.0M

1/16W5%

2

1

1%1/16W

10.0KR1501

2

R14910.0K

1/16W1%

2

1 C152

0.01UF16VX7R

1

2X5R10V0.1UF

C62

2

1 C60

0.1UF10VX5R

1

2

1%1/16W

10.0KR147

1

2

1%1/16W

10.0KR146

1234

J5

DNP

21

C59

0.1UF

10V

X5R

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16U2

CD74HC4051

2

1 C217

0.068UF10VX5R

NCNC

VCC1A_CS 22NC

NC

NCNC NC

TEMP1 22

23TEMP2

21TMUX0

21TMUX1

TMUX2 21

NC

TEMP21

NC

NC

NC

NC

21 TMUX2TMUX121

21 TMUX0

21 TEMP

VCC1A_SRE 22

25FAN_PWM

VCC2_EA_P 23

VCC1_EA_P 22

23VCC2_EA_N

VCC1_EA_N 22

VCC1A_PWM 22

NC

TRST_B

TI_TDOTI_TDITI_TMSTI_TCK

NC

NC

2 4

63

51

U5TL1963AKTTR

NC

NC NC

VCC2A_CS 23

21

1%1/16W

1.00K

R287

2

1 C220

0.068UF10VX5R

NC

21

FERRITE-220

F273

VCC2B_FLT26

1

2 1/16W5%2.0KR203

Page 22: Xilinx XTP067 - SP605 Schematics

0.005R1W0.1%

I2I1

E1 E2

VCCINT

VCC12_P

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCINT_FPGA

VCCINT_FPGA

VCC5

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

INH

FAULT

SRE

PWM

GND_1

GND_0

TEMP

IOUT

AGND

VOVI

VBIAS

AGND1

0603_SHORT

SP605 EVALUATION PLATFORM Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

<=1.5V : DNP>1.5V = 787 ohms

VCCINT @ 10A

SCHEM, ROHS COMPLIANT

PTD08A010W 10A Max. Power Channel

PTD08A010W 10A Max. Power Channel

04

D9-18-2009_15:03

3522 BF

1 2Z4

8910

11

32 5 6 7

41

12

U18

PTD08A010W

4 5

63

2 7

81

INA333

U38

2

1 C275

820PF25VX7R

1

2

R52DNP

1/16W1%

21

1%1/16W

1.00K

R234

1

2

C235330UF

16VELEC

VCC1_SENSE_P

21

1%

1/16W

4.22K

R43

1

2

C229330UF

10VTANT

VCC1_SENSE_N

2

1 C134

22UF25VX5R

1

2

C24247UF

6.3VTANT

21 VCC1_EA_N

VCC1_EA_P21

21VCC1A_CS

TEMP121

21VCC1A_FLT21VCC1A_SRE

VCC1A_PWM 21

21,23,24,29,30PWR_INH

NC

E1 E2

I1 I2

R67

Page 23: Xilinx XTP067 - SP605 Schematics

INH

FAULT

SRE

PWM

GND_1

GND_0

TEMP

IOUT

AGND

VOVI

VBIAS

VCC5

VCC2V5

VCC12_P

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC2V5_FPGA

VCC2V5_FPGA

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

0.005R1W0.1%

I2I1

E1 E2

AGND2

0603_SHORT

SP605 EVALUATION PLATFORM Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

<=1.5V : DNP>1.5V = 787 ohms

VCC2V5 @ 10A

PTD08A010W 10A Max. Power Channel

SCHEM, ROHS COMPLIANTPTD08A010W 20A Max. Power Channel

BF23 35

9-18-2009_15:03 D

04

1 2Z5

I2I1

E1 E2

R68

4 5

63

2 7

81

INA333

U39

1 2

R240

2.2K

1/16W

5%

1

2

R261.8K

1/16W5%2

1 C276

820PF25VX7R

1

2

C236330UF

16VELEC

1

2

C24347UF

6.3VTANT

1

2

C230330UF

10VTANT

21

1%

1/16W

4.22K

R44

21VCC2A_FLT21VCC2A_SRE

VCC2A_PWM 21

TEMP221

NC

21,22,24,29,30PWR_INH

VCC2_EA_P21

21 VCC2_EA_N

2

1 C135

22UF25VX5R

VCC2_SENSE_P

VCC2_SENSE_N

21VCC2A_CS8910

11

32 5 6 7

41

12

U19

PTD08A010W

Page 24: Xilinx XTP067 - SP605 Schematics

VCCAUXVCC12_P

INH

FAULT

SRE

PWM

GND_1

GND_0

TEMP

IOUT

AGND

VOVI

VBIAS

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCAUX

0.005R1W0.1%

I2I1

E1 E2

VCC5

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

AGND3

0603_SHORT

SP605 EVALUATION PLATFORM Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

VCCAUX @ 10A

<=1.5V : DNP>1.5V = 787 ohms

PTD08A010W 10A Max. Power Channel

SCHEM, ROHS COMPLIANTPTD08A010W 10A Max. Power Channel

04

D

BF24 35

9-24-2009_15:00

1 2Z6

1 8

72

3 6

54

U40

INA333

1

2

R54787

1/16W1%

21

1%1/16W

1.00K

R235

2

1 C277

820PF25VX7R

I2I1

E1 E2

R65

VCC3_EA_P21

TEMP321

8910

11

32 5 6 7

41

12

U20

PTD08A010W

1 2

R45

4.22K

1/16W

1%

2

1

TANT6.3V

47UFC244 1

2

C231330UF

10VTANT

2

1 C136

22UF25VX5R

1

2ELEC16V

330UFC237

VCC3_SENSE_P

21VCC3A_CS

21VCC3A_FLT21VCC3A_SRE

VCC3A_PWM 21

NC

21,22,23,29,30PWR_INH

VCC3_SENSE_N

21 VCC3_EA_N

Page 25: Xilinx XTP067 - SP605 Schematics

VCC2V5

VCC12_P

VCC12_P

IN_P

VCC_N

OUT

IN_N

VCC_P

+ -

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

12V

5V

COM

COM

EC

B

DPDTG2

COM

N/C

12V

12V

N/C

COM

G1

SP605 EVALUATION PLATFORM Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

ATX Peripheral Cable

12V Power Jacks, 12V Fan

UCD9420 Fan Circuit

SP605 Power Good

TI UCD9240 Power SystemSCHEM, ROHS COMPLIANT

BF25 35

9-24-2009_15:00 D

04

VCC12_P_IN

1

32

N

NDS331N7

2

1

U7

SN74LVC2G08DCU

1

4

3

6

2

5

J18

39-30-1060

8

36

5

4

U7

SN74LVC2G08DCU

3

2

1

J42

NC1

32

4

65

SW21201M2S3ABE2

34

1 Q1MJD200

1

2

3

4

J27

350211-1

3

2

1

4

5

U36TS321IDBVR

2

1 C65

0.1UF10VX5R

1

2

R2371.00K

1/16W1% 2

1 C253

1UF16VX5R

TI_V3P3

1 2

R233.2K

1/16W

1%

1 2

R243

1.3K

1/16W

5%

1

2

R15510.0K

1/16W1%

21FAN_TACH

FAN_PWM21

NC

NC

21

DS14

LED-GRN-SMT

2

1

1%1/16W

1.00KR236

NC

NC

VCC3V3

2

1 R140200

1/16W5%

21

LED-GRN-SMT

DS9

1

2

C640.1UF

10VX5R

NC

MGT_TI_PWRGOOD26

TI_PWRGOOD21

NCNC

Page 26: Xilinx XTP067 - SP605 Schematics

9240DGND2

9240DGND2

VCC12_P

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

A4

A6

A

A7

A5

E_B

VEE

GND S2

S1

S0

A3

A0

A1

A2

VCC

9240AGND2

9240AGND2

0603_SHORT 0603_SHORT

9240AGND2

9240AGND2

/RESET

/TRST

ADC_REF

ADDRSEN0ADDRSEN1

AG

ND

1A

GN

D2

AG

ND

3

AUX-IN_AD13AUX-IN_AD14

BPCAP

CS-1ACS-1B

CS-2ACS-2B

CS-3ACS-3B

CS-4ACS-4B

DG

ND

1D

GN

D2

DG

ND

3

DIAG-LED

DPWM-1ADPWM-1B

DPWM-2ADPWM-2B

DPWM-3ADPWM-3B

DPWM-4ADPWM-4B

EAN1

EAN2

EAN3

EAN4

EAP1

EAP2

EAP3

EAP4

FAN-PWMFAN-TACH

FAULT-1AFAULT-1B

FAULT-2AFAULT-2B

FAULT-3AFAULT-3B

FAULT-4AFAULT-4B

PMBUS_ALERT

PMBUS_CLKPMBUS_CTRL

PMBUS_DATA

PWRGOOD

SRE-1ASRE-1B

SRE-2ASRE-2B

SRE-3ASRE-3B

SRE-4ASRE-4B

SYNC-INSYNC-OUT

TCK

TDITDO

TEMP

TMS

TMUX0TMUX1TMUX2

TRCK

V33

AV

33D

V33

DIO

1V

33D

IO2

V33

FB

VIN

VTRACK

9240DGND2

9240DGND2

9240AGND2

9240AGND2

9240DGND2

9240AGND2

9240AGND2

9240AGND2

PMBus Address is calculated as follows:

ADDRSENxRPMBusValue

11109876543210Short

Open -

-

Note:

158k115k84.5k63.4k47.5k36.5k

210k

27.4k21.5k16.9k13.0k10.2k

PMBus Address = 12 × Value(ADDRSEN1) + Value(ADDRSEN0)

Example: ADDRSEN1 R=27.4k and ADDRSEN0 R=27.4k

PMBus Address = (12 x 4) + 4 = 52 decimal

Do not use PMBus Addresses 0, 1, 2, 3, 12, 126 or 127

SP605 EVALUATION PLATFORM Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

VCCxxxx_EAP/N are remote sense

pairs wired back from power plane

connections at FPGA

FPGA UCD9240 PMBus Controller

TI UCD9240 Power SystemSCHEM, ROHS COMPLIANT

AGND should be a copper island underneaththe 9240 and every associated module

BF26 35

9-24-2009_15:00 D

04

MGT_VCC3V3A

MGT_VCC3V3A

13

48

1

7776

616080

7271

59

7579

478

374

273

9 3455

10

2122

2324

2526

2728

63

65

67

69

62

64

66

68

5332

1516

1718

2941

4243

35

1936

20

49

1211

5137

3852

3350

3130

44

4645

7

47

394054

14

58

578

56

70

5

6

U27

UCD9240PFC

1

2

R15810.0K

1/16W1%

1

2X5R10V0.1UF

C69

1 2Z721 Z2

MGT_TEMPXREF=26

MGT_TEMP26

1

2X7R16V0.1UF

C399

2

1 C251

0.1UF16VX7R

1

2Y5V16V4.7UF

C394

2

1X5R10V4.7UF

C289

30MGT_VCC4A_FLT

VCC1B_FLT 21

21VCC2B_FLT

21VCC3B_FLT

21VCC4B_FLT

1

2

R2736.5K

1/16W1%

1

2

R17127.4K

1/16W1%

1

2J12

DNP

2

1

J11

DNP

1 2

R238

1.00K

1/16W

1%

27MGT_VCC1A_CS

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16U3

CD74HC4051

26 MGT_TMUX2MGT_TMUX126MGT_TMUX026

26MGT_TMUX2

MGT_TMUX1 26

MGT_TMUX0 26

1

32

Q12

2

1

1%1/16W

10.0KR164

25MGT_TI_PWRGOOD

3,21 PMBUS_CTRLPMBUS_CLK4,21

4,21 PMBUS_DATA2,21 PMBUS_ALERT

NC

NC

29MGT_VCC3_EA_N29MGT_VCC3_EA_P

29MGT_VCC3A_FLT

29MGT_VCC3A_SRE

29MGT_VCC3A_PWM

NC

1234

J6

DNP

MGT_TI_TDOMGT_TI_TDIMGT_TI_TMS

MGT_TI_V3P32

1

J13

21C288

4.7UF

10V

X5R

1

2

R16310.0K

1/16W1%

2

1

1%1/16W

10.0KR162

21

D10

BZT52C5V1-TP

5.1V

500MW

1

2

R28410.0K

1/16W1%

2

1

1%1/16W

10.0KR1601

2

R15910.0K

1/16W1%

2

1 C155

0.01UF16VX7R

1

2X5R10V0.1UF

C68

2

1 C67

0.1UF10VX5R

2

1 C66

0.1UF10VX5R

1

2

1%1/16W

10.0KR157

1

2

1%1/16W

10.0KR156

MGT_TI_V3P3

MGT_TI_RESET_B

MGT_TRST_B

MGT_TI_TCK

NC

NC

NCNC

NCNC

2

1 C131

10UF16VX5R

21

C70

0.1UF

10V

X5R

2

1 C221

0.068UF10VX5R

NC

MGT_TEMP1 29

NC

NC

NC

MGT_TEMP2 30

NC

NC

30MGT_VCC4A_PWM

30MGT_VCC4A_SRE

30MGT_VCC4_EA_P30MGT_VCC4_EA_N

NC

NC

1 2

R142

2.0K

1/16W

5%

2

1 C259

6800PF25VX7R

MGT_VCC3A_CS 29

NC

NCNC

NCNC

NC

NC

NC

NCNC

NCNC

NC

NC

2

1 C323

6800PF25VX7R

1 2

R276

1.00K

1/16W

1%

1

2X7R16V0.1UF

C3961

2X5R10V0.1UF

C398

21

FERRITE-220

F276

21

FERRITE-220

F307

Page 27: Xilinx XTP067 - SP605 Schematics

C

E

B

3904

VCC5

0.005R1W0.1%

I2I1

E1 E2

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC5

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

TI

GND_TAB

NC_4

VIN_5

EN

VOUT_18

GND_12

NC_3

NC_2

NC_13

NC_14

NC_17

VIN_6

VIN_7

VIN_8

BIAS

VOUT_1

VOUT_19

VOUT_20

PG

FB

SS

SP605 EVALUATION PLATFORM Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

1.2V @ 3A

TPS74401 3A Max MGT Power

TPS74401 3A Max MGT PowerSCHEM, ROHS COMPLIANT

1

2

R2712.49K

1/16W1%

1

2

R2744.99K1%

04

D

BF

1-7-2010_17:04

3527

15

16

9

2019

1

10

876

17

14

13

23 12

18

11

5

4 21

TPS74401

U51

1 8

72

3 6

54

U50

INA333

MGT_VCC1A_CS 26

MGT_AVCC

VCC1V5

1

2X5R10V

0.1UFC2961

20.1UF

C295

10VX5R

1

2X5R10V

C302

1UF

1

2 X7R50V

1000PFC322

AUX_SS

AUX_FB

MGT_POWERGOOD

I2I1

E1 E2

R270

1 2

R259

4.22K

1/16W

1%

MGT_VCC1_SENSE_N

MGT_VCC1_SENSE_P

2

1 C31810UF10VX5R

2

1 C2970.1UF

10VX5R

1

2

3

Q13

MMBT3904

21

LED-GRN-SMT

DS19

1

2

R273200

1/16W5%

VCC3V3

Page 28: Xilinx XTP067 - SP605 Schematics

VCC3V3 VCC3V3

VCC3V3

VCC3V3 VDDA VDD

Q0GND

XTAL_OUT NQ0

OEXTAL_IN

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

PLL_SEL

NC1

NC2

NC3

MR

BW_SEL

F_SEL1

VDDA

VDD

F_SEL0

NC6

VDDO

Q

NQ

NC5

NC4

GND

NCLK

CLK

OE

SP605 EVALUATION PLATFORM

125.00 MHz Clock

Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

MGT Clocks

SFP Clock - 125MHz

MGT ClocksSCHEM, ROHS COMPLIANT

2

1 C320

10UF6.3VX5R

0805

04

D

BF

9-24-2009_15:30

3528

2

1

5%

1/16W

4.7K

R262

2

1

5%

1/16W

4.7K

R264

1

2

R255DNP

1/16W1%

1

2

R256DNP

1/16W1%

2

1

1%1/16W

DNPR2681

2

R267DNP

1/16W1%

1

2

5%1/16W

100R290

12 PCIE_CLK_QO_P

PCIE_CLK_QO_N12

7

6

5

4

3

2

1

9

8

11

12

13

14

16

17

18

19

20

15

10

U48

ICS874001

PCIE_250M_MGT1_C_N

PCIE_250M_MGT1_C_P

2

1

1%1/16W

DNPR266

VDD_SFPCLK

VDDA_SFPCLKVDD_SFPCLK

GND_SFPCLKGND_SFPCLK

VDDA_SFPCLK

SFPCLK_QO_N 6

SFPCLK_QO_P 6

21

NPO

50V

33PF

C325

1 2

F195

FERRITE-220

1 2

FERRITE-220

F194

21

5%10R272

2

1

X7R16V

0.01UFC304

2

1 C3030.01UF16VX7R

2

1

X5R10V

10UFC319

1

2

R261DNP

1/16W1%

X4

25.000MHZ

1 8

72

3 6

54

U47

ICS844021I

210.1UF

C299

10V

X5R

21

X5R

10V

C298

0.1UF

GND_SFPCLK

21C324

33PF

50V

NPO

SFPCLK_QO_C_P

SFPCLK_QO_C_NSFPCLK_XTAL_OUT

SFPCLK_XTAL_IN

2

1

5%

1/16W

4.7K

R258

1

2

R265DNP

1/16W1%

1

2

R257

4.7K

1/16W

5%

1

2 X7R16V

0.01UFC306

1

2

R254

4.7K

1/16W

5%

1

2

R26910

1/16W5%

2

1

5%

1/16W

4.7K

R253

2

1 C3050.01UF

16VX7R

1

2

R263DNP

1/16W1%

NC

NC

NC

NC

NC

NC

1 2X5R

10V

0.1UF

C301

1 2X5R

10V

0.1UF

C300

PCIE_250M_N6

PCIE_250M_P6

Page 29: Xilinx XTP067 - SP605 Schematics

VCC5

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

VCC12_P

INH

FAULT

SRE

PWM

GND_1

GND_0

TEMP

IOUT

AGND

VOVIVBIAS

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC1V5_FPGA

0.005R1W0.1%

I2I1

E1 E2

VCC1V5_FPGA

AGND7

0603_SHORT

SP605 EVALUATION PLATFORM Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

<=1.5V : DNP>1.5V = 787 ohms

VCC1V5 @ 10A

PTD08A010W 10A Max. Power Channel

PTD08A010W 10A Max. Power ChannelSCHEM, ROHS COMPLIANT

9-18-2009_15:03

3529 BF

D

04

1 2Z8

2

1 C278

820PF25VX7R

1

2

R53DNP

1/16W1%

1 2

R239

1.00K

1/16W

1%

1

2

C239330UF

16VELEC

MGT_VCC3_SENSE_N

26MGT_VCC3A_CS

I2I1

E1 E2

R66

VCC1V5

MGT_TEMP126

26MGT_VCC3A_FLT26MGT_VCC3A_SRE

MGT_VCC3A_PWM 26

8910

11

32 5 6 7

4112

U21

PTD08A010W

2

1

TANT6.3V

47UFC245 1

2

C232330UF

10VTANT

NC

21,22,23,24,30PWR_INH

MGT_VCC3_EA_P26

26 MGT_VCC3_EA_N

2

1 C137

22UF25VX5R

1 2

R46

4.22K

1/16W

1%

1 8

72

3 6

54

U41

INA333

MGT_VCC3_SENSE_P

Page 30: Xilinx XTP067 - SP605 Schematics

VCC12_P

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

INH

FAULT

SRE

PWM

GND_1

GND_0

TEMP

IOUT

AGND

VOVIVBIAS

AGND8

0603_SHORT

SP605 EVALUATION PLATFORM Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

<=1.5V : DNP>1.5V = 787 ohms

VCC3V3 @ 10A

PTD08A010W 10A Max. Power Channel

PTD08A010W 10A Max. Power ChannelSCHEM, ROHS COMPLIANT

04

D9-18-2009_15:03

3530 BF

1 2Z9

8910

11

32 5 6 7

4112

U22

PTD08A010W

2

1 C279

820PF25VX7R

1 2

R241

2.2K

1/16W

5%

1

2

R2481.6K

1/16W5%

1

2

C240330UF

16VELEC

VCC3V3

VCC3V3

MGT_VCC4_EA_N26

26 MGT_VCC4_EA_P

26 MGT_TEMP2

MGT_VCC4A_SRE 2626MGT_VCC4A_PWM

2

1

TANT6.3V

47UFC246 1

2

C233330UF

10VTANT

NC

PWR_INH 21,22,23,24,29MGT_VCC4A_FLT 26

2

1 C138

22UF25VX5R

Page 31: Xilinx XTP067 - SP605 Schematics

VCC5VCC3V0

VCCINT_FPGA

VCCINT_FPGA VCC2V5

VCC2V5

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VTTDDR

VCC2V5VCC1V8

VCC2V5

VCC2V5

VTTVREF

VIN

PGOOD

GND

REFOUT

EN

REFIN

VLDOIN

VO

PGND

VOSNS

PWRPAD

CON_SMA_SCREW_ON

SOT223-6

SHDN_N

IN

GND1 OUT

SNS_ADJ

GND2

TL1963A-18DCQR

LT1763CS8

BYP

GND3

GND6

GND7

OUT

ADJ

SHDN

IN

3.0V @ 500mA

SP605 EVALUATION PLATFORM Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

VCCINT_FPGA, VCCAUX Power Probe Channels

VCC1V8 @ 500mA

DDR3 Power Good

DDR3 Termination RegulatorSCHEM, ROHS COMPLIANT

MGT Power Probe Channel

DDR3 Termination Regulator, power probes

4

3

6

7

1

2

5

8U49

ROOM

BF31 35

9-24-2009_15:00 D

04

2

1 C209

10UF10VY5V

2

1 C208

10UF10VY5V

1

2Y5V10V10UF

C207

2

1 C206

10UF10VY5V

1

2Y5V10V10UF

C205

1

2

3 4

5

6

U44

12 3

J29

DNP

2 3 4 5 6 7 8 9

10

11

12

13

14

15

1

J54

DNP

1

15

14

13

12

11

1098765432

DNP

J53

1

15

14

13

12

11

1098765432

DNP

J52

2 3 4 5 6 7 8 9

10

11

12

13

14

15

1

J51

DNP

10

9

8

6

7

1

2

3

4

5

11U11

TPS51200DRCT

MGT_AVCC

2

1 C71

0.1UF10VX5R

2

1 C166

1UF6.3VX5R

1

2X7R16V

0.01UFC158

2

1 C1590.01UF

16VX7R

21

1%1/16W

10.0K

R166

1 2

R165

10.0K

1/16W

1%

2

1 C222

1000PF50VX7R

2

1 C290

4.7UF10VX5R

1

2

R204100K

1/16W5%

VCC1V5 21

DS15

LED-GRN-SMT

1

32

Q9

NDS331N

2

1 C165

1UF6.3VX5R

VCC3V3

1

2

1%1/16W

27.4R3

1

2

C3173.3UF

25VTANT

1

2

C32122UF

16VTANT

1

2

R27738.3

1/16W1%

1

2

R27526.1

1/16W1%

NC

Page 32: Xilinx XTP067 - SP605 Schematics

B1

E

P

B1

B1

B1

A

B

C

D

1234

D

C

B

A

4 3 2 1

Drawing Number:

Date:

Sheet Size: D

Sheet of

Ver:

Rev:

Drawn By

E

F

G

H

E

F

G

H

5678

5678

LAST REVISION:

B1

B1

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

GND

SHLD4

VBUS

D_N

D_P

SHLD1

SHLD2

SHLD3

ID

USB_MINI_B

GND;2,19,21,39,48,50GND;65,75,94,99

AGND

AVCC

BKPT

CLKOUT

CTL0_FLAGA

CTL1_FLAGB

CTL2_FLAGC

CTL3

CTL4

CTL5

D+

D-

IFCLK

INT4

NC1

NC2

NC3

PA0_INT0

PA1_INT1

PA2_SLOE

PA3_WU2

PA4_FIFOADR0

PA5_FIFOADR1

PA6_PKTEND

PA7_FLAGD

PB0_FD0

PB1_FD1

PB2_FD2

PB3_FD3

PB4_FD4

PB5_FD5

PB6_FD6

PB7_FD7

PC0_GPIFADR0

PC1_GPIFADR1

PC2_GPIFADR2

PC3_GPIFADR3

PC4_GPIFADR4

PC5_GPIFADR5

PC6_GPIFADR6

PC7_GPIFADR7

PD0_FD8

PD1_FD9

PD2_FD10

PD3_FD11

PD4_FD12

PD5_FD13

PD6_FD14

PD7_FD15

PE0_T0OUT

PE1_TIOUT

PE2_T2OUT

PE3_RXD0OUT

PE4_RXD1OUT

PE5_INT6

PE6_T2EX

PE7_GPIFADR8

RDY0

RDY1

RDY2

RDY3

RDY4

RDY5

RESERVED

RXD0

RXD1

SCL

SDA

T0

T1

T2

TXD0

TXD1

WAKEUP

XTALIN

XTALOUT

INT5

RD

RESET

WR

PORT E

PORT A

PORT C

PORT D

PORT B

VCCINT

GPIF

GPIF

PORT E

PORT A

PORT E

GND;21,25,31,62GND;69,75,84,100

BIT_CLOCK

BUFFER_OE

BUS_ENABLE

COUNT0

COUNT1

COUNT2

COUNT3

COUNT4

CTRL1

CTRL2

DONE

DONE_INH

DONE_SM0

DONE_SM1

DONE_SM2

DOWN_CNT0

DOWN_CNT1

DOWN_CNT2

DOWN_CNT3

DOWN_CNT4

EXTEND

GPIF_D00

GPIF_D01

GPIF_D02

GPIF_D03

GPIF_D04

GPIF_D05

GPIF_D06

GPIF_D07

GPIF_D08

GPIF_D09

GPIF_D10

GPIF_D11

GPIF_D12

GPIF_D13

GPIF_D14

GPIF_D15

IDLE_FLAG

INIT_IN

INIT_OUT

JTP_CMD0

JTP_CMD1

JTP_CMD2

LAST_BIT

LAST_WORD

RDY1

RDY2

SHIFT_CLK

SPARE_COM

SPARE_P065

SPARE_P071

SPARE_P073

SPARE_P074

SPARE_P076

SPARE_P077

SPARE_P078

SPARE_P079

SPARE_P080

SPARE_P081

SPARE_P082

SPARE_P085

SPARE_P086

SPARE_P087

SPARE_P089

SPARE_P090

SPARE_P091

SPARE_P092

SPARE_P099

START

TAP_STATE0

TAP_STATE1

TAP_STATE2

TAP_STATE3

TCK

TCK_CCLK

TDI

TDI_DIN

TDO

TDO_B

TDO_SAMPLE_CLOCK

TMS

TMS_LEVEL

TMS_PROG

VERSION

BANK 2

BANK 1

BANK 1

BANK 1

BANK 1

BANK 1

BANK 2

VCCINTVAUXVCCIO1VCCIO2

TAP

BANK 2

BANK 2

Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

FPGA_TCK

LEGEND:

COMPONENTS TO BE LOADED FOR THE PRODUCTION

ASSEMBLY VERSION ONLY.

LOCAL 2MM CABEL CONNECTOR J1.

OPTIONAL NETS ROUTED IN PARALLEL TO

AND/OR DIAGNOSTICS.

OPTIONAL COMPONENTS THAT SUPPORT DEBUG

SCHWEIGLER

USB TYPE B

RECEPTACLE

USB

CONVERTER

6 PLACES

3 PLACES

USB CONTROLLER

CONNECTOR

PARALLEL TO SERIAL

NOTE: EMBEDDED VERSION

2 PLACES

N/CFROM JTAGTO

LAST DEVICE TDO

FIRST DEVICE TDI

TARGET INTERFACE CONNNECTIONS

3.3V INTERFACE TO LOCAL JTAG OR SLAVE-SERIAL DEVICE CHAIN.

AND EMBEDDED_TMS WITH LVDS BUFFERS.

14-JUNE-2006

IS NOT BUS POWERED

TCK ALL DEVICES

TMS ALL DEVICES

FOR LONG CHAINS OR TRACES, DISTRIBUTE EMBEDDED_TCK

OF THE NETS MARKED TO FACILITATE FASTER IN-CIRCUIT

RE-PROGRAMMING OF THE CPLD DURING BOARD TEST.

ASSEMBLY FOOTPRINT IS RECOMMENDED FOR THE PWB LAYOUT.

NOTE:

J1 DOES NOT NEED TO BE POPULATED DURING PRODUCTION, BUT THE

0381242

MAKE PARALLEL CONNECTIONS TO J1 (OPTION B) AT EACH

3 PLACES

FPGA_TMS

USB_HEADER_TDI

JTAG_TDO

EMBEDDED_INIT NO CONNECTION

FPGA_TCK

Embedded USB JTAG: USB Controller, CPLD

The Embedded USB JTAG Download circuit on this page is for reference only!This circuit should not be designed into an end customer product or solution.Xilinx will not provide support on this embedded USB JTAG Download circuit.

21Y1

24MHZ

2

1 C132

3.3UF10V

04

32 359-24-2009_15:56

C

22

61

2

14

15

16

17

18

54

55

63

8

3

6

7

97

96

95

94

93

24

77

76

74

73

72

71

85

86

87

89

65

99

11

1

92

91

90

13

10

12

82

78

79

80

81

32

33

34

35

36

37

39

40

41

42

43

44

46

49

50

52

28

70

19

29

30

4

58

64

59

9

53

48

66

45

68

47

60

67

56

83

27

23

U24

XC2C256

VCC3V3;20,38,51VCC3V3;88,98

VCC3V3;5VCC1V8;26,57

VQFP100

12

9

28

54

55

56

51

52

76

17

18

22

13

14

15

67

68

69

70

71

72

73

74

34

35

36

37

44

45

46

47

57

58

59

60

61

62

63

64

80

81

82

83

95

96

97

98

86

87

88

89

90

91

92

93

3

4

5

6

7

8

27

41

43

29

30

23

24

25

40

42

79

11

10

84

31

77

32

100

26

U28

PART_NUMBER=CY7C68013A

VCC3V3;1,16,20,33,38VCC3V3;49,53,66,78,85

TQFP100

NC

NC

5

9

1

2

3

678

4

J4

7JTAG_TMS

7JTAG_TCK

JTAG_TDO 20

JTAG_TDI 7

1

2

R18910K

1/16W5%

USBHDR_TDI_R

USBHDR_TMS_R

USBHDR_TCK_R

NC

NC

NC

SPARE_COM

CPLD_TDO 33

CPLD_TDI 33

CPLD_TMS 33

CPLD_TCK 33

2

1 R17810K

1/16W5%

2

1 C72

0.1UF10VX5R

1

2NPO50V11PF

C264

2

1 C263

11PF50VNPO

21R58

15

1/16W

5%

1 2

5%1/16W

15R57

21R56

15

1/16W

5%

EMBEDDED_INIT

1

2

R19720K

1/16W5%

2

1 R17710K

1/16W5%

POR33

USB_SDA33

USB_SCL33

LED_GRN 33

LED_RED 33

SERIAL_NUMBER 33

NC

NC

NC

NC

NC

NC

NC

1

2

R19520K

1/16W5%

2

1 R18810K

1/16W5%

12

5%1/16W

10K

R183

2 1R186

10K

1/16W

5%

12

5%1/16W

10K

R185

2 1R182

10K

1/16W

5%

2

1 R18110K

1/16W5%

2

1 R18010K

1/16W5%

2 1R176

10K

1/16W

5%

12

R175

2 1R174

GPIF_DONE

GPIF_START

JTP_CMD3

VREF_DETECT

VERSION_REQUEST

TDO_SAMPLE_CLK

LAST_WORD

TMS_LEVEL

GPIF_D15

GPIF_D00

GPIF_D01

GPIF_D02

GPIF_D03

GPIF_D04

GPIF_D05

GPIF_D06

GPIF_D07

GPIF_D08

GPIF_D09

GPIF_D10

GPIF_D11

GPIF_D12

GPIF_D13

GPIF_D14

CTRL2

CTRL3

COUNT0

COUNT1

COUNT2

COUNT3

COUNT4

JTP_CMD0

JTP_CMD1

JTP_CMD2

RDY1

RDY2

BIT_CLOCK

1

2

5%1/16W

10KR179

2 1R184

10K

1/16W

5%

12

5%1/16W

10K

R187

2

1

5%1/16W

20KR196

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

2

1

5%1/16W

10KR190

NC

2

1 1%4.

75KR12

0

BUFFER_OE

NC

Page 33: Xilinx XTP067 - SP605 Schematics

VCC3V3

E

E E

E

VCC3V3

VCC3V3

VCC3V3

VCC3V3 VCC1V8

VCC3V3

VCC3V3

E

GND

SCL

SDA

VCC

NC

NC

NC

NC

DS2411

I/O

GND

VCC

NC

NC

NC

MAX6412UK22

GND

VCC

MR

RESET

SRT

SUPERVISORYPOWER

P

GR

TSM_107_01_L_DV

GND

GND

GND

GND

GND

TDI

GND

TMS

VTST

VREF

TCK

INIT

GTST

TDO

A

B

C

D

1234

D

C

B

A

4 3 2 1

Drawing Number:

Date:

Sheet Size: D

Sheet of

Ver:

Rev:

Drawn By

E

F

G

H

E

F

G

H

5678

5678

LAST REVISION:

The Embedded USB JTAG Download circuit on this page is for reference only!This circuit should not be designed into an end customer product or solution.Xilinx will not provide support on this embedded USB JTAG Download circuit.

Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305

VENDOR ID

PRODUCT ID

DATA FIELD

I2C EEPROM

LED

SCHWEIGLER

STATUS

DEFAULT

CYPRESS

0x004B4

0x8613

0x03FD

XILINX

EMBEDDED

14-JUNE-2006

DEFAULT PID/VID EEPROM

POWER-ON RESET

BYPASS CAPACITORS

NOTE: PRODUCES 5MS POWER-ON RESET

STATUS LEDS (OPTION A)

PC4 JTAG CONNECTOR (OPTION B)

ELECTRONIC SERIAL NUMBER

0x000D

PROM PRIOR TO ASSEMBLY.

LOW POWER BOOT CONDITIONS

0381242

USE FILE 1080058 (HEX) TO PROGRAM THE I2C

Embedded USB JTAG: IIC, POR, Decoupling, LED, JTAG Header, Serial Number

PCB P/N: 0431534

C04

9-24-2009_15:00 33 35

1

10

11

12

13

14

2

3

4

5

6

7

8

9

J26

DNP

21

5%

1/16W0

R217 1 2

3

DS10

SSL-LX15IGCSOT23_LUMEX

USB_SDA 32

2

5

3

1

4

U35

5

3

42

1

6

U13

2

1

1%1/16W

100KR205

1

2 X7R16V

0.01UFC160

2

1 C262

1800PF50VX7R

7

4

3 6

5

81

2

U3324LC00T-SN

2

1 R1442.0K

1/16W5%

USB_SCL 32

1

2

R19820K

1/16W5%

LED_RED32

LED_GRN32

SERIAL_NUMBER32

32POR

1

2

C1703.3UF

25VTANT

1

2

R245270

1/16W5%

1

2

R244360

1/16W5%

2

1 C90

0.1UF10VX5R

2

1 C83

0.1UF10VX5R

1

2X5R10V0.1UF

C73 1

2X5R10V0.1UF

C80

2

1 C77

0.1UF10VX5R

1

2X5R10V0.1UF

C76

2

1 C74

0.1UF10VX5R

NC

2

1 R1452.0K

1/16W5%

2

1 R1432.0K

1/16W5%

NC

NC

NC

NC

NC

NC

1

2X5R10V0.1UF

C75 1

2X5R10V0.1UF

C78

2

1 C79

0.1UF10VX5R

2

1 C81

0.1UF10VX5R

1

2X5R10V0.1UF

C82

1

2X5R10V0.1UF

C84

2

1 C86

0.1UF10VX5R

1

2X5R10V0.1UF

C85 1

2X5R10V0.1UF

C88

2

1 C87

0.1UF10VX5R

1

2X5R10V0.1UF

C89

CPLD_TDO 32

CPLD_TCK 32

CPLD_TMS 32

NC

NC

32CPLD_TDI

Page 34: Xilinx XTP067 - SP605 Schematics

SFP_BOT_CAGE

SFP_TOP_CAGE

RUBBER_BUMPERNUT_SS_4-40MACHINE_SCREW_SS_PHILHD_4-40_X_3-8

JUMPER_BLOCK_2-PIN JUMPER_BLOCK_2-PINJUMPER_BLOCK_2-PIN

NUT_SS_4-40

RUBBER_BUMPER

RUBBER_BUMPER

NUT_SS_4-40MACHINE_SCREW_SS_PHILHD_4-40_X_3-8

MACHINE_SCREW_SS_PHILHD_4-40_X_3-8

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

NUT_SS_4-40 RUBBER_BUMPER

JUMPER_BLOCK_2-PIN

MACHINE_SCREW_SS_PHILHD_4-40_X_3-8NUT_SS_4-40 RUBBER_BUMPER

MACHINE_SCREW_SS_PHILHD_4-40_X_3-8

110V Prong Power Brick

Power Cord

USB A

USB Mini-B Cable

USB Mini-B

12v Power Brick

OE

GND

VCC

OUT

OSC

0250446

PCIE

POWER

Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

SP605 EVALUATION PLATFORM

Half Size Oscillator

Mechanical ComponentsSCHEM, ROHS COMPLIANT

Mechanical Components

9-25-2009_10:34

3534 BF

D

04

MSTK1

PL1

3650017

1

4

8

5

MX1

MBH2100H-27.000MHZ

PB1

CBL2

CBL1

MS1

MRB1MSO1MN2MS2

MJB4

MJS1

MSO5 MRB5MN5

1

MH_125_250

MH9

1

MH_125_250

MH8

1

MH7

MH_125_250

1

MH_125_250

MH6

1

MH5

MH_125_250

MS5

MS4MN3

MSO3

MRB3

MRB2

MN1MSO2

MJS2

MJB3 MJB2MJB1

MS3 MN4

MSO4 MRB4

PB2

CG1

Page 35: Xilinx XTP067 - SP605 Schematics

TXB0108

VCCBB1B2B3B4

B6B7

GND

A3

A8OE

A4A5

A7A6

B5

A1A2

B8

VCCA

VCC1V5_FPGA

VCC2V5

TXB0108

VCCBB1B2B3B4

B6B7

GND

A3

A8OE

A4A5

A7A6

B5

A1A2

B8

VCCA

VCC1V5_FPGA

VCC1V5_FPGA

TXB0108

VCCBB1B2B3B4

B6B7

GND

A3

A8OE

A4A5

A7A6

B5

A1A2

B8

VCCA

VCC2V5

VCC1V5_FPGA VCC2V5

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC3V3

TXB0108

VCCBB1B2B3B4

B6B7

GND

A3

A8OE

A4A5

A7A6

B5

A1A2

B8

VCCA

Test P/N: TSS0123ART P/N: 1280473

SCH P/N: 0381305PCB P/N: 0431534

SP605 EVALUATION PLATFORM

Level Shifters

Level ShiftersSCHEM, ROHS COMPLIANT

1920181716

1413

11

4

910

56

87

15

13

12

2

U14

04

D

BF35 35

9-24-2009_15:00

PCIE_PERST_B_LS5 12PCIE_PERST_B

NC NC

14GPIO_HEADER_014GPIO_HEADER_1

GPIO_HEADER_2 1414GPIO_HEADER_3

5 GPIO_HEADER_0_LS5 GPIO_HEADER_1_LS

NC

NCNCNC

NCNC

SYSACE_MPA04_LS5 SYSACE_MPA04 20

SYSACE_MPCE_LS5SYSACE_MPA06_LS5SYSACE_MPA05_LS5

SYSACE_MPA03_LS5SYSACE_MPA02_LS5

20SYSACE_D0

1

2X5R10V0.1UF

C91

21

C96

0.1UF

10V

X5R

20SYSACE_MPOE20SYSACE_MPWE20SYSACE_MPA0020SYSACE_MPA0120SYSACE_MPA0220SYSACE_MPA03

20SYSACE_D120SYSACE_D220SYSACE_D320SYSACE_D420SYSACE_D520SYSACE_D620SYSACE_D7

SYSACE_MPA05 20SYSACE_MPA06 20

SYSACE_MPIRQ 20SYSACE_MPCE 20

SYSACE_MPBRDY 20

1

2X5R10V0.1UF

C93

21

C92

0.1UF

10V

X5R

1920181716

1413

11

4

910

56

87

15

13

12

2

U15

2

12

31

1578

65

109

4

11

1314

1617182019

U16

1 2X5R

10V

0.1UFC

95

2

1 C94

0.1UF10VX5R

SYSACE_MPIRQ_LS5SYSACE_MPBRDY_LS5

SYSACE_D7_LS5SYSACE_D6_LS5SYSACE_D5_LS5SYSACE_D4_LS5SYSACE_D3_LS5SYSACE_D2_LS5SYSACE_D1_LS5SYSACE_D0_LS5

SYSACE_MPA01_LS5SYSACE_MPA00_LS5SYSACE_MPWE_LS5SYSACE_MPOE_LS5

NC NC

2

12

31

1578

65

109

4

11

1314

1617182019

U52

1 2X5R

10V

0.1UFC

385

2

1 C384

0.1UF10VX5R

NCNC

GPIO_HEADER_2_LS55 GPIO_HEADER_3_LS

NCNC