48
of Sheet Date: Title: Ver: A B C D 1 2 3 4 D C B A 4 3 2 1 Sheet Size: B Rev: Drawn By Disclaimer: 0b0011011 J1 TDI FMC LPC TDO FMC HPC TDO TDI U1 FPGA TDI TSTTDI CFGTDO CFGTDI TSTTDO U1 Jack JTAG Chain Differential Clock Clock Socket SMA Clock ML605 EVALUATION PLATFORM Power Supply Parallel Flash USB JTAG Connector IIC EEPROM LXT Virtex-6 ML605 Block Diagram SCH P/N: 0381311 ASSY P/N: 0431540 PCB P/N: 1280479 TDO DDR3 SODIMM MII/GMII/RGMII/SGMII FMC HPC/LPC Expansion Connectors Connector PCIe x8 Edge MGT SMA System Monitor LEDs, Buttons MODE DIP Switch USB UART USB Host/Peripheral DIP Switches DVI Video System ACE CF System ACE MPU x8 12V U6 0bXXXXX00 System ACE CF 3.3V 2.5V Linear Regulator [email protected] max VCCINT@20A max FMC_VADJ@20A max 2.5V@20A max MGT_VCC@6A max MGT_VTT@6A max 1.5V@20A max 3.3V@20A max Switching Regulator Switching Regulator Sink/Source DDR Regulator VTT/[email protected] max Power Controller 1 Power Controller 2 PWR Switching Module Switching Module Switching Module Switching Module Switching Module J64 J63 Page 15 Page 16-20 Page 24 Page 30 Page 34 Page 31 Page 28-29 Page 32 Page 25 Page 27, 33 Page 46 Page 30 Page 21 Page 13 Platform Flash Page 25, 26 USB HDR J22 J64 J63 J17 J18 U19 Linear Regulator 1.8V@500mA max 0b1010100 0b0101011 10/100/1000 Ethernet 0bXXXXX01 IIC Addressing THE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS")ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. SCHEM, ROHS COMPLIANT D 9-17-2009_15:45 48 1 04 BF

Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

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Page 1: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

Disclaimer:

0b0011011

J1

TDI

FMC LPC

TDO

FMC HPC

TDOTDI

U1

FPGA

TDITSTTDI CFGTDO

CFGTDITSTTDO

U1

Jack

JTAG Chain

Differential Clock

Clock Socket

SMA Clock

ML605 EVALUATION PLATFORM

Power Supply

Parallel Flash

USB JTAG ConnectorIIC EEPROM

LXT

Virtex-6

ML605 Block Diagram

SCH P/N: 0381311

ASSY P/N: 0431540

PCB P/N: 1280479

TDO

DDR3 SODIMM

MII/GMII/RGMII/SGMII

FMC HPC/LPC Expansion

Connectors

Connector

PCIe x8 Edge

MGT SMA

System Monitor

LEDs, Buttons

MODE DIP Switch

USB UART

USB Host/Peripheral

DIP Switches

DVI Video

System ACE CF

System ACE MPU x8

12V

U6

0bXXXXX00

System ACE CF

3.3V 2.5V

Linear Regulator

[email protected] max

VCCINT@20A max

FMC_VADJ@20A max

2.5V@20A max

MGT_VCC@6A max

MGT_VTT@6A max

1.5V@20A max

3.3V@20A max

Switching Regulator

Switching Regulator

Sink/Source DDR Regulator

VTT/[email protected] max

Power Controller 1

Power Controller 2

PWR

Switching Module

Switching Module

Switching Module

Switching Module

Switching Module

J64

J63

Page 15

Page 16-20 Page 24

Page 30

Page 34

Page 31

Page 28-29

Page 32

Page 25 Page 27, 33 Page 46

Page 30

Page 21

Page 13

Platform Flash

Page 25, 26

USB HDR

J22

J64 J63

J17 J18

U19

Linear Regulator

1.8V@500mA max

0b1010100

0b0101011

10/100/1000 Ethernet

0bXXXXX01

IIC Addressing

THE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS")ARE SUBJECT TO THE TERMS

AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT

http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE

OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED

ON THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION

REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS,

OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY OR PROPERTY

OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS

IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. ALL

SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

SCHEM, ROHS COMPLIANT

D9-17-2009_15:45

481

04

BF

Page 2: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC2V5_FPGA

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC2V5

INIT_B_0_P8

DONE_0_R8

M1_0_W8

M2_0_V8

HSWAPEN_0_M8

PROGRAM_B_0_L8

M0_0_U8

AVSS_0_T17

AVDD_0_T18

VP_0_U18

VREFP_0_V18

VN_0_V17

VREFN_0_U17

DXP_0_W18

DXN_0_W17

VBATT_0_N8

DIN_0_H8

RDWR_B_0_G8

CSI_B_0_F8

DOUT_BUSY_0_AA8

CCLK_0_K8

TDO_0_AC8

TCK_0_AE8

TMS_0_AF8

TDI_0_AD8

VFS_0_Y8

VCCO_0_AB9

VCCO_0_Y9

6vlx240tff1156

BANK 0

DUT

VCC2V5_FPGA

IO_L0P_14_U25

IO_L0N_14_T25

IO_L1P_14_T28

IO_L1N_14_T29

IO_L2P_14_R33

IO_L2N_14_R34

IO_L3P_14_T30

IO_L3N_14_T31

IO_L4P_14_T33

IO_L4N_VREF_14_T34

IO_L5P_14_U26

IO_L5N_14_U27

IO_L6P_14_U33

IO_L6N_14_U32

IO_L7P_14_U28

IO_L7N_14_V29

IO_L8P_SRCC_14_U31

IO_L8N_SRCC_14_U30

IO_L9P_MRCC_14_V30

IO_L9N_MRCC_14_W30

IO_L10P_MRCC_14_V34

IO_L10N_MRCC_14_W34

IO_L11P_SRCC_14_V28

IO_L11N_SRCC_14_V27

IO_L12P_VRN_14_V32

IO_L12N_VRP_14_V33

IO_L13P_14_Y32

IO_L13N_14_Y31

IO_L14P_14_Y33

IO_L14N_VREF_14_Y34

IO_L15P_14_W29

IO_L15N_14_Y29

IO_L16P_14_W31

IO_L16N_14_W32

IO_L17P_14_Y28

IO_L17N_14_Y27

IO_L18P_14_W25

IO_L18N_14_V25

IO_L19P_14_W27

IO_L19N_14_W26

VCCO_14_T27

VCCO_14_U34

VCCO_14_V31

VCCO_14_W28

6vlx240tff1156

BANK 14

DUT

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

ML605

FPGA Banks 0, 14

FPGA Banks 0, 14

BF

04

9-17-2009_15:43

482

D

FMC_HPC_HA20_P 17

FMC_HPC_HA20_N 17

FMC_HPC_HA19_P 17

FMC_HPC_HA19_N 17

FMC_HPC_HA18_P 18

FMC_HPC_HA18_N 18

18FMC_HPC_HA21_P

18FMC_HPC_HA21_N

18FMC_HPC_HA22_P

18FMC_HPC_HA22_N

18FMC_HPC_HA23_P

18FMC_HPC_HA23_N

32USB_A0_LS

U25

T25

T28

T29

R33

R34

T30

T31

T33

T34

U26

U27

U33

U32

U28

V29

U31

U30

V30

W30

V34

W34

V28

V27

V32

V33

Y32

Y31

Y33

Y34

W29

Y29

W31

W32

Y28

Y27

W25

V25

W27

W26

T27

U34

V31

W28

U1

P8

R8

W8

V8

M8

L8

U8

T17

T18

U18

V18

V17

U17

W18

W17

N8

H8

G8

F8

AA8

K8

AC8

AE8

AF8

AD8

Y8

AB9

Y9

U1

TEST_MON_VN0_N34

SYSACE_CFGTDI 13

FPGA_TCK 13

FPGA_TDI 13

13FPGA_TMS

32USB_D4_LS

LCD_RS_LS 32

USER_SMA_GPIO_P 30

USER_SMA_GPIO_N 30

1

2

R334

470

1/16W

5%

2

1

5%

1/16W

4.7K

R23

1

2

R201

1K

1/16W

5%

1

2

R22

4.7K

1/16W

5%

NC

13,25FPGA_PROG_B

31FPGA_DONE

GND_TESTMON2,34

TEST_MON_AVDD34

GND_TESTMON2,34

FPGA_DX_N34

FPGA_CCLK 25

FPGA_VBATT34

34FPGA_DX_P

TEST_MON_VREFP34

TEST_MON_VP0_P34

FPGA_M025

FPGA_M2 25

25FPGA_M1

FPGA_INIT_B 13,25,31

NC

NC

32USB_D6_LS

32USB_D15_LS

32USB_D14_LS

32USB_D12_LS

32USB_D9_LS

32USB_A1_LS

32USB_D5_LS

32USB_RD_B_LS

32USB_WR_B_LS

32USB_CS_B_LS

32USB_INT_LS

32USB_D13_LS

32USB_D11_LS

32USB_D10_LS

32USB_D8_LS

32USB_D3_LS

32USB_D2_LS

32USB_D1_LS

32USB_D0_LS

FMC_HPC_HA17_CC_P 18

FMC_HPC_HA17_CC_N 18

32USB_D7_LS

32USB_RESET_B_LS

Page 3: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC2V5_FPGA VCC2V5_FPGA

VCC2V5

VCC2V5

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

IO_L0P_15_M31

IO_L0N_15_L31

IO_L1P_15_N25

IO_L1N_15_M25

IO_L2P_SM8P_15_K32

IO_L2N_SM8N_15_K31

IO_L3P_SM9P_15_M26

IO_L3N_SM9N_15_M27

IO_L4P_15_P31

IO_L4N_VREF_15_P30

IO_L5P_SM10P_15_N27

IO_L5N_SM10N_15_P27

IO_L6P_SM11P_15_L33

IO_L6N_SM11N_15_M32

IO_L7P_SM12P_15_L28

IO_L7N_SM12N_15_M28

IO_L8P_SRCC_15_N32

IO_L8N_SRCC_15_P32

IO_L9P_MRCC_15_N28

IO_L9N_MRCC_15_N29

IO_L10P_MRCC_15_N33

IO_L10N_MRCC_15_M33

IO_L11P_SRCC_15_L29

IO_L11N_SRCC_15_L30

IO_L12P_SM13P_15_P25

IO_L12N_SM13N_15_P26

IO_L13P_SM14P_15_R28

IO_L13N_SM14N_15_R27

IO_L14P_15_R31

IO_L14N_VREF_15_R32

IO_L15P_SM15P_15_R26

IO_L15N_SM15N_15_T26

IO_L16P_VRN_15_K34

IO_L16N_VRP_15_L34

IO_L17P_15_M30

IO_L17N_15_N30

IO_L18P_15_N34

IO_L18N_15_P34

IO_L19P_15_P29

IO_L19N_15_R29

VCCO_15_L32

VCCO_15_M29

VCCO_15_N26

VCCO_15_P33

VCCO_15_R30

6vlx240tff1156

BANK 15

DUT

IO_L0P_16_C32

IO_L0N_16_B32

IO_L1P_16_J26

IO_L1N_16_J27

IO_L2P_16_E32

IO_L2N_16_E33

IO_L3P_16_F30

IO_L3N_16_G30

IO_L4P_16_A33

IO_L4N_VREF_16_B33

IO_L5P_16_G31

IO_L5N_16_H30

IO_L6P_16_C33

IO_L6N_16_B34

IO_L7P_16_K28

IO_L7N_16_J29

IO_L8P_SRCC_16_D34

IO_L8N_SRCC_16_C34

IO_L9P_MRCC_16_K26

IO_L9N_MRCC_16_K27

IO_L10P_MRCC_16_F33

IO_L10N_MRCC_16_G33

IO_L11P_SRCC_16_F31

IO_L11N_SRCC_16_E31

IO_L12P_VRN_16_E34

IO_L12N_VRP_16_F34

IO_L13P_16_J30

IO_L13N_16_K29

IO_L14P_16_H34

IO_L14N_VREF_16_H33

IO_L15P_16_D31

IO_L15N_16_D32

IO_L16P_16_K33

IO_L16N_16_J34

IO_L17P_16_G32

IO_L17N_16_H32

IO_L18P_16_L25

IO_L18N_16_L26

IO_L19P_16_J31

IO_L19N_16_J32

VCCO_16_A32

VCCO_16_D33

VCCO_16_G34

VCCO_16_H31

VCCO_16_J28

VCCO_16_K25

6vlx240tff1156

BANK 16

DUT

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

ML605

FPGA Banks 15, 16

FPGA Banks 15, 16

Place above components near FPGA

BF

04

9-17-2009_15:43

483

D

20FMC_LPC_LA20_P

20FMC_LPC_LA20_N

20FMC_LPC_LA23_P

20FMC_LPC_LA23_N

20FMC_LPC_LA22_P

20FMC_LPC_LA22_N

20FMC_LPC_LA21_P

20FMC_LPC_LA21_N

20FMC_LPC_LA33_P

20FMC_LPC_LA33_N

20FMC_LPC_LA26_P

20FMC_LPC_LA26_N

20FMC_LPC_LA30_P

20FMC_LPC_LA30_N

20FMC_LPC_LA29_P

20FMC_LPC_LA29_N

20FMC_LPC_LA28_P

20FMC_LPC_LA28_N

20FMC_LPC_LA24_P

20FMC_LPC_LA24_N

20FMC_LPC_LA25_P

20FMC_LPC_LA25_N

20FMC_LPC_LA27_P

20FMC_LPC_LA27_N

20FMC_LPC_LA19_P

20FMC_LPC_LA19_N

20FMC_LPC_LA15_P

20FMC_LPC_LA15_N

20FMC_LPC_LA16_P

20FMC_LPC_LA16_N

20FMC_LPC_LA14_P

20FMC_LPC_LA14_N

20FMC_LPC_LA13_P

20FMC_LPC_LA13_N

20FMC_LPC_LA12_P

20FMC_LPC_LA12_N

20FMC_LPC_LA10_P

20FMC_LPC_LA10_N

20FMC_LPC_LA07_P

20FMC_LPC_LA07_N

20FMC_LPC_LA05_P

20FMC_LPC_LA05_N

FMC_LPC_LA06_P 20

20FMC_LPC_LA06_N

20FMC_LPC_LA03_P

20FMC_LPC_LA03_N

20FMC_LPC_LA02_P

20FMC_LPC_LA02_N

20FMC_LPC_LA04_P

20FMC_LPC_LA04_N

C32

B32

J26

J27

E32

E33

F30

G30

A33

B33

G31

H30

C33

B34

K28

J29

D34

C34

K26

K27

F33

G33

F31

E31

E34

F34

J30

K29

H34

H33

D31

D32

K33

J34

G32

H32

L25

L26

J31

J32

A32

D33

G34

H31

J28

K25

U1

M31

L31

N25

M25

K32

K31

M26

M27

P31

P30

N27

P27

L33

M32

L28

M28

N32

P32

N28

N29

N33

M33

L29

L30

P25

P26

R28

R27

R31

R32

R26

T26

K34

L34

M30

N30

N34

P34

P29

R29

L32

M29

N26

P33

R30

U1

FMC_HPC_PG_M2C_LS 32

26FLASH_WAIT

3,39VAUX_COMMON_R

21

1%

1/16W

1.00K

R373

3,39VAUX_COMMON_R

VAUX_CURR_N

VAUX_VOLT_N

VAUX_VOLT_R 39

VAUX_CURR_R 39

VAUX_VOLT_P

1 2

R371

1.00K

1/16W

1%

21

1%

1/16W

1.00K

R372

VAUX_CURR_P

1

2

X7R

16V

0.01UF

C384

21

1%

1/16W

1.00K

R370

20FMC_LPC_LA18_CC_P

20FMC_LPC_LA18_CC_N

FMC_LPC_LA01_CC_P 20

20FMC_LPC_LA31_P

20FMC_LPC_LA31_N

VRN_15 3

VRN_16 3

VRP_163

3 VRN_16

20FMC_LPC_CLK1_M2C_N

20FMC_LPC_CLK1_M2C_P

20FMC_LPC_LA08_N

20FMC_LPC_LA08_P

20FMC_LPC_LA09_P

20FMC_LPC_LA09_N

20FMC_LPC_LA01_CC_N

20FMC_LPC_LA00_CC_P

20FMC_LPC_LA00_CC_N

2

1

1%

1/16W

49.9

R349

2

1R348

49.9

1/16W

1%

3 VRN_15

VRP_153

20FMC_LPC_LA17_CC_N

20FMC_LPC_LA17_CC_P

20FMC_LPC_LA32_N

20FMC_LPC_LA32_P

1

2

1%

1/16W

49.9

R351

1

2

R350

49.9

1/16W

1%

3VRP_16

3VRP_15

20FMC_LPC_LA11_N

20FMC_LPC_LA11_P

2

1 C385

0.01UF

16V

X7R

Page 4: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC2V5_FPGA

VCC2V5_FPGA

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

IO_L0P_GC_34_J9

IO_L0N_GC_34_H9

IO_L1P_GC_34_A10

IO_L1N_GC_34_B10

IO_L2P_A15_D31_34_F9

IO_L2N_A14_D30_34_F10

IO_L3P_A13_D29_34_C10

IO_L3N_A12_D28_34_D10

IO_L4P_A11_D27_34_C9

IO_L4N_VREF_A10_D26_34_D9

IO_L5P_A09_D25_34_A9

IO_L5N_A08_D24_34_A8

IO_L6P_A07_D23_34_E8

IO_L6N_A06_D22_34_E9

IO_L7P_A05_D21_34_B8

IO_L7N_A04_D20_34_C8

IO_L8P_SRCC_34_L9

IO_L8N_SRCC_34_K9

IO_L9P_MRCC_34_L10

IO_L9N_MRCC_34_M10

IO_L10P_MRCC_34_AC10

IO_L10N_MRCC_34_AB10

IO_L11P_SRCC_34_AH9

IO_L11N_SRCC_34_AJ9

IO_L12P_A03_D19_34_AD10

IO_L12N_A02_D18_34_AC9

IO_L13P_A01_D17_34_AK8

IO_L13N_A00_D16_34_AL8

IO_L14P_A25_34_AD9

IO_L14N_VREF_A24_34_AE9

IO_L15P_A23_34_AK9

IO_L15N_A22_34_AL9

IO_L16P_A21_34_AF9

IO_L16N_A20_34_AF10

IO_L17P_A19_34_AN9

IO_L17N_A18_34_AP9

IO_L18P_A17_34_AG8

IO_L18N_A16_34_AH8

IO_L19P_VRN_34_AN10

IO_L19N_VRP_34_AP10

VCCO_34_AE10

VCCO_34_AJ8

VCCO_34_AM9

VCCO_34_B9

VCCO_34_E10

VCCO_34_M9

6vlx240tff1156

BANK 34

DUT

IO_L0P_GC_24_L23

IO_L0N_GC_24_M22

IO_L1P_GC_24_K24

IO_L1N_GC_24_K23

IO_L2P_D15_24_M23

IO_L2N_D14_24_L24

IO_L3P_D13_24_F24

IO_L3N_D12_24_F23

IO_L4P_D11_24_N23

IO_L4N_VREF_D10_24_N24

IO_L5P_D9_24_H23

IO_L5N_D8_24_G23

IO_L6P_D7_24_R24

IO_L6N_D6_24_P24

IO_L7P_D5_24_H25

IO_L7N_D4_24_H24

IO_L8P_SRCC_24_T24

IO_L8N_SRCC_24_T23

IO_L9P_MRCC_24_J25

IO_L9N_MRCC_24_J24

IO_L10P_MRCC_24_U23

IO_L10N_MRCC_24_V23

IO_L11P_SRCC_24_AD24

IO_L11N_SRCC_24_AE24

IO_L12P_D3_24_V24

IO_L12N_D2_FS2_24_W24

IO_L13P_D1_FS1_24_AF25

IO_L13N_D0_FS0_24_AF24

IO_L14P_FCS_B_24_Y24

IO_L14N_VREF_FOE_B_MOSI_24_AA24

IO_L15P_FWE_B_24_AF23

IO_L15N_RS1_24_AG23

IO_L16P_RS0_24_AA23

IO_L16N_CSO_B_24_AB23

IO_L17P_VRN_24_AE23

IO_L17N_VRP_24_AE22

IO_L18P_24_AC23

IO_L18N_24_AC24

IO_L19P_24_AC22

IO_L19N_24_AD22

VCCO_24_AD23

VCCO_24_AG24

VCCO_24_G24

VCCO_24_L22

VCCO_24_U24

VCCO_24_Y25

6vlx240tff1156

BANK 24

DUT

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

ML605

FPGA Banks 24, 34

FPGA Banks 24, 34

BF

D

4 48

9-17-2009_15:43

04

DVI_GPIO1_FMC_C2M_PG_LS32

L23

M22

K24

K23

M23

L24

F24

F23

N23

N24

H23

G23

R24

P24

H25

H24

T24

T23

J25

J24

U23

V23

AD24

AE24

V24

W24

AF25

AF24

Y24

AA24

AF23

AG23

AA23

AB23

AE23

AE22

AC23

AC24

AC22

AD22

AD23

AG24

G24

L22

U24

Y25

U1

J9

H9

A10

B10

F9

F10

C10

D10

C9

D9

A9

A8

E8

E9

B8

C8

L9

K9

L10

M10

AC10

AB10

AH9

AJ9

AD10

AC9

AK8

AL8

AD9

AE9

AK9

AL9

AF9

AF10

AN9

AP9

AG8

AH8

AN10

AP10

AE10

AJ8

AM9

B9

E10

M9

U1

31GPIO_LED_3

31GPIO_LED_2

PLATFLASH_L_B 25

20FMC_LPC_CLK0_M2C_P

20FMC_LPC_CLK0_M2C_N

25,26FLASH_A15

FMC_LPC_PRSNT_M2C_L20

IIC_SDA_MAIN_LS 32

FMC_HPC_CLK0_M2C_P 18

FMC_HPC_CLK0_M2C_N 18

32PMBUS_CTRL_LS

SM_FAN_PWM 39

13SYSACE_MPIRQ

SM_FAN_TACH 39

32PMBUS_ALERT_LS

PMBUS_CLK_LS 32

32PMBUS_DATA_LS

30USER_SMA_CLOCK_N

30USER_SMA_CLOCK_P

SYSCLK_N 30

SYSCLK_P 30

IIC_SCL_DVI28,29

IIC_SDA_DVI28,29

IIC_SCL_MAIN_LS 32

25,26FPGA_FOE_B

25,26FPGA_FWE_B

31GPIO_LED_4

31GPIO_LED_5

32PCIE_WAKE_B_LS

FLASH_A14 25,26

25,26FLASH_A13

25,26FLASH_A10

FLASH_A9 25,26

FLASH_A7 25,26

FLASH_A6 25,26

FLASH_A5 25,26

25,26FLASH_A4

FLASH_A3 25,26

25,26FLASH_A2

FLASH_A1 25,26

25,26FLASH_A0

25,26FLASH_A22

FLASH_A21 25,26

25,26FLASH_A20

FLASH_A19 25,26

25,26FLASH_A18

FLASH_A17 25,26

25,26FLASH_A16

25,26FLASH_A8

25,26FLASH_A12

FLASH_A11 25,26

31GPIO_LED_0

31GPIO_LED_1

FLASH_A23 25,26

25FPGA_FCS_B

FLASH_D0 25,26

25,26FLASH_D1

25,26FLASH_D2

25,26FLASH_D3

31GPIO_LED_6

31GPIO_LED_7

33USB_1_TX

USB_1_RX 33

USB_1_RTS 33

USB_1_CTS 33

25,26FLASH_D4

FLASH_D5 25,26

25,26FLASH_D6

25,26FLASH_D7

25,26FLASH_D8

25,26FLASH_D9

25,26FLASH_D10

FLASH_D11 25,26

25,26FLASH_D12

FLASH_D13 25,26

25,26FLASH_D14

25,26FLASH_D15

USER_CLOCK 30

SFP_LOS 23

Page 5: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC1V5_FPGAVCC1V5_FPGA

VTTVREFVTTVREF

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

IO_L0P_35_G13

IO_L0N_35_H14

IO_L1P_35_D14

IO_L1N_35_C14

IO_L2P_SM0P_35_G11

IO_L2N_SM0N_35_F11

IO_L3P_SM1P_35_A13

IO_L3N_SM1N_35_A14

IO_L4P_35_G12

IO_L4N_VREF_35_H13

IO_L5P_SM2P_35_F14

IO_L5N_SM2N_35_E14

IO_L6P_SM3P_35_H10

IO_L6N_SM3N_35_G10

IO_L7P_SM4P_35_B12

IO_L7N_SM4N_35_B13

IO_L8P_SRCC_35_K14

IO_L8N_SRCC_35_J14

IO_L9P_MRCC_35_L13

IO_L9N_MRCC_35_M13

IO_L10P_MRCC_35_M12

IO_L10N_MRCC_35_M11

IO_L11P_SRCC_35_C13

IO_L11N_SRCC_35_C12

IO_L12P_SM5P_35_H12

IO_L12N_SM5N_35_J12

IO_L13P_SM6P_35_A11

IO_L13N_SM6N_35_B11

IO_L14P_35_J11

IO_L14N_VREF_35_J10

IO_L15P_SM7P_35_E13

IO_L15N_SM7N_35_F13

IO_L16P_VRN_35_K11

IO_L16N_VRP_35_L11

IO_L17P_35_D12

IO_L17N_35_E12

IO_L18P_GC_35_K13

IO_L18N_GC_35_K12

IO_L19P_GC_35_D11

IO_L19N_GC_35_E11

VCCO_35_A12

VCCO_35_D13

VCCO_35_G14

VCCO_35_H11

VCCO_35_L12

6vlx240tff1156

BANK 35

DUT

IO_L0P_25_D25

IO_L0N_25_D26

IO_L1P_25_C24

IO_L1N_25_C25

IO_L2P_25_E26

IO_L2N_25_F26

IO_L3P_25_B25

IO_L3N_25_A25

IO_L4P_25_D27

IO_L4N_VREF_25_E27

IO_L5P_25_B26

IO_L5N_25_A26

IO_L6P_25_G26

IO_L6N_25_G27

IO_L7P_25_B27

IO_L7N_25_C27

IO_L8P_SRCC_25_D24

IO_L8N_SRCC_25_E24

IO_L9P_MRCC_25_C28

IO_L9N_MRCC_25_B28

IO_L10P_MRCC_25_C29

IO_L10N_MRCC_25_D29

IO_L11P_SRCC_25_F25

IO_L11N_SRCC_25_G25

IO_L12P_25_H27

IO_L12N_25_G28

IO_L13P_25_A28

IO_L13N_25_A29

IO_L14P_25_F28

IO_L14N_VREF_25_E28

IO_L15P_25_A30

IO_L15N_25_B30

IO_L16P_VRN_25_E29

IO_L16N_VRP_25_F29

IO_L17P_25_C30

IO_L17N_25_D30

IO_L18P_GC_25_H28

IO_L18N_GC_25_H29

IO_L19P_GC_25_B31

IO_L19N_GC_25_A31

VCCO_25_B29

VCCO_25_C26

VCCO_25_E30

VCCO_25_F27

6vlx240tff1156

BANK 25

DUT

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

ML605

FPGA Banks 25, 35

FPGA Banks 25, 35

BF

04

9-17-2009_15:43

485

D

DDR3_D58 15

DDR3_D59 15

DDR3_DQS7_P 15

DDR3_D61 15

DDR3_D62 15

DDR3_D60 15

DDR3_D63 15

GPIO_SW_C 31

DDR3_D48 15

DDR3_D49 15

DDR3_D50 15

DDR3_D51 15

DDR3_D52 15

DDR3_D53 15

DDR3_D54 15

DDR3_D55 15

DDR3_D40 15

DDR3_D41 15

DDR3_D42 15

DDR3_D43 15

DDR3_D44 15

DDR3_D45 15

DDR3_D47 15DDR3_D16 15

DDR3_D17 15

DDR3_D20 15

DDR3_D21 15

DDR3_D22 15

DDR3_D23 15

DDR3_D12 15

DDR3_D9 15

DDR3_D11 15

DDR3_D46 15

DDR3_DQS5_P 15

DDR3_DQS5_N 15

DDR3_DM5 15

DDR3_D56 15

DDR3_DM7 15

DDR3_DQS7_N 15

DDR3_DQS6_P 15

DDR3_DQS6_N 15

DDR3_DM6 15

DDR3_D7 15

DDR3_DM0 15

DDR3_D6 15

DDR3_D5 15

DDR3_D0 15

DDR3_DQS0_N 15

DDR3_DQS0_P 15

DDR3_DM2 15

DDR3_D13 15

2

1 C386

0.01UF

16V

X7R 2

1 C387

0.01UF

16V

X7R

D25

D26

C24

C25

E26

F26

B25

A25

D27

E27

B26

A26

G26

G27

B27

C27

D24

E24

C28

B28

C29

D29

F25

G25

H27

G28

A28

A29

F28

E28

A30

B30

E29

F29

C30

D30

H28

H29

B31

A31

B29

C26

E30

F27

U1

G13

H14

D14

C14

G11

F11

A13

A14

G12

H13

F14

E14

H10

G10

B12

B13

K14

J14

L13

M13

M12

M11

C13

C12

H12

J12

A11

B11

J11

J10

E13

F13

K11

L11

D12

E12

K13

K12

D11

E11

A12

D13

G14

H11

L12

U1

NC

NC

NC

NC

31CPU_RESET

DDR3_D10 15

DDR3_D14 15

DDR3_DQS1_P 15

DDR3_DQS1_N 15

DDR3_D15 15

DDR3_DM1 15

NC

NC

NC

NC

DDR3_D4 15

DDR3_D3 15

DDR3_D2 15

DDR3_D1 15

DDR3_D19 15

DDR3_D18 15

DDR3_DQS2_P 15

DDR3_DQS2_N 15

DDR3_D8 15

DDR3_D57 15

Page 6: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC1V5_FPGA

VCC1V5_FPGA

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VTTVREF VTTVREF

IO_L0P_36_F18

IO_L0N_36_E17

IO_L1P_36_E18

IO_L1N_36_D17

IO_L2P_36_K18

IO_L2N_36_K17

IO_L3P_36_H17

IO_L3N_36_G17

IO_L4P_36_L19

IO_L4N_VREF_36_L18

IO_L5P_36_C17

IO_L5N_36_B17

IO_L6P_36_K19

IO_L6N_36_J19

IO_L7P_36_M18

IO_L7N_36_M17

IO_L8P_SRCC_36_G18

IO_L8N_SRCC_36_H18

IO_L9P_MRCC_36_K16

IO_L9N_MRCC_36_L16

IO_L10P_MRCC_36_L15

IO_L10N_MRCC_36_L14

IO_L11P_SRCC_36_A16

IO_L11N_SRCC_36_B16

IO_L12P_VRN_36_F16

IO_L12N_VRP_36_G16

IO_L13P_36_E16

IO_L13N_36_D16

IO_L14P_36_J17

IO_L14N_VREF_36_J16

IO_L15P_36_A15

IO_L15N_36_B15

IO_L16P_36_G15

IO_L16N_36_F15

IO_L17P_36_M16

IO_L17N_36_M15

IO_L18P_36_H15

IO_L18N_36_J15

IO_L19P_36_D15

IO_L19N_36_C15

VCCO_36_C16

VCCO_36_F17

VCCO_36_J18

VCCO_36_K15

6vlx240tff1156

BANK 36

DUT

IO_L0P_26_C20

IO_L0N_26_D20

IO_L1P_26_A23

IO_L1N_26_A24

IO_L2P_26_G21

IO_L2N_26_G22

IO_L3P_26_B23

IO_L3N_26_C23

IO_L4P_26_J20

IO_L4N_VREF_26_J21

IO_L5P_26_B21

IO_L5N_26_B22

IO_L6P_26_E22

IO_L6N_26_E23

IO_L7P_26_A20

IO_L7N_26_A21

IO_L8P_SRCC_26_F19

IO_L8N_SRCC_26_F20

IO_L9P_MRCC_26_B20

IO_L9N_MRCC_26_C19

IO_L10P_MRCC_26_F21

IO_L10N_MRCC_26_G20

IO_L11P_SRCC_26_H19

IO_L11N_SRCC_26_H20

IO_L12P_VRN_26_D21

IO_L12N_VRP_26_E21

IO_L13P_26_E19

IO_L13N_26_D19

IO_L14P_26_H22

IO_L14N_VREF_26_J22

IO_L15P_26_A18

IO_L15N_26_A19

IO_L16P_26_K21

IO_L16N_26_K22

IO_L17P_26_B18

IO_L17N_26_C18

IO_L18P_26_L20

IO_L18N_26_L21

IO_L19P_26_C22

IO_L19N_26_D22

VCCO_26_A22

VCCO_26_B19

VCCO_26_D23

VCCO_26_E20

VCCO_26_H21

6vlx240tff1156

BANK 26

DUT

FPGA Banks 26, 36

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

ML605

FPGA Banks 26, 36

BF

04

9-17-2009_15:43

486

D

DDR3_D36 15

DDR3_D37 15

DDR3_D39 15

DDR3_D32 15

DDR3_D33 15

DDR3_D27 15

DDR3_D28 15

DDR3_D29 15

DDR3_D30 15

DDR3_D31 15

DDR3_D26 15

DDR3_D25 15

DDR3_D24 15

DDR3_DM4 15

DDR3_D38 15

DDR3_DQS4_P 15

DDR3_DQS4_N 15

DDR3_D34 15

DDR3_D35 15

DDR3_DM3 15

DDR3_DQS3_N 15

DDR3_DQS3_P 15

C20

D20

A23

A24

G21

G22

B23

C23

J20

J21

B21

B22

E22

E23

A20

A21

F19

F20

B20

C19

F21

G20

H19

H20

D21

E21

E19

D19

H22

J22

A18

A19

K21

K22

B18

C18

L20

L21

C22

D22

A22

B19

D23

E20

H21

U1

F18

E17

E18

D17

K18

K17

H17

G17

L19

L18

C17

B17

K19

J19

M18

M17

G18

H18

K16

L16

L15

L14

A16

B16

F16

G16

E16

D16

J17

J16

A15

B15

G15

F15

M16

M15

H15

J15

D15

C15

C16

F17

J18

K15

U1

NC

GPIO_SW_W 31

GPIO_SW_E 31

DDR3_TEMP_EVENT 15

DDR3_ODT0 15

DDR3_ODT1 15

DDR3_RESET_B 15

DDR3_S0_B 15

DDR3_S1_B 15

DDR3_RAS_B 15

DDR3_WE_B 15

DDR3_CAS_B 15

DDR3_BA0 15

DDR3_BA1 15

DDR3_CKE0 15

DDR3_CKE1 15

DDR3_CLK0_P 15

DDR3_CLK0_N 15

DDR3_CLK1_P 15

DDR3_CLK1_N 15

DDR3_BA2 15

DDR3_A0 15

DDR3_A1 15

DDR3_A2 15

VRP_36 6

VRN_36 6

DDR3_A5 15

DDR3_A4 15

DDR3_A3 15

DDR3_A6 15

DDR3_A7 15

DDR3_A8 15

DDR3_A9 15

DDR3_A10 15

DDR3_A11 15

DDR3_A12 15

DDR3_A13 15

DDR3_A15 15

DDR3_A14 15

6VRN_26

NC

NC

GPIO_SW_S 31

VRN_366VRP_266

VCC1V5

1

2

R167

49.9

1/16W

1%

2

1

1%

1/16W

49.9

R166

VCC1V5

1

2

R164

49.9

1/16W

1%2

1

1%

1/16W

49.9

R165

VRN_266

VRP_366

GPIO_SW_N 31

31GPIO_DIP_SW8

31GPIO_DIP_SW7

GPIO_DIP_SW6 31

GPIO_DIP_SW5 31

GPIO_DIP_SW4 31

GPIO_DIP_SW3 31

GPIO_DIP_SW2 31

GPIO_DIP_SW1 31

6VRP_26

2

1 C388

0.01UF

16V

X7R

2

1 C389

0.01UF

16V

X7R

NC

Page 7: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC2V5_FPGA

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

IO_L0P_12_AD25

IO_L0N_12_AD26

IO_L1P_12_AE27

IO_L1N_12_AD27

IO_L2P_12_AH33

IO_L2N_12_AH32

IO_L3P_12_AE28

IO_L3N_12_AE29

IO_L4P_12_AJ34

IO_L4N_VREF_12_AH34

IO_L5P_12_AF28

IO_L5N_12_AF29

IO_L6P_12_AL34

IO_L6N_12_AK34

IO_L7P_12_AH29

IO_L7N_12_AH30

IO_L8P_SRCC_12_AN33

IO_L8N_SRCC_12_AN34

IO_L9P_MRCC_12_AG27

IO_L9N_MRCC_12_AG28

IO_L10P_MRCC_12_AF30

IO_L10N_MRCC_12_AG30

IO_L11P_SRCC_12_AF26

IO_L11N_SRCC_12_AE26

IO_L12P_VRN_12_AJ31

IO_L12N_VRP_12_AJ32

IO_L13P_12_AJ29

IO_L13N_12_AJ30

IO_L14P_12_AK33

IO_L14N_VREF_12_AK32

IO_L15P_12_AL31

IO_L15N_12_AK31

IO_L16P_12_AM33

IO_L16N_12_AL33

IO_L17P_12_AN32

IO_L17N_12_AM32

IO_L18P_12_AP32

IO_L18N_12_AP33

IO_L19P_12_AL30

IO_L19N_12_AM31

VCCO_12_AF27

VCCO_12_AG34

VCCO_12_AH31

VCCO_12_AL32

6vlx240tff1156

BANK 12

DUT

IO_L0P_13_AA34

IO_L0N_13_AA33

IO_L1P_13_AA30

IO_L1N_13_AA31

IO_L2P_13_AD34

IO_L2N_13_AC34

IO_L3P_13_AB30

IO_L3N_13_AB31

IO_L4P_13_AC33

IO_L4N_VREF_13_AB33

IO_L5P_13_AE31

IO_L5N_13_AD31

IO_L6P_13_AA25

IO_L6N_13_Y26

IO_L7P_13_AA28

IO_L7N_13_AA29

IO_L8P_SRCC_13_AE34

IO_L8N_SRCC_13_AF34

IO_L9P_MRCC_13_AD30

IO_L9N_MRCC_13_AC30

IO_L10P_MRCC_13_AE33

IO_L10N_MRCC_13_AF33

IO_L11P_SRCC_13_AD29

IO_L11N_SRCC_13_AC29

IO_L12P_VRN_13_AB32

IO_L12N_VRP_13_AC32

IO_L13P_13_AB28

IO_L13N_13_AC28

IO_L14P_13_AD32

IO_L14N_VREF_13_AE32

IO_L15P_13_AB27

IO_L15N_13_AC27

IO_L16P_13_AG33

IO_L16N_13_AG32

IO_L17P_13_AA26

IO_L17N_13_AB26

IO_L18P_13_AG31

IO_L18N_13_AF31

IO_L19P_13_AB25

IO_L19N_13_AC25

VCCO_13_AA32

VCCO_13_AB29

VCCO_13_AC26

VCCO_13_AD33

VCCO_13_AE30

6vlx240tff1156

BANK 13

DUT

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

LX240T ONLY

SCHEM, ROHS COMPLIANT

LX240T ONLY

ML605

FPGA Banks 12, 13

FPGA Banks 12, 13

BF

04

9-17-2009_15:43

487

D

14,18 FMC_VIO_B_M2C

FMC_HPC_HA03_P 18

FMC_HPC_HA03_N 18

FMC_HPC_HA07_P 18

FMC_HPC_HA07_N 18

FMC_HPC_HA05_P 17

FMC_HPC_HA05_N 17

FMC_HPC_HA04_N 17

FMC_HPC_HA04_P 17

FMC_HPC_HA06_P 18

FMC_HPC_HA06_N 18

17FMC_HPC_HA09_P

17FMC_HPC_HA09_N

FMC_HPC_HA08_P 17

FMC_HPC_HA08_N 17

FMC_HPC_HA11_P 18

FMC_HPC_HA11_N 18

FMC_HPC_HA13_P 17

FMC_HPC_HA13_N 17

FMC_HPC_HA12_P 17

FMC_HPC_HA12_N 17

18FMC_HPC_HA10_N

18FMC_HPC_HA10_P

FMC_HPC_HA16_P 17

FMC_HPC_HA16_N 17

FMC_HPC_HA15_P 17

FMC_HPC_HA15_N 17

FMC_HPC_HB08_P 17

FMC_HPC_HB08_N 17

FMC_HPC_HB03_P 17

FMC_HPC_HB03_N 17

FMC_HPC_HB11_P 18

FMC_HPC_HB11_N 18

FMC_HPC_HB10_P 18

FMC_HPC_HB10_N 18

FMC_HPC_HB14_P 18

FMC_HPC_HB14_N 18

FMC_HPC_HB18_P 18

FMC_HPC_HB18_N 18

FMC_HPC_HB01_P 18

FMC_HPC_HB01_N 18

FMC_HPC_HB05_P 17

17FMC_HPC_HB05_N

FMC_HPC_HB04_P 17

FMC_HPC_HB04_N 17

FMC_HPC_HB09_P 17

FMC_HPC_HB09_N 17

FMC_HPC_HB07_P 18

FMC_HPC_HB07_N 18

FMC_HPC_HB13_P 17

FMC_HPC_HB13_N 17

FMC_HPC_HB12_P 17

FMC_HPC_HB12_N 17

FMC_HPC_HB19_P 17

FMC_HPC_HB19_N 17

FMC_HPC_HB16_P 17

FMC_HPC_HB16_N 17

18FMC_HPC_HB00_CC_N

FMC_HPC_HB06_CC_P 18

18FMC_HPC_HB00_CC_P

AA34

AA33

AA30

AA31

AD34

AC34

AB30

AB31

AC33

AB33

AE31

AD31

AA25

Y26

AA28

AA29

AE34

AF34

AD30

AC30

AE33

AF33

AD29

AC29

AB32

AC32

AB28

AC28

AD32

AE32

AB27

AC27

AG33

AG32

AA26

AB26

AG31

AF31

AB25

AC25

AA32

AB29

AC26

AD33

AE30

U1

AD25

AD26

AE27

AD27

AH33

AH32

AE28

AE29

AJ34

AH34

AF28

AF29

AL34

AK34

AH29

AH30

AN33

AN34

AG27

AG28

AF30

AG30

AF26

AE26

AJ31

AJ32

AJ29

AJ30

AK33

AK32

AL31

AK31

AM33

AL33

AN32

AM32

AP32

AP33

AL30

AM31

AF27

AG34

AH31

AL32

U1

22FMC_HPC_CLK3_M2C_IO_N

FMC_HPC_CLK2_M2C_IO_P 22

FMC_HPC_HA00_CC_P 17

FMC_HPC_CLK2_M2C_IO_N 22

22FMC_HPC_CLK3_M2C_IO_P

IIC_SDA_SFP 23

FMC_HPC_HA01_CC_P 17

FMC_HPC_HA01_CC_N 17

FMC_HPC_HA02_P 18

FMC_HPC_HA02_N 18

FMC_HPC_HB17_CC_P 18

FMC_HPC_HB17_CC_N 18

FMC_HPC_HB15_P 18

FMC_HPC_HB15_N 18

FMC_HPC_HB02_P 17

FMC_HPC_HB02_N 17

FMC_HPC_HA00_CC_N 17

IIC_SCL_SFP 23

FMC_HPC_HB06_CC_N 18

FMC_HPC_HA14_N 18

FMC_HPC_HA14_P 18

Page 8: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC2V5_FPGA

VCC2V5_FPGA

VCC2V5

VCC2V5

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

IO_L0P_22_AE21

IO_L0N_22_AD21

IO_L1P_22_AM18

IO_L1N_22_AL18

IO_L2P_22_AG22

IO_L2N_22_AH22

IO_L3P_22_AP19

IO_L3N_22_AN18

IO_L4P_22_AK22

IO_L4N_VREF_22_AJ22

IO_L5P_22_AN19

IO_L5N_22_AN20

IO_L6P_22_AC20

IO_L6N_22_AD20

IO_L7P_22_AM20

IO_L7N_22_AL20

IO_L8P_SRCC_22_AF19

IO_L8N_SRCC_22_AE19

IO_L9P_MRCC_22_AP20

IO_L9N_MRCC_22_AP21

IO_L10P_MRCC_22_AK19

IO_L10N_MRCC_22_AL19

IO_L11P_SRCC_22_AF20

IO_L11N_SRCC_22_AF21

IO_L12P_VRN_22_AJ20

IO_L12N_VRP_22_AH20

IO_L13P_22_AM21

IO_L13N_22_AL21

IO_L14P_22_AC19

IO_L14N_VREF_22_AD19

IO_L15P_22_AM23

IO_L15N_22_AL23

IO_L16P_22_AK21

IO_L16N_22_AJ21

IO_L17P_22_AM22

IO_L17N_22_AN22

IO_L18P_22_AG20

IO_L18N_22_AG21

IO_L19P_22_AP22

IO_L19N_22_AN23

VCCO_22_AE20

VCCO_22_AH21

VCCO_22_AL22

VCCO_22_AM19

VCCO_22_AP23

6vlx240tff1156

BANK 22

DUT

IO_L0P_23_AH27

IO_L0N_23_AH28

IO_L1P_23_AN30

IO_L1N_23_AM30

IO_L2P_23_AG25

IO_L2N_23_AG26

IO_L3P_23_AP30

IO_L3N_23_AP31

IO_L4P_23_AL29

IO_L4N_VREF_23_AK29

IO_L5P_23_AN29

IO_L5N_23_AP29

IO_L6P_23_AL28

IO_L6N_23_AK28

IO_L7P_23_AN28

IO_L7N_23_AM28

IO_L8P_SRCC_23_AH25

IO_L8N_SRCC_23_AJ25

IO_L9P_MRCC_23_AN27

IO_L9N_MRCC_23_AM27

IO_L10P_MRCC_23_AK27

IO_L10N_MRCC_23_AJ27

IO_L11P_SRCC_23_AH23

IO_L11N_SRCC_23_AH24

IO_L12P_VRN_23_AK26

IO_L12N_VRP_23_AJ26

IO_L13P_23_AL26

IO_L13N_23_AM26

IO_L14P_23_AJ24

IO_L14N_VREF_23_AK24

IO_L15P_23_AP27

IO_L15N_23_AP26

IO_L16P_23_AM25

IO_L16N_23_AL25

IO_L17P_23_AN25

IO_L17N_23_AN24

IO_L18P_23_AK23

IO_L18N_23_AL24

IO_L19P_23_AP25

IO_L19N_23_AP24

VCCO_23_AJ28

VCCO_23_AK25

VCCO_23_AM29

VCCO_23_AN26

6vlx240tff1156

BANK 23

DUT

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

LX240T ONLY

LX240T ONLY

SCHEM, ROHS COMPLIANT

ML605

FPGA Banks 22, 23

FPGA Banks 22, 23

BF

04

9-17-2009_15:43

488

D

17FMC_HPC_LA31_P

17FMC_HPC_LA31_N

18FMC_HPC_LA28_N

17FMC_HPC_LA33_P

FMC_HPC_LA17_CC_N 16

18FMC_HPC_LA19_P

18FMC_HPC_LA19_N

FMC_HPC_LA23_P 16

FMC_HPC_LA23_N 16

FMC_HPC_LA22_P 17

FMC_HPC_LA22_N 17

FMC_HPC_LA21_P 18

FMC_HPC_LA21_N 18

16FMC_HPC_LA27_P

16FMC_HPC_LA27_N

17FMC_HPC_LA25_P

17FMC_HPC_LA25_N

18FMC_HPC_LA24_P

18FMC_HPC_LA24_N

16FMC_HPC_LA26_P

16FMC_HPC_LA26_N

17FMC_HPC_LA29_P

17FMC_HPC_LA29_N

18FMC_HPC_LA30_P

18FMC_HPC_LA30_N

17FMC_HPC_LA33_N

18FMC_HPC_LA32_P

18FMC_HPC_LA32_N

FMC_HPC_LA16_N 17

FMC_HPC_LA16_P 17

FMC_HPC_LA14_P 16

FMC_HPC_LA14_N 16

FMC_HPC_LA13_P 16

FMC_HPC_LA13_N 16

FMC_HPC_LA08_P 17

FMC_HPC_LA02_P 18

FMC_HPC_LA02_N 18

17FMC_HPC_LA03_N

FMC_HPC_LA03_P 17

FMC_HPC_LA04_P 18

FMC_HPC_LA04_N 18

FMC_HPC_LA06_P 16

FMC_HPC_LA06_N 16

FMC_HPC_LA05_P 16

FMC_HPC_LA05_N 16

FMC_HPC_LA08_N 17

FMC_HPC_LA07_P 18

FMC_HPC_LA07_N 18

FMC_HPC_LA12_P 17

FMC_HPC_LA12_N 17

FMC_HPC_LA11_P 18

FMC_HPC_LA11_N 18

FMC_HPC_LA15_P 18

FMC_HPC_LA15_N 18

2

1R356

49.9

1/16W

1%

2

1

1%

1/16W

49.9

R357

2

1

1%

1/16W

49.9

R355

2

1R354

49.9

1/16W

1%

AH27

AH28

AN30

AM30

AG25

AG26

AP30

AP31

AL29

AK29

AN29

AP29

AL28

AK28

AN28

AM28

AH25

AJ25

AN27

AM27

AK27

AJ27

AH23

AH24

AK26

AJ26

AL26

AM26

AJ24

AK24

AP27

AP26

AM25

AL25

AN25

AN24

AK23

AL24

AP25

AP24

AJ28

AK25

AM29

AN26

U1

AE21

AD21

AM18

AL18

AG22

AH22

AP19

AN18

AK22

AJ22

AN19

AN20

AC20

AD20

AM20

AL20

AF19

AE19

AP20

AP21

AK19

AL19

AF20

AF21

AJ20

AH20

AM21

AL21

AC19

AD19

AM23

AL23

AK21

AJ21

AM22

AN22

AG20

AG21

AP22

AN23

AE20

AH21

AL22

AM19

AP23

U1

VRN_23 8

8VRP_23VRN_22 8

VRP_22 8

GPIO_LED_W 31

FMC_HPC_LA17_CC_P 16

VRP_228

VRN_228

FMC_HPC_CLK1_M2C_P 17

FMC_HPC_LA01_CC_N 16

FMC_HPC_LA00_CC_P 17

FMC_HPC_LA01_CC_P 16

FMC_HPC_LA00_CC_N 17

FMC_HPC_CLK1_M2C_N 17

FMC_HPC_LA10_N 16

FMC_HPC_LA10_P 16

FMC_HPC_LA20_N 17

FMC_HPC_LA20_P 17

FMC_HPC_PRSNT_M2C_L 18

GPIO_LED_C 31

GPIO_LED_S 31

GPIO_LED_N 31

8 VRN_23

VRP_238

FMC_HPC_LA18_CC_P 16

FMC_HPC_LA18_CC_N 16

GPIO_LED_E 31

18FMC_HPC_LA28_P

FMC_HPC_LA09_N 16

FMC_HPC_LA09_P 16

Page 9: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC2V5_FPGAVCC2V5_FPGA

VCC2V5

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

IO_L0P_33_AE13

IO_L0N_33_AE12

IO_L1P_33_AJ11

IO_L1N_33_AK11

IO_L2P_33_AD14

IO_L2N_33_AC14

IO_L3P_33_AK12

IO_L3N_33_AJ12

IO_L4P_33_AF11

IO_L4N_VREF_33_AE11

IO_L5P_33_AM10

IO_L5N_33_AL10

IO_L6P_33_AG11

IO_L6N_33_AG10

IO_L7P_33_AL11

IO_L7N_33_AM11

IO_L8P_SRCC_33_AJ10

IO_L8N_SRCC_33_AH10

IO_L9P_MRCC_33_AC13

IO_L9N_MRCC_33_AC12

IO_L10P_MRCC_33_AD12

IO_L10N_MRCC_33_AD11

IO_L11P_SRCC_33_AP11

IO_L11N_SRCC_33_AP12

IO_L12P_VRN_33_AF13

IO_L12N_VRP_33_AG13

IO_L13P_33_AM12

IO_L13N_33_AN12

IO_L14P_33_AE14

IO_L14N_VREF_33_AF14

IO_L15P_33_AN13

IO_L15N_33_AM13

IO_L16P_33_AG12

IO_L16N_33_AH12

IO_L17P_33_AK13

IO_L17N_33_AL13

IO_L18P_33_AH13

IO_L18N_33_AH14

IO_L19P_33_AP14

IO_L19N_33_AN14

VCCO_33_AD13

VCCO_33_AG14

VCCO_33_AH11

VCCO_33_AL12

VCCO_33_AP13

6vlx240tff1156

BANK 33

DUT

IO_L0P_32_AG15

IO_L0N_32_AF15

IO_L1P_32_AK14

IO_L1N_32_AJ14

IO_L2P_32_AJ15

IO_L2N_32_AH15

IO_L3P_32_AL15

IO_L3N_32_AL14

IO_L4P_32_AG16

IO_L4N_VREF_32_AF16

IO_L5P_32_AN15

IO_L5N_32_AM15

IO_L6P_32_AJ17

IO_L6N_32_AJ16

IO_L7P_32_AP16

IO_L7N_32_AP15

IO_L8P_SRCC_32_AH17

IO_L8N_SRCC_32_AG17

IO_L9P_MRCC_32_AC15

IO_L9N_MRCC_32_AD15

IO_L10P_MRCC_32_AE16

IO_L10N_MRCC_32_AD16

IO_L11P_SRCC_32_AC18

IO_L11N_SRCC_32_AC17

IO_L12P_VRN_32_AH18

IO_L12N_VRP_32_AG18

IO_L13P_32_AN17

IO_L13N_32_AP17

IO_L14P_32_AJ19

IO_L14N_VREF_32_AH19

IO_L15P_32_AM17

IO_L15N_32_AM16

IO_L16P_32_AD17

IO_L16N_32_AE17

IO_L17P_32_AK18

IO_L17N_32_AK17

IO_L18P_32_AE18

IO_L18N_32_AF18

IO_L19P_32_AL16

IO_L19N_32_AK16

VCCO_32_AC16

VCCO_32_AF17

VCCO_32_AJ18

VCCO_32_AK15

VCCO_32_AN16

6vlx240tff1156

BANK 32

DUT

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

LX240T ONLY

SCHEM, ROHS COMPLIANT

ML605

FPGA Banks 32, 33

FPGA Banks 32, 33

LX240T ONLY

D

9 48

9-17-2009_15:42

04

BF

32FMC_LPC_IIC_SDA_LS

24PHY_RXD4

AG15

AF15

AK14

AJ14

AJ15

AH15

AL15

AL14

AG16

AF16

AN15

AM15

AJ17

AJ16

AP16

AP15

AH17

AG17

AC15

AD15

AE16

AD16

AC18

AC17

AH18

AG18

AN17

AP17

AJ19

AH19

AM17

AM16

AD17

AE17

AK18

AK17

AE18

AF18

AL16

AK16

AC16

AF17

AJ18

AK15

AN16

U1

2

1R169

49.9

1/16W

1%

2

1

1%

1/16W

49.9

R168

AE13

AE12

AJ11

AK11

AD14

AC14

AK12

AJ12

AF11

AE11

AM10

AL10

AG11

AG10

AL11

AM11

AJ10

AH10

AC13

AC12

AD12

AD11

AP11

AP12

AF13

AG13

AM12

AN12

AE14

AF14

AN13

AM13

AG12

AH12

AK13

AL13

AH13

AH14

AP14

AN14

AD13

AG14

AH11

AL12

AP13

U1

32FMC_LPC_IIC_SCL_LS

LCD_RW_LS32

LCD_E_LS32

PHY_TXCTL_TXEN 24

LCD_DB4_LS32

PHY_TXCLK 24

PHY_MDIO 24

PHY_INT 24

PHY_RXCTL_RXDV 24

24PHY_RXER

PHY_COL 24

PHY_CRS 24

PHY_RESET 24

PHY_MDC 24

PHY_RXD3 24

PHY_RXD2 24

PHY_RXD1 24

PHY_RXD0 24

LCD_DB6_LS32

P30_CS_SEL 25

PHY_TXER 24

PHY_TXD0 24

PHY_TXD1 24

PHY_TXD2 24

PHY_TXD5 24

24PHY_TXD6

24PHY_TXD7

PHY_TXD3 24

PHY_TXD4 24

LCD_DB5_LS32

LCD_DB7_LS3232PCIE_PERST_B_LS

PHY_RXCLK 24

24PHY_RXD6

24PHY_RXD7

24PHY_RXD5

PHY_TXC_GTXCLK 24

9 VRN_32

9 VRP_32

SFP_TX_DISABLE_FPGA 23

DVI_D11 29

29DVI_D10

DVI_D9 29

DVI_D8 29

DVI_D7 29

29DVI_D6

DVI_D5 29

DVI_D4 29

DVI_D3 29

DVI_D2 29

DVI_D1 29

DVI_D0 29

32DVI_RESET_B_LS

DVI_H 29

9VRN_32

29DVI_XCLK_N

29DVI_XCLK_P

DVI_DE 29

13CLK_33MHZ_SYSACE

DVI_V 29

SYSACE_MPA00 13

SYSACE_MPA02 13

SYSACE_MPA03 13

SYSACE_MPA01 13

SYSACE_D3 13

SYSACE_D2 13

SYSACE_D1 13

SYSACE_D0 13

SYSACE_D7 13

SYSACE_D6 13

SYSACE_D4 13

SYSACE_MPWE 13

SYSACE_MPOE 13

SYSACE_D5 13

SYSACE_MPBRDY 13

SYSACE_MPCE 13

SYSACE_MPA06 13

SYSACE_MPA05 13

SYSACE_MPA04 13

9VRP_32

Page 10: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

MGTREFCLK1N_116_F5

MGTREFCLK1P_116_F6

MGTREFCLK0N_116_H5

MGTREFCLK0P_116_H6

MGTRXN3_116_B6

MGTRXP3_116_B5

MGTTXN3_116_A4

MGTTXP3_116_A3

MGTRXN2_116_D6

MGTRXP2_116_D5

MGTTXN2_116_B2

MGTTXP2_116_B1

MGTRXN1_116_E4

MGTRXP1_116_E3

MGTTXN1_116_C4

MGTTXP1_116_C3

MGTRXN0_116_G4

MGTRXP0_116_G3

MGTTXN0_116_D2

MGTTXP0_116_D1

6vlx240tff1156

BANK 116

DUT

MGTREFCLK1N_114_T5

MGTREFCLK1P_114_T6

MGTREFCLK0N_114_V5

MGTREFCLK0P_114_V6

MGTRXN3_114_R4

MGTRXP3_114_R3

MGTTXN3_114_P2

MGTTXP3_114_P1

MGTRXN2_114_U4

MGTRXP2_114_U3

MGTTXN2_114_T2

MGTTXP2_114_T1

MGTRXN1_114_W4

MGTRXP1_114_W3

MGTTXN1_114_V2

MGTTXP1_114_V1

MGTRXN0_114_AA4

MGTRXP0_114_AA3

MGTTXN0_114_Y2

MGTTXP0_114_Y1

6vlx240tff1156

BANK 114

DUT

MGTREFCLK1N_112_AH5

MGTREFCLK1P_112_AH6

MGTREFCLK0N_112_AK5

MGTREFCLK0P_112_AK6

MGTRXN3_112_AJ4

MGTRXP3_112_AJ3

MGTTXN3_112_AK2

MGTTXP3_112_AK1

MGTRXN2_112_AL4

MGTRXP2_112_AL3

MGTTXN2_112_AM2

MGTTXP2_112_AM1

MGTRXN1_112_AM6

MGTRXP1_112_AM5

MGTTXN1_112_AN4

MGTTXP1_112_AN3

MGTRXN0_112_AP6

MGTRXP0_112_AP5

MGTTXN0_112_AP2

MGTTXP0_112_AP1

6vlx240tff1156

BANK 112

DUT

MGTRREF_115_AN7

MGTAVTTRCAL_115_AP7

MGTREFCLK1N_115_M5

MGTREFCLK1P_115_M6

MGTREFCLK0N_115_P5

MGTREFCLK0P_115_P6

MGTRXN3_115_J4

MGTRXP3_115_J3

MGTTXN3_115_F2

MGTTXP3_115_F1

MGTRXN2_115_K6

MGTRXP2_115_K5

MGTTXN2_115_H2

MGTTXP2_115_H1

MGTRXN1_115_L4

MGTRXP1_115_L3

MGTTXN1_115_K2

MGTTXP1_115_K1

MGTRXN0_115_N4

MGTRXP0_115_N3

MGTTXN0_115_M2

MGTTXP0_115_M1

6vlx240tff1156

BANK 115

DUT

MGTREFCLK1N_113_AB5

MGTREFCLK1P_113_AB6

MGTREFCLK0N_113_AD5

MGTREFCLK0P_113_AD6

MGTRXN3_113_AC4

MGTRXP3_113_AC3

MGTTXN3_113_AB2

MGTTXP3_113_AB1

MGTRXN2_113_AE4

MGTRXP2_113_AE3

MGTTXN2_113_AD2

MGTTXP2_113_AD1

MGTRXN1_113_AF6

MGTRXP1_113_AF5

MGTTXN1_113_AF2

MGTTXP1_113_AF1

MGTRXN0_113_AG4

MGTRXP0_113_AG3

MGTTXN0_113_AH2

MGTTXP0_113_AH1

6vlx240tff1156

BANK 113

DUT

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

LX240T ONLY

SCHEM, ROHS COMPLIANT

LX240T ONLY

ML605

FPGA MGT Banks

FPGA MGT Banks

BF

04

9-17-2009_15:42

4810

D

FMC_HPC_DP4_M2C_N 16

10FMC_HPC_GBTCLK1_M2C_C_N

10FMC_HPC_GBTCLK1_M2C_C_P

10FMC_HPC_GBTCLK0_M2C_C_N

10FMC_HPC_GBTCLK0_M2C_C_P

FMC_HPC_GBTCLK0_M2C_N16

FMC_HPC_GBTCLK0_M2C_P16

FMC_LPC_GBTCLK0_M2C_C_N 10

FMC_LPC_GBTCLK0_M2C_C_P 10

AB5

AB6

AD5

AD6

AC4

AC3

AB2

AB1

AE4

AE3

AD2

AD1

AF6

AF5

AF2

AF1

AG4

AG3

AH2

AH1

U1

22 FMC_HPC_CLK2_M2C_MGT_P

1 2

X5R

10V

0.1UF

C399

1 2

X5R

10V

0.1UF

C423

AN7

AP7

M5

M6

P5

P6

J4

J3

F2

F1

K6

K5

H2

H1

L4

L3

K2

K1

N4

N3

M2

M1

U1

FMC_LPC_GBTCLK0_M2C_N20

21C422

0.1UF 10V

X5R

FMC_LPC_GBTCLK0_M2C_P20

AH5

AH6

AK5

AK6

AJ4

AJ3

AK2

AK1

AL4

AL3

AM2

AM1

AM6

AM5

AN4

AN3

AP6

AP5

AP2

AP1

U1

10FMC_HPC_CLK2_M2C_MGT_C_N

10FMC_HPC_CLK2_M2C_MGT_C_N

10FMC_HPC_CLK2_M2C_MGT_C_P

22 FMC_HPC_CLK2_M2C_MGT_N

10FMC_HPC_CLK3_M2C_MGT_C_N

10FMC_HPC_CLK3_M2C_MGT_C_P T5

T6

V5

V6

R4

R3

P2

P1

U4

U3

T2

T1

W4

W3

V2

V1

AA4

AA3

Y2

Y1

U1

F5

F6

H5

H6

B6

B5

A4

A3

D6

D5

B2

B1

E4

E3

C4

C3

G4

G3

D2

D1

U1

1

2

R213

100

1/16W

1%

MGT_AVTT

PCIE_TX7_P 21

PCIE_TX7_N 21

PCIE_RX7_P 21

PCIE_RX7_N 21

PCIE_TX6_P 21

PCIE_TX6_N 21

PCIE_RX6_P 21

PCIE_RX6_N 21

PCIE_TX5_P 21

PCIE_TX5_N 21

PCIE_RX5_P 21

PCIE_RX5_N 21

PCIE_TX4_P 21

PCIE_TX4_N 21

PCIE_RX4_P 21

PCIE_RX4_N 21

22PCIE_250M_MGT1_P

22PCIE_250M_MGT1_N

NC

NC

16FMC_HPC_DP7_C2M_P

16FMC_HPC_DP7_C2M_N

16FMC_HPC_DP7_M2C_P

16FMC_HPC_DP7_M2C_N

16FMC_HPC_DP6_C2M_P

16FMC_HPC_DP6_C2M_N

FMC_HPC_DP6_M2C_P 16

FMC_HPC_DP6_M2C_N 16

16FMC_HPC_DP5_C2M_P

16FMC_HPC_DP5_C2M_N

16FMC_HPC_DP5_M2C_P

16FMC_HPC_DP5_M2C_N

FMC_HPC_DP4_C2M_P 16

FMC_HPC_DP4_C2M_N 16

FMC_HPC_DP4_M2C_P 16

FMC_LPC_DP0_C2M_P 20

FMC_LPC_DP0_C2M_N 20

20FMC_LPC_DP0_M2C_P

20FMC_LPC_DP0_M2C_N

23SFP_TX_P

23SFP_TX_N

SFP_RX_P 23

SFP_RX_N 23

SMA_TX_P 30

SMA_TX_N 30

SMA_RX_P 30

SMA_RX_N 30

SGMII_TX_P 24

SGMII_TX_N 24

SGMII_RX_P 24

SGMII_RX_N 24

SGMIICLK_QO_P 30

SGMIICLK_QO_N 30

SMA_REFCLK_P 30

SMA_REFCLK_N 30

16FMC_HPC_DP3_C2M_P

16FMC_HPC_DP3_C2M_N

FMC_HPC_DP3_M2C_P 16

FMC_HPC_DP3_M2C_N 16

FMC_HPC_DP2_C2M_P 16

FMC_HPC_DP2_C2M_N 16

FMC_HPC_DP2_M2C_P 16

FMC_HPC_DP2_M2C_N 16

16FMC_HPC_DP1_C2M_P

16FMC_HPC_DP1_C2M_N

16FMC_HPC_DP1_M2C_P

16FMC_HPC_DP1_M2C_N

16FMC_HPC_DP0_C2M_P

16FMC_HPC_DP0_C2M_N

FMC_HPC_DP0_M2C_P 16

FMC_HPC_DP0_M2C_N 16

22 FMC_HPC_CLK3_M2C_MGT_N

22 FMC_HPC_CLK3_M2C_MGT_P FMC_HPC_CLK3_M2C_MGT_C_P10

FMC_HPC_CLK3_M2C_MGT_C_N10

1 2

X5R

10V

0.1UF

C396

21C397

0.1UF 10V

X5R

21C398

0.1UF 10V

X5R

10FMC_HPC_CLK2_M2C_MGT_C_P

21PCIE_TX3_P

21PCIE_TX3_N

21PCIE_RX3_P

21PCIE_RX3_N

21PCIE_TX2_P

21PCIE_TX2_N

21PCIE_RX2_P

21PCIE_RX2_N

21PCIE_TX1_P

21PCIE_TX1_N

21PCIE_RX1_P

21PCIE_RX1_N

21PCIE_TX0_P

21PCIE_TX0_N

21PCIE_RX0_P

21PCIE_RX0_N

PCIE_100M_MGT0_P 22

PCIE_100M_MGT0_N 22

1 2

X5R

10V

0.1UF

C425

21C424

0.1UF 10V

X5R

FMC_HPC_GBTCLK0_M2C_C_P 10

FMC_HPC_GBTCLK0_M2C_C_N 10

FMC_LPC_GBTCLK0_M2C_C_P 10

FMC_LPC_GBTCLK0_M2C_C_N 10

1 2

X5R

10V

0.1UF

C427

21C426

0.1UF 10V

X5R

FMC_HPC_GBTCLK1_M2C_P16

FMC_HPC_GBTCLK1_M2C_N16

10FMC_HPC_GBTCLK1_M2C_C_P

10FMC_HPC_GBTCLK1_M2C_C_N

Page 11: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCCINT_FPGA

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCAUX_AA10

VCCAUX_AA22

VCCAUX_N10

VCCAUX_N22

VCCAUX_P9

VCCAUX_P23

VCCAUX_R22

VCCAUX_T9

VCCAUX_U22

VCCAUX_V9

VCCAUX_W10

VCCAUX_W22

VCCAUX_Y23

6vlx240tff1156

BANK VCCAUX

DUT

MGTAVCC_N_C6

MGTAVCC_N_E6

MGTAVCC_N_G6

MGTAVCC_N_J6

MGTAVCC_N_L6

MGTAVCC_N_N6

6vlx240tff1156

BANK MGTAVCC_N

DUT

MGTAVCC_S_AA6

MGTAVCC_S_AC6

MGTAVCC_S_AE6

MGTAVCC_S_AG6

MGTAVCC_S_AJ6

MGTAVCC_S_AL6

MGTAVCC_S_AN6

MGTAVCC_S_R6

MGTAVCC_S_U6

MGTAVCC_S_W6

6vlx240tff1156

BANK MGTAVCC_S

DUT

MGTAVTT_S_AC2

MGTAVTT_S_AD3

MGTAVTT_S_AG2

MGTAVTT_S_AH3

MGTAVTT_S_AL2

MGTAVTT_S_AM3

MGTAVTT_S_R2

MGTAVTT_S_T3

MGTAVTT_S_W2

MGTAVTT_S_Y3

6vlx240tff1156

BANK MGTAVTT_S

DUT

MGTAVTT_N_C2

MGTAVTT_N_D3

MGTAVTT_N_G2

MGTAVTT_N_H3

MGTAVTT_N_L2

MGTAVTT_N_M3

6vlx240tff1156

BANK MGTAVTT_N

DUT

VCCINT_AA12

VCCINT_AA14

VCCINT_AA16

VCCINT_AA18

VCCINT_AA20

VCCINT_AB11

VCCINT_AB13

VCCINT_AB15

VCCINT_AB17

VCCINT_AB19

VCCINT_AB21

VCCINT_M19

VCCINT_M21

VCCINT_N12

VCCINT_N14

VCCINT_N16

VCCINT_N18

VCCINT_N20

VCCINT_P11

VCCINT_P13

VCCINT_P15

VCCINT_P17

VCCINT_P19

VCCINT_P21

VCCINT_R10

VCCINT_R12

VCCINT_R14

VCCINT_R16

VCCINT_R18

VCCINT_R20

VCCINT_T11

VCCINT_T13

VCCINT_T15

VCCINT_T19

VCCINT_T21

VCCINT_U10

VCCINT_U12

VCCINT_U14

VCCINT_U16

VCCINT_U20

VCCINT_V11

VCCINT_V13

VCCINT_V15

VCCINT_V19

VCCINT_V21

VCCINT_W12

VCCINT_W14

VCCINT_W16

VCCINT_W20

VCCINT_Y11

VCCINT_Y13

VCCINT_Y15

VCCINT_Y17

VCCINT_Y19

VCCINT_Y21

6vlx240tff1156

BANK VCCINT

DUT

VCCAUX

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

ML605

FPGA Power

FPGA Power

BF

04

9-17-2009_15:42

4811

D

AA12

AA14

AA16

AA18

AA20

AB11

AB13

AB15

AB17

AB19

AB21

M19

M21

N12

N14

N16

N18

N20

P11

P13

P15

P17

P19

P21

R10

R12

R14

R16

R18

R20

T11

T13

T15

T19

T21

U10

U12

U14

U16

U20

V11

V13

V15

V19

V21

W12

W14

W16

W20

Y11

Y13

Y15

Y17

Y19

Y21

U1

C2

D3

G2

H3

L2

M3

U1

AC2

AD3

AG2

AH3

AL2

AM3

R2

T3

W2

Y3

U1

AA6

AC6

AE6

AG6

AJ6

AL6

AN6

R6

U6

W6

U1

C6

E6

G6

J6

L6

N6

U1

AA10

AA22

N10

N22

P9

P23

R22

T9

U22

V9

W10

W22

Y23

U1

MGT_AVCC

MGT_AVCC

MGT_AVTT

MGT_AVTT

Page 12: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND_A1

GND_A2

GND_A5

GND_A6

GND_A7

GND_A17

GND_A27

GND_A34

GND_AA1

GND_AA2

GND_AA5

GND_AA7

GND_AA9

GND_AA11

GND_AA13

GND_AA15

GND_AA17

GND_AA19

GND_AA21

GND_AA27

GND_AB3

GND_AB4

GND_AB7

GND_AB8

GND_AB12

GND_AB14

GND_AB16

GND_AB18

GND_AB20

GND_AB22

GND_AB24

GND_AB34

GND_AC1

GND_AC5

GND_AC7

GND_AC11

GND_AC21

GND_AC31

GND_AD4

GND_AD7

GND_AD18

GND_AD28

GND_AE1

GND_AE2

GND_AE5

GND_AE7

GND_AE15

GND_AE25

GND_AF3

GND_AF4

GND_AF7

GND_AF12

GND_AF22

GND_AF32

GND_AG1

GND_AG5

GND_AG7

GND_AG9

GND_AG19

GND_AG29

GND_AH4

GND_AH7

GND_AH16

GND_AH26

GND_AJ1

GND_AJ2

GND_AJ5

GND_AJ7

GND_AJ13

GND_AJ23

GND_AJ33

GND_AK3

GND_AK4

GND_AK7

GND_AK10

GND_AK20

GND_AK30

GND_AL1

GND_AL5

GND_AL7

GND_AL17

GND_AL27

GND_AM4

GND_AM7

GND_AM8

GND_AM14

GND_AM24

GND_AM34

GND_AN1

GND_AN2

GND_AN5

GND_AN8

GND_AN11

GND_AN21

GND_AN31

GND_AP3

GND_AP4

GND_AP8

GND_AP18

GND_AP28

GND_AP34

GND_B3

GND_B4

GND_B7

GND_B14

GND_B24

GND_C1

GND_C5

GND_C7

GND_C11

GND_C21

GND_C31

GND_D4

GND_D7

GND_D8

GND_D18

GND_D28

GND_E1

GND_E2

GND_E5

GND_E7

GND_E15

GND_E25

GND_F3

GND_F4

GND_F7

GND_F12

GND_F22

GND_F32

GND_G1

GND_G5

GND_G7

GND_G9

GND_G19

GND_G29

GND_H4

GND_H7

GND_H16

GND_H26

GND_J1

GND_J2

GND_J5

GND_J7

GND_J8

GND_J13

GND_J23

GND_J33

GND_K3

GND_K4

GND_K7

GND_K10

GND_K20

GND_K30

GND_L1

GND_L5

GND_L7

GND_L17

GND_L27

GND_M4

GND_M7

GND_M14

GND_M20

GND_M24

GND_M34

GND_N1

GND_N2

GND_N5

GND_N7

GND_N9

GND_N11

GND_N13

GND_N15

GND_N17

GND_N19

GND_N21

GND_N31

GND_P3

GND_P4

GND_P7

GND_P10

GND_P12

GND_P14

GND_P16

GND_P18

GND_P20

GND_P22

GND_P28

GND_R1

GND_R5

GND_R7

GND_R9

GND_R11

GND_R13

GND_R15

GND_R17

GND_R19

GND_R21

GND_R23

GND_R25

GND_T4

GND_T7

GND_T10

GND_T12

GND_T14

GND_T16

GND_T20

GND_T22

GND_T32

GND_U1

GND_U2

GND_U5

GND_U7

GND_U9

GND_U11

GND_U13

GND_U15

GND_U19

GND_U21

GND_U29

GND_V3

GND_V4

GND_V7

GND_V10

GND_V12

GND_V14

GND_V16

GND_V20

GND_V22

GND_V26

GND_W1

GND_W5

GND_W7

GND_W9

GND_W11

GND_W13

GND_W15

GND_W19

GND_W21

GND_W23

GND_W33

GND_Y4

GND_Y5

GND_Y6

GND_Y7

GND_Y10

GND_Y12

GND_Y14

GND_Y16

GND_Y18

GND_Y20

GND_Y22

GND_Y30

GND_T8

6vlx240tff1156

BANK GND

DUT

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

ML605

FPGA GND

FPGA GND

BF

04

9-17-2009_15:42

4812

D

A1

A2

A5

A6

A7

A17

A27

A34

AA1

AA2

AA5

AA7

AA9

AA11

AA13

AA15

AA17

AA19

AA21

AA27

AB3

AB4

AB7

AB8

AB12

AB14

AB16

AB18

AB20

AB22

AB24

AB34

AC1

AC5

AC7

AC11

AC21

AC31

AD4

AD7

AD18

AD28

AE1

AE2

AE5

AE7

AE15

AE25

AF3

AF4

AF7

AF12

AF22

AF32

AG1

AG5

AG7

AG9

AG19

AG29

AH4

AH7

AH16

AH26

AJ1

AJ2

AJ5

AJ7

AJ13

AJ23

AJ33

AK3

AK4

AK7

AK10

AK20

AK30

AL1

AL5

AL7

AL17

AL27

AM4

AM7

AM8

AM14

AM24

AM34

AN1

AN2

AN5

AN8

AN11

AN21

AN31

AP3

AP4

AP8

AP18

AP28

AP34

B3

B4

B7

B14

B24

C1

C5

C7

C11

C21

C31

D4

D7

D8

D18

D28

E1

E2

E5

E7

E15

E25

F3

F4

F7

F12

F22

F32

G1

G5

G7

G9

G19

G29

H4

H7

H16

H26

J1

J2

J5

J7

J8

J13

J23

J33

K3

K4

K7

K10

K20

K30

L1

L5

L7

L17

L27

M4

M7

M14

M20

M24

M34

N1

N2

N5

N7

N9

N11

N13

N15

N17

N19

N21

N31

P3

P4

P7

P10

P12

P14

P16

P18

P20

P22

P28

R1

R5

R7

R9

R11

R13

R15

R17

R19

R21

R23

R25

T4

T7

T10

T12

T14

T16

T20

T22

T32

U1

U2

U5

U7

U9

U11

U13

U15

U19

U21

U29

V3

V4

V7

V10

V12

V14

V16

V20

V22

V26

W1

W5

W7

W9

W11

W13

W15

W19

W21

W23

W33

Y4

Y5

Y6

Y7

Y10

Y12

Y14

Y16

Y18

Y20

Y22

Y30

T8

U1

Page 13: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC2V5

VCC2V5

VCC2V5

VCC2V5

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

P2

P1

P3

P4

Pushbutton

PARTS=1

LEVEL=STD

NC20

NC19

NC18

NC17

NC16

NC21

NC22

NC23

NC24

NC25

NC11

NC12

NC13

NC14

NC15

NC6

NC7

NC8

NC9

NC10

NC5

NC4

NC3

NC2

CFD08

CFD02

CFD09

MPIRQ

MPCE

MPA06

MPA05

MPA04

MPD15

MPD14

MPD13

MPD12

MPD11

MPD10

MPD09

MPD08

MPD07

MPD06

MPD05

MPD04

MPD03

MPD02

MPD01

MPD00

MPA03

MPA02

MPA01

MPA00

MPWE

MPOE

CFGINIT

CFGPROG

CFGADDR0

CFGADDR1

CFGADDR2

CLK

STATLED

ERRLED

TSTTMS

CFA07

CFA05

CFWAIT

CFA02

91_GND

100_GND

75_GND

83_GND

64_GND

54_GND

46_GND

120_GND

136_GND

129_GND

144_GND

9_GND

18_GND

26_GND

CFCD2

CFD10

CFCD1

CFD03

CFD11

CFD04

CFD12

CFD05

CFD13

CFD06

CFD14

CFD07

CFD15

CFCE1

CFCE2

CFA10

CFD01

CFA00

CFOE

CFA09

CFA08

CFWE

CFA06

CFA03

CFREG

CFA01

CFD00

CFA04

CFGRSVD

111_GND

CFGMODEPIN

35_GND

VCCL_126

110_GND

112_GND

TSTTDO

TSTTCK

TSTTDI

CFGTCK

CFGTMS

CFGTDO

CFGTDI

POR_RESET

POR_TEST

POR_BYPASS

RESET_B

VCCH_128

VCCH_109

VCCH_73

VCCH_92

VCCH_55

VCCH_37

VCCH_17

VCCH_1

VCCL_99

VCCL_94

VCCL_84

VCCL_57

VCCL_25

VCCL_15

VCCL_10

MPBRDY

NC1

(DIE DOWN)

TQFP144

SYSTEMACE

P2

P1

P3

P4

Pushbutton

3_D04

27_D11

2_D03

49_D10

48_D09

23_D02

47_D08

22_D01

20_A00

44_REG

19_A01

18_A02

42_WAIT

17_A03

16_A04

15_A05

14_A06

37_RDY/BSY

12_A07

36_WE

11_A08

10_A09

9_OEI

8_A10

32_CE2

7_CE1I

31_D15

6_D07

30_D14

5_D06

29_D13

4_D05

28_D12

50_GND

38_VCC

13_VCC

46_BVD1

21_D00

45_BVD2

40_VS2

26_CD1

25_CD2

41_RESET

39_CSEL

35_IOWR

34_IORD

33_VS1

24_WP

43_INPACK

1_GND

VCC2V5

VCC2V5

GND OUT

TRI VCC

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

Failsafe Mode EnabledOR =

FPGA & CPU

Combined

"Status LED"

"System ACE"

Silkscreen

FPGA PROG

Silkscreen:

PROG

PC4 Connector

SysACE Failsafe Mode Jumpers

Silkscreen:

"SYSACE RESET"

System ACE CF

Silkscreen

"System ACE"

"Error LED" Disable Sysace

Error LED

41

2 3

U28

33.000MHZ

50PPM

D

SCHEM, ROHS COMPLIANT,

04

13

3-17-2010_8:25

48BF

SYSTEM ACE CF

2 1

J69H-1X2

12

H-1X2J37

12

LED-RED-SMT

DS30 12

R293

140 1%

2 1

1%140

R292

12

LED-GRN-SMT

DS1

1

2

C1

0.1UF

10V

X5R

12

5%

4.7KRP4

8 7 6 5

4321

X5R

10V

0.1UF

CP1

1 2 3 4

5678

CP2

0.1UF

10V

X5R

8 7 6 5

4321

X5R

10V

0.1UF

CP3

86

RP8

4.7K

5%

3

27

2

49

48

23

47

22

20

44

19

18

42

17

16

15

14

37

12

36

11

10

9

8

32

7

31

6

30

5

29

4

28

50

38

13

46

21

45

40

26

25

41

39

35

34

33

24

43

1

U73

N7E50-7516PG-2076

RP4

4.7K

5%

2 1

H-1X2

J38

13

5%

4.7KRP42

1

3

4

SW3

71

40

38

36

34

90

122

124

127

143

28

29

30

31

32

21

22

23

24

27

20

19

16

14

7

8

11

41

42

43

44

45

47

48

49

50

51

52

53

56

58

59

60

61

62

63

65

66

67

68

69

70

76

77

78

79

86

87

88

93

95

96

98

132

135

140

141

91

100

75

83

64

54

46

120

136

129

1449

18

26

13

12

103

104

105

106

107

113

114

115

116

117

118

119

138

121

6

4

123

125

130

131

134

139

3

142

5

137

133

111

89

35

126

110

112

97

101

102

80

85

82

81

72

74

108

33

128

109

73

92

55

37

17

199

94

84

57

25

15

10

39

2

U19

XCCACE-TQ144I

41

RP4

4.7K

5%

4

3

1

2

SW4

SYSACE_TMS_BUF 16

SYSACE_TCK_BUF 16

JTAG_TDO 46

20SYSACE_TDI

2 FPGA_TMS

SYSACE_CFGMODEPIN25

2,25,31 FPGA_INIT_B

VCC3V3

SYSACE_RESET_B 13

SYSACE_RESET_B 13

FPGA_PROG_B2,13,25 SYSACE_ERR_LED 13

SYSACE_MPOE9

SYSACE_MPWE9

SYSACE_MPA009

SYSACE_MPA019

SYSACE_MPA029

SYSACE_MPA039

SYSACE_D09

SYSACE_D19

SYSACE_D29

SYSACE_D39

SYSACE_D49

SYSACE_D59

SYSACE_D69

SYSACE_D79

SYSACE_MPA049

SYSACE_MPA059

SYSACE_MPA069

SYSACE_MPIRQ4

SYSACE_MPCE9

SYSACE_MPBRDY9

FPGA_PROG_B2,13,25

FPGA_PROG_B2,13,25

CLK_33MHZ_SYSACE9

SYSACE_CFGADDR025

2 FPGA_TDI

2 FPGA_TCK

NC

SYSACE_CFGTDI2

NC

SYSACE_CFGADDR225

SYSACE_CFGADDR125

VCC3V3

1

2R339

1%

1.21K

NC

NC

NC

69

5%

4.7KRP8

2

1

1.21K

1%

R340

SYSACE_CFA00

SYSACE_CFA06

SYSACE_CFD00

SYSACE_CFD05

SYSACE_CFD10

SYSACE_CFDE

NC

SYSACE_ERR_LED

SA_ERR_RES

SA_STAT_RES SYSACE_STAT_LED

SYSACE_CFRDBSY

NC

NC

NC

NC

NC

NC

NC

SYSACE_CFCD2

SYSACE_CFD09

SYSACE_CFD02

SYSACE_CFD08

SYSACE_CFD01

SYSACE_CFREG

SYSACE_CFA01

SYSACE_CFA02

SYSACE_CFWAIT

SYSACE_CFA03

SYSACE_CFA04

SYSACE_CFA05

SYSACE_CFA07

SYSACE_CFWE

SYSACE_CFA08

SYSACE_CFA09

SYSACE_CFA10

SYSACE_CFCE2

SYSACE_CFCE1

SYSACE_CFD15

SYSACE_CFD07

SYSACE_CFD14

SYSACE_CFD06

SYSACE_CFD13

SYSACE_CFD12

SYSACE_CFD04

SYSACE_CFD11

SYSACE_CFD03

SYSACE_CFCD1

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

VCC3V3

VCC3V3

NC

NC

NC

NC

NC

NC

NC

NC

NC

SYSACE_ERR_LED 13

Page 14: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC1V5_FPGAVCC1V5_FPGA

VCC1V5_FPGA

VCC1V5_FPGA

VCC2V5_FPGA

VCC2V5_FPGA

VCC2V5_FPGA

VCC2V5_FPGA

VCC2V5_FPGA

VCC2V5_FPGAVCC2V5_FPGA

VCC2V5_FPGA

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCINT_FPGA

VCC2V5_FPGA

VCC2V5_FPGA

VCC2V5_FPGA

VCCAUX

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

ML605

2.2uF: No more than 3" from periphery of FPGA,

0.22uF: No more than 1" from periphery of FPGA,

but as close as possible.

but as close as possible

to FPGA.

330uF, 100uF, 47uF, 33uF: Anywhere on board,

but as close as possible.

VCCINT VCCAUX

PLACEMENT

RULES

VCCO

FPGA Decoupling

FPGA Decoupling

V-6 FF1156 DECOUPLING

D

04

9-17-2009_15:42

4814 BF

1

2

C360

330UF

2.5V

TANT

2

1

TANT

2.5V

330UF

C359

2

1 C119

2.2UF

10V

X7R

FMC_VIO_B_M2C7,18

1

2

C287

47UF

6.3V

TANT

1

2

C285

47UF

6.3V

TANT

1

2

C298

47UF

6.3V

TANT

2

1 C120

2.2UF

10V

X7R

2

1 C124

2.2UF

10V

X7R

2

1 C126

2.2UF

10V

X7R

2

1 C130

2.2UF

10V

X7R

2

1 C133

2.2UF

10V

X7R

2

1 C138

2.2UF

10V

X7R2

1 C225

0.22UF

10V

X7R

2

1 C224

0.22UF

10V

X7R

2

1 C137

2.2UF

10V

X7R

2

1 C139

2.2UF

10V

X7R2

1 C220

0.22UF

10V

X7R

1

2

C292

47UF

6.3V

TANT

1

2

C201

33UF

6.3V

TANT

2

1 C123

2.2UF

10V

X7R

2

1 C226

0.22UF

10V

X7R

1

2

C283

47UF

6.3V

TANT

2

1 C206

0.22UF

10V

X7R

2

1 C205

0.22UF

10V

X7R

2

1 C204

0.22UF

10V

X7R

2

1 C203

0.22UF

10V

X7R

2

1 C202

0.22UF

10V

X7R

2

1 C122

2.2UF

10V

X7R

2

1 C121

2.2UF

10V

X7R

2

1 C209

0.22UF

10V

X7R

2

1 C208

0.22UF

10V

X7R

2

1 C207

0.22UF

10V

X7R

2

1 C210

0.22UF

10V

X7R

2

1 C211

0.22UF

10V

X7R

1

2

C284

47UF

6.3V

TANT

2

1 C125

2.2UF

10V

X7R2

1 C212

0.22UF

10V

X7R

2

1 C213

0.22UF

10V

X7R

1

2

C286

47UF

6.3V

TANT

2

1 C127

2.2UF

10V

X7R2

1 C214

0.22UF

10V

X7R

2

1 C128

2.2UF

10V

X7R2

1 C215

0.22UF

10V

X7R

1

2

C291

47UF

6.3V

TANT

2

1 C132

2.2UF

10V

X7R2

1 C219

0.22UF

10V

X7R

1

2

C290

47UF

6.3V

TANT

2

1 C131

2.2UF

10V

X7R2

1 C218

0.22UF

10V

X7R

1

2

C289

47UF

6.3V

TANT

2

1 C217

0.22UF

10V

X7R

1

2

C288

47UF

6.3V

TANT

2

1 C129

2.2UF

10V

X7R2

1 C216

0.22UF

10V

X7R

1

2

C297

47UF

6.3V

TANT

1

2

C296

47UF

6.3V

TANT

1

2

C295

47UF

6.3V

TANT

2

1 C136

2.2UF

10V

X7R2

1 C223

0.22UF

10V

X7R

1

2

C294

47UF

6.3V

TANT

2

1 C135

2.2UF

10V

X7R2

1 C222

0.22UF

10V

X7R

1

2

C293

47UF

6.3V

TANT

2

1 C134

2.2UF

10V

X7R2

1 C221

0.22UF

10V

X7R

Page 15: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VSS24

VSS52

VSS51

VSS50

VSS49

VSS48

VSS47

VSS46

VSS45

VSS44

VSS43

VSS42

VSS41

VSS40

VSS39

VSS38

VSS37

VSS36

VSS35

VSS34

VSS33

VSS32

VSS31

VSS30

VSS29

VSS28

VSS27

VSS26

A0

A1

A10/AP

A11

A12_BC_N

A13

A14

A15

A2

A3

A4

A5

A6

A7

A8

A9

BA0

BA1

BA2

CAS_B

CK0_N

CK0_P

CK1_N

CK1_P

CKE0

CKE1

DM0

DM1

DM2

DM3

DM4

DM5

DM6

DM7

DQ0

DQ1

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ2

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ3

DQ30

DQ31

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ4

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ48

DQ5

DQ50

DQ51

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ6

DQ60

DQ61

DQ62

DQ63

DQ7

DQ8

DQ9

DQS0_N

DQS0_P

DQS1_N

DQS1_P

DQS2_N

DQS2_P

DQS3_N

DQS3_P

DQS4_N

DQS4_P

DQS5_N

DQS5_P

DQS6_N

DQS6_P

DQS7_N

DQS7_P

EVENT_B

NC1

NC2

ODT0

ODT1

RAS_B

RESET_B

S0_B

S1_B

SA0

SA1

SCL

SDA

TEST

VDD1

VDD10

VDD11

VDD12

VDD13

VDD14

VDD15

VDD16

VDD17

VDD18

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDD9

VDDSPD

VREFCA

VREFDQ

VSS1

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS2

VSS20

VSS21

VSS22

VSS23

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VTT1

VTT2

WE_B

DQ49

DQ52

VSS25

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VTTDDR

VTTVREF

VTTDDR

VTTDDR

VTTVREF

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

DDR3 SO-DIMM

SCHEM, ROHS COMPLIANT

Silkscreen:

Place Near

"DDR3 SO-DIMM"

pin 1 of DIMM

ML605

DDR3 SO-DIMM

D

04

9-17-2009_15:42

4815 BF

2

1 C7

0.1UF

10V

X5R

1

2

X7R

16V

0.01UF

C155

2

1

10V

X5R

10UF

C230

1 2 3 4

5678

X5R

10V

0.1UF

CP8

1 2 3 4

5678

CP7

0.1UF

10V

X5R

8 7 6 5

4321

X5R

10V

0.1UF

CP9

VCC3V3

VCC3V3

VCC3V3

DDR3_CKE1

6

DDR3_CKE0

6

16,32IIC_SCL_MAIN

16,32IIC_SDA_MAIN

DDR3_TEMP_EVENT

6

DDR3_RESET_B

6

DDR3_D6

5

DDR3_DQS0_P

5

DDR3_DQS0_N

5

DDR3_DM0

5

DDR3_D0

5

DDR3_D4

5

DDR3_ODT0

6

DDR3_D62

5

DDR3_D63

5

DDR3_DM3

6

DDR3_DM1

5

DDR3_DQS1_N

5

DDR3_DQS1_P

5

DDR3_D11

5

DDR3_DQS2_N

5

DDR3_DQS2_P

5

DDR3_DM2

5

DDR3_DQS3_N

6

DDR3_DQS3_P

6

DDR3_DQS7_N

5

DDR3_DQS7_P

5

DDR3_DQS6_P

5

DDR3_DM6

5

DDR3_DM7

5

DDR3_DQS6_N

5

DDR3_DQS5_P

5

DDR3_DQS5_N

5

DDR3_DM5

5

DDR3_DQS4_P

6

DDR3_DQS4_N

6

DDR3_DM4

6

2

1

5%

1/16W

4.7K

R26

1

2

R27

4.7K

1/16W

5%

DDR3_BA2

6

DDR3_BA1

6

DDR3_BA0

6

DDR3_RAS_B

6

DDR3_WE_B

6

DDR3_CAS_B

6

DDR3_ODT1

6

DDR3_S1_B

6

DDR3_CLK1_N

6

DDR3_CLK1_P

6

DDR3_CLK0_N

6

DDR3_CLK0_P

6

DDR3_A10

6

DDR3_A5

6

DDR3_A3

6

DDR3_A11

6

DDR3_A7

6

DDR3_A8

6

DDR3_A15

6

DDR3_A14

6

DDR3_A13

6

DDR3_A12

6

DDR3_A9

6

DDR3_A6

6

DDR3_A4

6

DDR3_A2

6

DDR3_A1

6

DDR3_A0

6

1

2

R25

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R24

VCC1V5

VCC1V5

VCC1V5VCC1V5

NC

NC

NC

1

2

C361

330UF

2.5V

TANT

1

2R183

4.75K

1%

1

2

C3

0.1UF

10V

X5R

2

1

1%

4.75K

R184

8 7 6 5

4321

X5R

10V

0.1UF

CP4

1

2

C2

0.1UF

10V

X5R

1

2

X5R

10V

0.1UF

C4

8 7 6 5

4321

X5R

10V

0.1UF

CP6

1 2 3 4

5678

CP5

0.1UF

10V

X5R 2

1 C5

0.1UF

10V

X5R

8 7 6 5

4321

X5R

10V

0.1UF

CP12

1 2 3 4

5678

CP11

0.1UF

10V

X5R

8 7 6 5

4321

X5R

10V

0.1UF

CP10

2

1 C6

0.1UF

10V

X5R

1

2

X5R

10V

0.1UF

C101

2

X5R

10V

0.1UF

C91

2

X5R

10V

0.1UF

C8

2

1

10V

X5R

10UF

C228

2

1

10V

X5R

10UF

C229

DDR3_S0_B

6

DDR3_D32

6

DDR3_D36

6

DDR3_D33

6

DDR3_D37

6

DDR3_D38

6

DDR3_D34

6

DDR3_D39

6

DDR3_D35

6

DDR3_D44

5

DDR3_D40

5

DDR3_D45

5

DDR3_D41

5

DDR3_D42

5

DDR3_D46

5

DDR3_D43

5

DDR3_D47

5

DDR3_D48

5

DDR3_D52

5

DDR3_D49

5

DDR3_D53

5

DDR3_D50

5

DDR3_D54

5

DDR3_D51

5

DDR3_D55

5

DDR3_D56

5

DDR3_D60

5

DDR3_D57

5

DDR3_D61

5

DDR3_D58

5

DDR3_D59

5

DDR3_D10

5

DDR3_D31

6

DDR3_D27

6

DDR3_D30

6

DDR3_D26

6

DDR3_D29

6

DDR3_D25

6

DDR3_D28

6

DDR3_D24

6

DDR3_D23

5

DDR3_D19

5

DDR3_D22

5

DDR3_D18

5

DDR3_D21

5

DDR3_D17

5

DDR3_D20

5

DDR3_D16

5

DDR3_D15

5

DDR3_D14

5

DDR3_D9

5

DDR3_D8

5

DDR3_D13

5

DDR3_D12

5

DDR3_D3

5

DDR3_D2

5

DDR3_D7

5

DDR3_D1

5

DDR3_D5

5

VCC1V5

66

196

195

190

189

185

184

179

178

173

172

168

167

162

161

156

155

151

150

145

144

139

138

134

133

128

127

72

98

97

107

84

83

119

80

78

96

95

92

91

90

86

89

85

109

108

79

115

103

101

104

102

73

74

11

28

46

63

136

153

170

187

5 7

33

35

22

24

34

36

39

41

51

53

15

40

42

50

52

57

59

67

69

56

58

17

68

70

129

131

141

143

130

132

140

142

4

147

149

157

159

146

148

158

160

163

6

175

177

166

174

176

181

183

191

193

16

180

182

192

194

18

21

23

10

12

27

29

45

47

62

64

135

137

152

154

169

171

186

188

198

77

122

116

120

110

30

114

121

197

201

202

200

125

75

100

105

106

111

112

117

118

123

124

76

81

82

87

88

93

94

99

199

126

1

2

26

31

32

37

38

43

44

48

49

543

55

60

61

658 9

13

14

19

20

25

203

204

113

165

164

71

J1

Page 16: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC2V5 VCC12_PVCC3V3

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

Y8

Y1

Y3

Y4

Y5

Y6

Y7

Y2

OE1_N

A1

A3

A4

A2

A5

A8

A7

A6

GND

SN74LV541APWR

OE2_N

VCC

3P3V_4

GA1

TRST_L

TMS

3P3VAUX

TDO

TDI

TCK

LA26_N

LA26_P

LA23_N

LA17_N_CC

LA17_P_CC

LA13_N

LA13_P

LA09_N

LA09_P

LA05_N

LA05_P

LA01_N_CC

LA01_P_CC

GBTCLK0_M2C_N

GBTCLK0_M2C_P

PG_C2M

LA23_P

3P3V_2

3P3V_3

DP5_C2M_N

DP5_C2M_P

DP4_C2M_N

DP4_C2M_P

DP3_C2M_N

DP3_C2M_P

DP2_C2M_N

DP2_C2M_P

DP1_C2M_N

DP1_C2M_P

DP5_M2C_N

DP5_M2C_P

DP4_M2C_N

DP4_M2C_P

DP3_M2C_N

DP3_M2C_P

DP2_M2C_N

DP2_M2C_P

DP1_M2C_N

DP1_M2C_P

DP6_C2M_P

DP7_C2M_N

DP7_C2M_P

DP8_C2M_N

DP8_C2M_P

DP9_C2M_N

DP9_C2M_P

GBTCLK1_M2C_N

GBTCLK1_M2C_P

DP6_M2C_N

DP6_M2C_P

DP7_M2C_N

DP7_M2C_P

DP8_M2C_N

DP8_M2C_P

DP9_M2C_N

DP6_C2M_N

DP9_M2C_P

RES0

RES1

VCC3V3

VCC12_P

VCC3V3

3P3V_1

12P0V_2

12P0V_1

GA0

SDA

SCL

LA27_N

LA27_P

LA18_N_CC

LA18_P_CC

LA14_N

LA14_P

LA10_N

LA10_P

LA06_N

LA06_P

DP0_M2C_N

DP0_M2C_P

DP0_C2M_N

DP0_C2M_P

ANSI/VITA 57.1-2008 Version 1.1

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

FMC HPC Header

FMC HPC Header, Rows A, B, C, D

ML605

BF

04

9-17-2009_15:42

4816

D

2

1 C414

1UF

16V

X7R

DVI_GPIO1_FMC_C2M_PG 17,20,32

C39

C37

C35

C34

C31

C30

C27

C26

C23

C22

C19

C18

C15

C14

C11

C10

C7

C6

C3

C2

J64

ASP_134486_01

1

2

C412

1UF

50V

ELEC

2

1 C415

1UF

16V

X7R

VCC3V3

JTAG_TDI46

B36

B33

B32

B29

B28

B25

B24

B21

B20

B17

B16

B13

B12

B9

B8

B5

B37

B4

B40

B1

J64

ASP_134486_01

A39

A38

A35

A34

A31

A30

A27

A26

A23

A22

A19

A18

A15

A14

A11

A10

A7

A6

A3

A2

J64

ASP_134486_01

D40

D35

D34

D33

D32

D31

D30

D29

D27

D26

D24

D21

D20

D18

D17

D15

D14

D12

D11

D9

D8

D5

D4

D1

D23

D36

D38

J64

ASP_134486_01

NC

VCC3V3

2

1 C390

0.1UF

10V

X5R

11

18

16

15

14

13

12

17

1

2

4

5

3

6

9

8

7

10

19

20

U88

1

2

3

J17

H-1X3

FMC_LPC_TDI20

FMC_TDI_BUF16

16FMC_HPC_TDO

16FMC_TDI_BUF

FMC_HPC_TCK_BUF 16

FMC_TMS_BUF 16,20

FMC_HPC_LA27_P 8

NC

FMC_HPC_DP1_M2C_P 10

10FMC_HPC_DP0_M2C_N

10FMC_HPC_DP0_M2C_P

FMC_HPC_DP0_C2M_N 10

FMC_HPC_DP0_C2M_P 10FMC_HPC_DP1_M2C_N 10

FMC_HPC_DP1_C2M_P 10

FMC_HPC_DP1_C2M_N 10

IIC_SCL_MAIN 15,32

IIC_SDA_MAIN 15,32

8FMC_HPC_LA06_P

10FMC_HPC_GBTCLK1_M2C_N

10FMC_HPC_GBTCLK1_M2C_P

8FMC_HPC_LA27_N

8FMC_HPC_LA18_CC_N

8FMC_HPC_LA14_P

8FMC_HPC_LA10_P

10FMC_HPC_DP5_C2M_P

10FMC_HPC_DP5_M2C_N

10FMC_HPC_DP5_M2C_P

FMC_HPC_DP3_M2C_N 10

FMC_HPC_DP4_M2C_P 10

FMC_HPC_DP3_M2C_P 10

FMC_HPC_DP2_M2C_P 10

FMC_HPC_DP4_M2C_N 10

8FMC_HPC_LA18_CC_P

8FMC_HPC_LA14_N

8FMC_HPC_LA10_N

8FMC_HPC_LA06_N

FMC_HPC_DP2_M2C_N 10

10FMC_HPC_DP7_M2C_P

10FMC_HPC_DP7_M2C_N

10FMC_HPC_DP6_M2C_P

10FMC_HPC_DP6_M2C_N

FMC_HPC_DP2_C2M_N 10

FMC_HPC_DP2_C2M_P 10

10FMC_HPC_DP3_C2M_N

10FMC_HPC_DP3_C2M_P

FMC_HPC_DP4_C2M_N 10

FMC_HPC_DP4_C2M_P 10

10FMC_HPC_DP5_C2M_N

FMC_HPC_DP7_C2M_N 10

FMC_HPC_DP7_C2M_P 10

10FMC_HPC_DP6_C2M_N

10FMC_HPC_DP6_C2M_P

8FMC_HPC_LA23_N

10FMC_HPC_GBTCLK0_M2C_P

10FMC_HPC_GBTCLK0_M2C_N

8FMC_HPC_LA01_CC_P

8FMC_HPC_LA01_CC_N

8FMC_HPC_LA05_P

8FMC_HPC_LA05_N

8FMC_HPC_LA09_P

8FMC_HPC_LA09_N

8FMC_HPC_LA13_P

8FMC_HPC_LA13_N

8FMC_HPC_LA17_CC_P

8FMC_HPC_LA17_CC_N

8FMC_HPC_LA23_P

8FMC_HPC_LA26_P

8FMC_HPC_LA26_N

NC

NC

NC

NC

NC

NC

NC

16 FMC_HPC_TDO

16,20FMC_TMS_BUF

13SYSACE_TCK_BUF

FMC_LPC_TCK_BUF 20

FMC_HPC_TCK_BUF 16

13SYSACE_TMS_BUF

16FMC_TDI_BUF

46 JTAG_TCK

NC

NC

NC

NC

46 JTAG_TMS

NC

NC

1

2

R273

10K

1/16W

5%

Page 17: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC2V5

VCC2V5 VCC2V5

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

HA01_P_CC

HA01_N_CC

HA05_P

HA05_N

HA09_P

HA09_N

HA13_P

HA13_N

HA16_P

HA16_N

HA20_P

HA20_N

HB03_P

HB03_N

HB05_P

HB05_N

HB09_P

HB09_N

HB13_P

HB13_N

HB19_P

HB19_N

HB21_P

HB21_N

VADJ_1

VADJ_3

LA33_N

LA33_P

LA31_N

LA31_P

LA29_N

LA29_P

LA25_N

LA25_P

LA22_N

LA22_P

LA20_N

LA20_P

LA16_N

LA16_P

LA12_N

LA12_P

LA08_N

LA08_P

LA03_N

LA03_P

LA00_N_CC

LA00_P_CC

CLK1_M2C_N

CLK1_M2C_P

VADJ_2

HB20_N

HB20_P

HB16_N

HB16_P

HB12_N

HB12_P

HB08_N

HB08_P

HB04_N

HB04_P

HB02_N

HB02_P

HA19_N

HA19_P

HA15_N

HA15_P

HA12_N

HA12_P

HA08_N

HA08_P

HA04_N

HA04_P

HA00_N_CC

PG_M2C

HA00_P_CC

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

FMC HPC Header

SCHEM, ROHS COMPLIANT

FMC HPC Header, Rows E, F, G

ANSI/VITA 57.1-2008 Version 1.1

ML605

FMC Power Good

D

17 48

9-17-2009_15:42

04

BF

23

1

NDS331N

Q25

VCC3V3

F40

F38

F37

F35

F34

F32

F31

F29

F28

F26

F25

F23

F22

F20

F19

F17

F16

F14

F13

F11

F10

F8

F7

F5

F1

F4

J64

ASP_134486_01

G39

G37

G36

G34

G33

G31

G30

G28

G27

G25

G24

G22

G21

G19

G18

G16

G15

G13

G12

G10

G9

G7

G6

G3

G2

J64

ASP_134486_01

E2

E3

E6

E7

E9

E10

E12

E13

E15

E16

E18

E19

E21

E22

E24

E25

E27

E28

E30

E31

E33

E34

E36

E37

E39

J64

ASP_134486_01

FMC_HPC_HA01_CC_N 7

FMC_HPC_HA20_N 2

FMC_HPC_HA20_P 2

FMC_HPC_HA13_N 7

FMC_HPC_HA13_P 7

FMC_HPC_HA09_N 7

FMC_HPC_HA09_P 7

FMC_HPC_HA05_N 7

FMC_HPC_HA05_P 7

FMC_HPC_HA01_CC_P 7

FMC_HPC_HB03_P 7

FMC_HPC_HB03_N 7

FMC_HPC_HB05_P 7

FMC_HPC_HB05_N 7

FMC_HPC_HB09_P 7

FMC_HPC_HB09_N 7

FMC_HPC_HB13_P 7

FMC_HPC_HB13_N 7

FMC_HPC_HB19_P 7

FMC_HPC_HB19_N 7

FMC_HPC_HA16_P 7

FMC_HPC_HA16_N 7

8FMC_HPC_CLK1_M2C_P

8FMC_HPC_CLK1_M2C_N

FMC_HPC_LA00_CC_P 8

FMC_HPC_LA00_CC_N 8

FMC_HPC_LA03_P 8

FMC_HPC_LA03_N 8

FMC_HPC_LA08_P 8

FMC_HPC_LA08_N 8

FMC_HPC_LA12_P 8

FMC_HPC_LA12_N 8

FMC_HPC_LA16_P 8

FMC_HPC_LA16_N 8

FMC_HPC_LA20_P 8

FMC_HPC_LA20_N 8

FMC_HPC_LA22_P 8

FMC_HPC_LA22_N 8

FMC_HPC_LA25_P 8

FMC_HPC_LA25_N 8

FMC_HPC_LA29_P 8

FMC_HPC_LA29_N 8

FMC_HPC_LA31_P 8

FMC_HPC_LA31_N 8

FMC_HPC_LA33_P 8

FMC_HPC_LA33_N 8

2

1R378

200

1/16W

5%

21

LED-GRN-SMT

DS32

7FMC_HPC_HA00_CC_P

FMC_HPC_HA00_CC_N 7

FMC_HPC_HA04_P 7

FMC_HPC_HA04_N 7

FMC_HPC_HA08_P 7

FMC_HPC_HA08_N 7

FMC_HPC_HA12_P 7

FMC_HPC_HA12_N 7

FMC_HPC_HA15_P 7

FMC_HPC_HA15_N 7

FMC_HPC_HA19_P 2

FMC_HPC_HA19_N 2

FMC_HPC_HB02_P 7

FMC_HPC_HB02_N 7

FMC_HPC_HB04_P 7

FMC_HPC_HB04_N 7

FMC_HPC_HB08_P 7

FMC_HPC_HB08_N 7

FMC_HPC_HB12_P 7

FMC_HPC_HB12_N 7

FMC_HPC_HB16_P 7

FMC_HPC_HB16_N 7

NC

NC

NC

NC

2

1

1%

1/16W

10.0K

R381

VCC3V3

32FMC_HPC_PG_M2C

VCC3V3

2

1

1%

1/16W

10.0K

R407

DVI_GPIO1_FMC_C2M_PG16,20,32

Page 18: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC2V5

VCC2V5

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VIO_B_M2C_1

HB18_N

HB18_P

HB15_N

HB15_P

HB11_N

HB11_P

HB07_N

HB07_P

HB01_N

HB01_P

HA22_N

HA22_P

HA18_N

HA18_P

HA14_N

HA14_P

HA11_N

HA11_P

HA07_N

HA07_P

HA03_N

HA03_P

CLK3_M2C_N

CLK3_M2C_P

VIO_B_M2C_2

HB17_N_CC

HB17_P_CC

HB14_N

HB14_P

HB10_N

HB10_P

HB06_N_CC

HB06_P_CC

HB00_N_CC

HB00_P_CC

HA23_N

HA23_P

HA21_N

HA21_P

HA17_N_CC

HA17_P_CC

HA10_N

HA10_P

HA06_N

HA06_P

HA02_N

HA02_P

CLK2_M2C_N

CLK2_M2C_P

VREF_B_M2C

VADJ_4

LA32_N

LA32_P

LA30_N

LA30_P

LA28_N

LA28_P

LA24_N

LA24_P

LA21_N

LA21_P

LA19_N

LA19_P

LA15_N

LA15_P

LA11_N

LA11_P

LA07_N

LA07_P

LA04_N

LA04_P

LA02_N

LA02_P

CLK0_M2C_N

CLK0_M2C_P

PRSNT_M2C_L

VREF_A_M2C

ANSI/VITA 57.1-2008 Version 1.1

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

ML605

FMC HPC Header, Rows H, J, K

FMC HPC Header, Rows H, J, K

BF

04

9-17-2009_15:42

4818

D

H40

H38

H37

H35

H34

H32

H31

H29

H28

H26

H25

H23

H22

H20

H19

H17

H16

H14

H13

H11

H10

H8

H7

H5

H4

H2

H1

J64

ASP_134486_01

FMC_HPC_HB06_CC_P 7

K40

K38

K37

K35

K34

K32

K31

K29

K28

K26

K25

K23

K22

K20

K19

K17

K16

K14

K13

K11

K10

K8

K7

K5

K4

K1

J64

ASP_134486_01

J39

J37

J36

J34

J33

J31

J30

J28

J27

J25

J24

J22

J21

J19

J18

J16

J15

J13

J12

J10

J9

J7

J6

J3

J2

J64

ASP_134486_01

2

1

5%

1/16W

4.7K

R28

7,14,18FMC_VIO_B_M2C

FMC_VIO_B_M2C 7,14,18

7FMC_HPC_HB17_CC_N

NC

FMC_HPC_LA02_N 8

FMC_HPC_LA02_P 8

22FMC_HPC_CLK3_M2C_N

22FMC_HPC_CLK3_M2C_P

FMC_HPC_HA22_N 2

FMC_HPC_HA22_P 2

2FMC_HPC_HA23_N

2FMC_HPC_HA23_P

2FMC_HPC_HA17_CC_N

2FMC_HPC_HA17_CC_P

FMC_HPC_HB00_CC_P 7

2FMC_HPC_HA18_N

2FMC_HPC_HA18_P

FMC_HPC_HA14_N 7

FMC_HPC_HA14_P 7

FMC_HPC_HA11_N 7

FMC_HPC_HA11_P 7

FMC_HPC_HA07_N 7

FMC_HPC_HA07_P 7

FMC_HPC_HA03_N 7

FMC_HPC_HA03_P 7

2FMC_HPC_HA21_N

2FMC_HPC_HA21_P

FMC_HPC_HA10_N 7

FMC_HPC_HA10_P 7

FMC_HPC_HA06_N 7

FMC_HPC_HA06_P 7

FMC_HPC_HA02_N 7

FMC_HPC_HA02_P 7

4FMC_HPC_CLK0_M2C_N

4FMC_HPC_CLK0_M2C_P

FMC_HPC_HB17_CC_P 7

FMC_HPC_HB14_N 7

FMC_HPC_HB14_P 7

FMC_HPC_HB10_N 7

FMC_HPC_HB10_P 7

FMC_HPC_HB06_CC_N 7

FMC_HPC_HB00_CC_N 7

FMC_HPC_HB18_N 7

FMC_HPC_HB18_P 7

FMC_HPC_HB15_N 7

FMC_HPC_HB15_P 7

FMC_HPC_HB11_N 7

FMC_HPC_HB11_P 7

FMC_HPC_HB07_N 7

FMC_HPC_HB07_P 7

FMC_HPC_HB01_N 7

FMC_HPC_HB01_P 7

FMC_HPC_LA32_N 8

FMC_HPC_LA32_P 8

FMC_HPC_LA30_N 8

FMC_HPC_LA30_P 8

FMC_HPC_LA28_N 8

FMC_HPC_LA28_P 8

FMC_HPC_LA24_N 8

FMC_HPC_LA24_P 8

FMC_HPC_LA21_N 8

FMC_HPC_LA21_P 8

FMC_HPC_LA19_N 8

FMC_HPC_LA19_P 8

FMC_HPC_LA15_N 8

FMC_HPC_LA15_P 8

FMC_HPC_LA11_N 8

FMC_HPC_LA11_P 8

FMC_HPC_LA07_N 8

FMC_HPC_LA07_P 8

FMC_HPC_LA04_N 8

FMC_HPC_LA04_P 8

FMC_HPC_PRSNT_M2C_L8 22FMC_HPC_CLK2_M2C_N

22FMC_HPC_CLK2_M2C_P

NC

Page 19: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND_159

GND_158

GND_157

GND_156

GND_155

GND_154

GND_153

GND_152

GND_151

GND_150

GND_149

GND_148

GND_147

GND_146

GND_145

GND_144

GND_143

GND_142

GND_141

GND_140

GND_139

GND_138

GND_137

GND_136

GND_135

GND_134

GND_133

GND_132

GND_131

GND_130

GND_129

GND_128

GND_127

GND_126

GND_125

GND_124

GND_123

GND_122

GND_121

GND_120

GND_119

GND_118

GND_117

GND_116

GND_115

GND_114

GND_113

GND_112

GND_111

GND_110

GND_109

GND_108

GND_107

GND_106

GND_105

GND_104

GND_103

GND_102

GND_101

GND_100

GND_99

GND_98

GND_97

GND_96

GND_95

GND_94

GND_93

GND_92

GND_91

GND_90

GND_89

GND_88

GND_87

GND_86

GND_85

GND_84

GND_83

GND_82

GND_81

GND_80

GND_79

GND_78

GND_77

GND_76

GND_75

GND_74

GND_70

GND_69

GND_68

GND_67

GND_66

GND_65

GND_64

GND_63

GND_62

GND_61

GND_60

GND_59

GND_58

GND_57

GND_56

GND_55

GND_54

GND_53

GND_52

GND_51

GND_50

GND_49

GND_48

GND_47

GND_46

GND_45

GND_44

GND_43

GND_42

GND_41

GND_40

GND_39

GND_38

GND_37

GND_36

GND_35

GND_34

GND_33

GND_32

GND_31

GND_30

GND_29

GND_28

GND_27

GND_26

GND_25

GND_24

GND_23

GND_22

GND_21

GND_20

GND_19

GND_18

GND_17

GND_16

GND_15

GND_14

GND_13

GND_12

GND_11

GND_10

GND_9

GND_8

GND_7

GND_6

GND_5

GND_4

GND_3

GND_2

GND_1

GND_71

GND_72

GND_73

ANSI/VITA 57.1-2008 Version 1.1

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

ML605

FMC HPC Header

FMC HPC Header, GND

D

19 48

9-17-2009_15:42

04

BF

K39

K36

K33

K30

K27

K24

K21

K18

K15

K12

K9

K6

K3

K2

J40

J38

J35

J32

J29

J26

J23

J20

J17

J14

J11

J8

J5

J4

J1

H39

H36

H33

H30

H27

H24

H21

H18

H15

H12

H9

H6

H3

G40

G38

G35

G32

G29

G26

G23

G20

G17

G14

G11

G8

G5

G4

G1

F39

F36

F33

F30

F27

F24

F21

F18

F15

F12

F9

F6

F3

F2

E40

E38

E35

E32

E29

E26

E23

E20

E17

E14

E11

E8

E5

E4

E1

D25

D22

D19

D16

D13

D10

D7

D6

D3

C40

C38

C36

C33

C32

C29

C28

C25

C24

C21

C20

C17

C16

C13

C12

C9

C8

C5

C4

C1

B39

B38

B35

B34

B31

B30

B27

B26

B23

B22

B19

B18

B15

B14

B11

B10

B7

B6

B3

B2

A40

A37

A36

A33

A32

A29

A28

A25

A24

A21

A20

A17

A16

A13

A12

A9

A8

A5

A4

A1

D28

D37

D39

D2

J64

ASP_134486_01

Page 20: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC2V5 VCC12_PVCC3V3

VCC2V5

VCC2V5

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC12_P

3P3VAUX

3P3V_2

3P3V_3

3P3V_4

GA1

GBTCLK0_M2C_N

GBTCLK0_M2C_P

LA01_N_CC

LA01_P_CC

LA05_N

LA05_P

LA09_N

LA09_P

LA13_N

LA13_P

LA17_N_CC

LA17_P_CC

LA23_N

LA23_P

LA26_N

LA26_P

PG_C2M

TCK

TDI

TDO

TMS

TRST_L

CLK0_M2C_N

CLK0_M2C_P

LA02_N

LA02_P

LA04_N

LA04_P

LA07_N

LA07_P

LA11_N

LA11_P

LA15_N

LA15_P

LA19_N

LA19_P

LA21_N

LA21_P

LA24_N

LA24_P

LA28_N

LA28_P

LA30_N

LA30_P

LA32_N

LA32_P

PRSNT_M2C_L

VADJ_4

VREF_A_M2C

12P0V_1

12P0V_2

3P3V_1

DP0_C2M_N

DP0_C2M_P

DP0_M2C_N

DP0_M2C_P

GA0

LA06_N

LA06_P

LA10_N

LA10_P

LA14_N

LA14_P

LA18_N_CC

LA18_P_CC

LA27_N

LA27_P

SCL

SDA

GND_103

GND_104

GND_105

GND_106

GND_107

GND_108

GND_109

GND_110

GND_111

GND_112

GND_113

GND_114

GND_115

GND_116

GND_117

GND_118

GND_119

GND_120

GND_121

GND_122

GND_123

GND_124

GND_125

GND_126

GND_127

GND_128

GND_129

GND_130

GND_41

GND_42

GND_43

GND_44

GND_45

GND_46

GND_47

GND_48

GND_49

GND_50

GND_51

GND_52

GND_53

GND_54

GND_55

GND_56

GND_57

GND_58

GND_59

GND_60

GND_61

GND_62

GND_63

GND_64

GND_65

GND_66

GND_67

GND_68

GND_69

GND_70

GND_71

GND_72

GND_73

CLK1_M2C_N

CLK1_M2C_P

LA00_N_CC

LA00_P_CC

LA03_N

LA03_P

LA08_N

LA08_P

LA12_N

LA12_P

LA16_N

LA16_P

LA20_N

LA20_P

LA22_N

LA22_P

LA25_N

LA25_P

LA29_N

LA29_P

LA31_N

LA31_P

LA33_N

LA33_P

VADJ_3

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

FMC LPC Connector

SA605 EVALUATION PLATFORM

ANSI/VITA 57.1-2008 Version 1.1

FMC LPC Connector

04

9-17-2009_15:42

4820

D

BF

DVI_GPIO1_FMC_C2M_PG16,17,32

G3

G2

G7

G6

G10

G9

G13

G12

G16

G15

G19

G18

G22

G21

G25

G24

G28

G27

G31

G30

G34

G33

G37

G36

G39

J63

ASP_134603_01

G1

G4

G5

G8

G11

G14

G17

G20

G23

G26

G29

G32

G35

G38

G40

H3

H6

H9

H12

H15

H18

H21

H24

H27

H30

H33

H36

H39

C1

C4

C5

C8

C9

C12

C13

C16

C17

C20

C21

C24

C25

C28

C29

C32

C33

C36

C38

C40

D2

D3

D6

D7

D10

D13

D16

D19

D22

D25

D28

D37

D39

J63

ASP_134603_01

C35

C37

C39

C3

C2

C7

C6

C34

C11

C10

C15

C14

C19

C18

C23

C22

C27

C26

C30

C31

J63

ASP_134603_01

H5

H4

H8

H7

H11

H10

H14

H13

H17

H16

H20

H19

H23

H22

H26

H25

H29

H28

H32

H31

H35

H34

H38

H37

H2

H40

H1

J63

ASP_134603_01

D32

D36

D38

D40

D35

D5

D4

D9

D8

D12

D11

D15

D14

D18

D17

D21

D20

D24

D23

D27

D26

D1

D29

D30

D31

D33

D34

J63

ASP_134603_01

1

2

3

J18

H-1X3

FMC_LPC_IIC_SCL 32

FMC_LPC_IIC_SDA 32

SYSACE_TDI13

20 FMC_LPC_TDO

FMC_LPC_TDO 20

FMC_TMS_BUF 16

16,20FMC_LPC_TDI

FMC_LPC_TDI16,20

16FMC_LPC_TCK_BUF

FMC_LPC_GBTCLK0_M2C_N 10

FMC_LPC_GBTCLK0_M2C_P 104FMC_LPC_PRSNT_M2C_L

10FMC_LPC_DP0_M2C_N

10FMC_LPC_DP0_M2C_P

FMC_LPC_DP0_C2M_N 10

FMC_LPC_DP0_C2M_P 10

VCC3V3

NC

FMC_LPC_CLK1_M2C_P 3

3FMC_LPC_LA01_CC_P

3FMC_LPC_LA06_P

VCC3V3

FMC_LPC_LA17_CC_N 3

FMC_LPC_CLK1_M2C_N 3

FMC_LPC_LA27_N 3

FMC_LPC_CLK0_M2C_P 4

FMC_LPC_CLK0_M2C_N 4

FMC_LPC_LA02_P 3

FMC_LPC_LA02_N 3

FMC_LPC_LA04_P 3

FMC_LPC_LA04_N 3

FMC_LPC_LA07_P 3

FMC_LPC_LA07_N 3

FMC_LPC_LA11_P 3

FMC_LPC_LA11_N 3

FMC_LPC_LA15_P 3

FMC_LPC_LA15_N 3

FMC_LPC_LA19_P 3

FMC_LPC_LA19_N 3

FMC_LPC_LA21_P 3

FMC_LPC_LA21_N 3

FMC_LPC_LA24_P 3

FMC_LPC_LA24_N 3

FMC_LPC_LA28_P 3

FMC_LPC_LA28_N 3

FMC_LPC_LA30_P 3

FMC_LPC_LA30_N 3

FMC_LPC_LA32_P 3

FMC_LPC_LA32_N 3

FMC_LPC_LA05_N 3

FMC_LPC_LA26_N 3

FMC_LPC_LA26_P 3

FMC_LPC_LA23_N 3

FMC_LPC_LA23_P 3

FMC_LPC_LA17_CC_P 3

FMC_LPC_LA13_N 3

FMC_LPC_LA13_P 3

FMC_LPC_LA09_N 3

FMC_LPC_LA09_P 3

FMC_LPC_LA05_P 3

FMC_LPC_LA01_CC_N 3

FMC_LPC_LA33_N 3

FMC_LPC_LA33_P 3

FMC_LPC_LA31_N 3

FMC_LPC_LA31_P 3

FMC_LPC_LA29_N 3

FMC_LPC_LA29_P 3

FMC_LPC_LA25_N 3

FMC_LPC_LA25_P 3

FMC_LPC_LA22_N 3

FMC_LPC_LA22_P 3

FMC_LPC_LA20_N 3

FMC_LPC_LA20_P 3

FMC_LPC_LA16_N 3

FMC_LPC_LA16_P 3

FMC_LPC_LA12_N 3

FMC_LPC_LA12_P 3

FMC_LPC_LA08_N 3

FMC_LPC_LA08_P 3

FMC_LPC_LA03_N 3

FMC_LPC_LA03_P 3

FMC_LPC_LA00_CC_N 3

FMC_LPC_LA00_CC_P 3

FMC_LPC_LA06_N 3

FMC_LPC_LA10_P 3

FMC_LPC_LA10_N 3

FMC_LPC_LA14_P 3

FMC_LPC_LA14_N 3

FMC_LPC_LA18_CC_P 3

FMC_LPC_LA18_CC_N 3

FMC_LPC_LA27_P 3

NC

1

2

C413

1UF

50V

ELEC

2

1 C417

1UF

16V

X7R

2

1 C416

1UF

16V

X7R

Page 21: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC3V3

RESERVED

RESERVED

RESERVED

GND

+3.3V

+3.3V

PRSNT#2

GND

GND

GND

+12V

RESERVED

GND

GND

GND

+12V

SMCLK

SMDAT

+3.3Vaux

WAKE#

KEY

GND

GND

GND

GND

GND

GND

+12V

GND

PETp1

PETn1

PETp2

PETn2

PETp3

PETn3

PETp4

PETn4

GND

GND

PETp5

PETn5

GND

GND

PETp6

PETn6

PETp7

PETn7

GND

PRSNT#2

PRSNT#1

+12V

GND

+12V

GND

JTAG1/TRST#

JTAG2/TCK

JTAG3/TDI

JTAG4/TDO

JTAG5/TMS+3.3V

PRSNT#2

PERST

KEY

REFCLK+

REFCLK-

GND

PETp0

PETn0

PERp0

PERn0

PERp1

PERn1

PERp2

PERn2

PERp3

PERn3

PERp4

PERn4

PERp5

PERn5

PERp6

PERn6

PERp7

PERn7

GND

GND

RESERVED

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

ML605

PCIe 8X Card Edge

PCIe 8X Card Edge

04

9-17-2009_15:42

4821

D

BF

PCIE_CLK_QO_P 22

PCIE_CLK_QO_N 22

PCIE_TX7_C_N

PCIE_TX6_C_N

PCIE_TX6_C_P

PCIE_TX3_C_P

PCIE_TX1_C_N

PCIE_TX0_C_P

1 2

3 4

65

J42

H-2X3

A1

A10

A11

A14

A15

A16

A17

A19

A2

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A3

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A4

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

A5

A6

A7

A8

A9

B10

B11

B15

B16

B17

B18

B19

B2

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B3

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

B43

B44

B45

B46

B47

B48

B49

B5

B6

B7

B8

B9

B1

B4

B14

A18

B12

B13

A12

A13

PCI_E-FINGER-8X

P1

1 2

X5R

10V

0.1UF

C16

1 2

X5R

10V

0.1UF

C15

1

2

R122

DNP

1/16W

1%

NC

1

2

R29

4.7K

1/16W

5%

NC

NC

PCIE_WAKE_B32

10 PCIE_RX0_P

32PCIE_PERST_B

PCIE_RX7_P10

PCIE_RX6_N10

PCIE_RX6_P10

PCIE_RX5_N10

PCIE_RX5_P10

PCIE_RX4_N10

PCIE_RX4_P10

PCIE_RX3_N10

PCIE_RX3_P10

PCIE_RX2_N10

PCIE_RX2_P10

PCIE_RX1_N10

PCIE_RX1_P10

PCIE_RX0_N10

PCIE_TX7_N 10

PCIE_TX7_P 10

PCIE_TX6_N 10

PCIE_TX6_P 10

PCIE_TX5_N 10

PCIE_TX5_P 10

PCIE_TX4_N 10

PCIE_TX4_P 10

PCIE_TX3_N 10

PCIE_TX2_N 10

PCIE_TX3_P 10

PCIE_TX2_P 10

PCIE_TX1_N 10

PCIE_TX1_P 10

PCIE_TX0_N 10

PCIE_TX0_P 10

1 2

X5R

10V

0.1UF

C18

1 2

X5R

10V

0.1UF

C11

1 2

X5R

10V

0.1UF

C12

PCIE_PRSNT_B 21

21 PCIE_PRSNT_X8

21 PCIE_PRSNT_X4

PCIE_PRSNT_X121

1 2

R148

15

1/16W

5%

1 2

X5R

10V

0.1UF

C17

1 2

X5R

10V

0.1UF

C20

1 2

X5R

10V

0.1UF

C19

1 2

X5R

10V

0.1UF

C22

1 2

X5R

10V

0.1UF

C21

1 2

X5R

10V

0.1UF

C24

1 2

X5R

10V

0.1UF

C23

1 2

X5R

10V

0.1UF

C26

1 2

X5R

10V

0.1UF

C25

1 2

X5R

10V

0.1UF

C28

1 2

X5R

10V

0.1UF

C27

PCIE_TX0_C_N

PCIE_TX1_C_P

PCIE_TX2_C_P

PCIE_TX2_C_N

PCIE_TX3_C_N

PCIE_TX4_C_P

PCIE_TX4_C_N

PCIE_TX5_C_P

PCIE_TX5_C_N

PCIE_TX7_C_P

NC

NC

NC

NC

PCIE_PRSNT_X821

PCIE_PRSNT_X421

NC

21 PCIE_PRSNT_X1

NC

NC

NC

NC

NC

NC

NC

21PCIE_PRSNT_B

PCIE_RX7_N10

NC

NC

NC

NC

NC

NC

Page 22: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC3V3

VCC3V3

VCC3V3

VCC3V3 VCC3V3

VCC3V3

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

NCLK

CLK

GND

VDD

OE2

OE0

OE1

OE3 NQ3

Q3

NQ2

Q2

NQ1

Q1

NQ0

Q0

PLL_SEL

NC1

NC2

NC3

MR

BW_SEL

F_SEL1

VDDA

VDD

F_SEL0

NC6

VDDO

Q

NQ

NC5

NC4

GND

NCLK

CLK

OE

NCLK

CLK

GND

VDD

OE2

OE0

OE1

OE3 NQ3

Q3

NQ2

Q2

NQ1

Q1

NQ0

Q0

NCLK

CLK

GND

VDD

OE2

OE0

OE1

OE3 NQ3

Q3

NQ2

Q2

NQ1

Q1

NQ0

Q0

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

PCIe / MGT Clocking

BF48

9-24-2009_11:18

22

04

SCHEM, ROHS COMPLIANT,

PCIE / MGT CLOCKING

D

16

15

14

13

12

11

10

98

2

1

3

4

5

6

7

ICS854104

U83

7

6

5

4

3

1

2

8 9

10

11

12

13

14

15

16

U84

ICS854104

2

1C365

0.1UF

10V

X5R

2

1C29

0.1UF

10V

X5R

2

1

5%

1/16W

4.7K

R33

1

2

R366

100

1/16W

5%

2

1

1%

1/16W

DNP

R347

1

2

R37

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R30

7

6

5

4

3

2

1

9

8

11

12

13

14

16

17

18

19

20

15

10

U9

ICS874001

7

6

5

4

3

1

2

8 9

10

11

12

13

14

15

16

U14

ICS854104

PCIE_250M_MGT1_C_N

PCIE_250M_MGT1_C_PPCIE_250M_MGT1_P10

PCIE_250M_MGT1_N10

PCIE_100M_MGT0_P 10

PCIE_100M_MGT0_N 10PCIE_100M_MGT0_C_N

PCIE_100M_MGT0_C_P

1 2

X5R

10V

0.1UF

C379

1 2

X5R

10V

0.1UF

C378

21 PCIE_CLK_QO_P

21 PCIE_CLK_QO_N

18 FMC_HPC_CLK2_M2C_P

18 FMC_HPC_CLK2_M2C_N

10FMC_HPC_CLK2_M2C_MGT_N

10FMC_HPC_CLK2_M2C_MGT_P

7FMC_HPC_CLK2_M2C_IO_N

7FMC_HPC_CLK2_M2C_IO_P

18 FMC_HPC_CLK3_M2C_N

18 FMC_HPC_CLK3_M2C_P

FMC_HPC_CLK3_M2C_MGT_N 10

FMC_HPC_CLK3_M2C_MGT_P 10

FMC_HPC_CLK3_M2C_IO_N 7

FMC_HPC_CLK3_M2C_IO_P 7

NC

NC

NC

1

2

R127

DNP

1/16W

1%

NC

PCIE_100M_MGT1_N22

22 PCIE_100M_MGT1_P

1

2

R38

4.7K

1/16W

5%

1

2 X7R

16V

0.01UF

C156

1

2

0805

6.3V

X5R

10UF

C231

2

1

5%

1/16W

4.7K

R36

2

1

5%

1/16W

4.7K

R40

1

2

R39

4.7K

1/16W

5%

1

2

R140

10

1/16W

5%

2

1

5%

1/16W

4.7K

R34

NC

PCIE_100M_MGT1_N 22

PCIE_100M_MGT1_P 22

NC

NC

NC

NC

NC

NC

NC

NC

2

1 C157

0.01UF

16V

X7R

2

1

1%

1/16W

DNP

R128

1

2

R129

DNP

1/16W

1%

2

1

1%

1/16W

DNP

R130

NC

NC

1

2

X5R

10V

0.1UF

C364

1

2

R343

4.7K

1/16W

5%

NC

2

1

5%

1/16W

4.7K

R342

NC

NC

NC

2

1

5%

1/16W

4.7K

R345

NC

1

2

R344

4.7K

1/16W

5%

NC

NC

NC

NC

1 2

X5R

10V

0.1UF

C381

1 2

X5R

10V

0.1UF

C380

Page 23: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC2V5VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC2V5

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

21_GND

22_GND

23_GND

24_GND

25_GND

26_GND

27_GND

28_GND

29_GND

30_GND

TDN_19

TDP_18

VCCT_16

VCCR_15

RDP_13

RDN_12

LOS_8

RATE_SELECT_7

MOD_DEF0_6

MOD_DEF1_5

MOD_DEF2_4

TX_DISABLE

TX_FAULT_2

31_GND

VEET_20

VEET_17

VEER_14

VEER_10

VEER_11

VEER_9

VEET_1

3

Silkscreen:

"SFP OK"

"SFP EN"

Silkscreen:

"RT_SEL"

"LOW BW"

"FULL BW"1

Silkscreen:

SFP_LOS

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

SFP MODULE

SFP Cage

SFP Cage

04

D

BF23 48

9-24-2009_11:18

21

22

23

24

25

26

27

28

29

30

19

18

16 13

12

8

7

6

5

4

3

2

31

20

17

14

10

11

9

1

15

P4

SFP_CONN_CASE

SFP_TX_FAULT

7IIC_SCL_SFP

7IIC_SDA_SFP

1

2R360

4.75K

1%

2

1

1%

4.75K

R359

1

J53

23

1

NDS331N

Q23

1

2

X5R

10V

0.1UF

C373

1 2 3 4

5678

CP17

0.1UF

10V

X5R

21

FERRITE-220

F1033

1 2

F1032

FERRITE-220

1 2 3

J54

2 1

J65

1

32

Q22

NDS331N

2

1 C372

0.1UF

10V

X5R

2

1

X5R

10V

10UF

C377

2

1

X5R

10V

C371

0.1UF

2

1C376

10UF

10V

X5R

1

3 2

Q21

NDS331N

1

J52

1

J51

SFP_TX_DISABLE_FPGA 9

SFP_LOS

4

SFP_MOD_DEF1

SFP_RX_N 10

SFP_TX_N 10

SFP_TX_P 10

SFP_RX_P 10

SFP_MOD_DETECT

SFP_VCCR

SFP_VCCT

SFP_RT_SEL

SFP_TX_DISABLE

SFP_MOD_DEF2

1

2R362

4.75K

1%

2

1

1%

4.75K

R361

2

1

1%

4.75K

R364

1

2R363

4.75K

1%

Page 24: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCCINT

VCC2V5

VCC2V5

VCC2V5

VCC2V5

VCCINT

VCC2V5

VCCINT

VCC2V5

VCC2V5

VCC2V5

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCINT

TD1_P

TD0_N

TD1_N

TD2_P

TD2_N

TD3_N

TD3_P

VCC

TD0_P

GND

SH2

SH1

10/100/1000

MAGNETICS

RJ45 AND

VSS_127

VDDO_122

DVDD_117

VSS_106

AVDD_104

DVDD_96

VDDOH_97

DVDD_90

DVDD_85

DVDD_78

VDDOX_71

AVDD_64

AVDD_59

AVDD_52

VSS_65

VSS_9

CONFIG1

CONFIG3

CONFIG4

CONFIG5

CONFIG6

CRS

HSDAC_N

LED_DPLX

LED_LINK10

LED_LINK100

LED_LINK1000

LED_RX

LED_TX

MDC

MDI1_N

MDI2_N

MDI3_N

MDIO

RXD1

RXD2

RXD3

RXD4

RXD5

RXD6

RXER

SIN_P

SCLK_P

SCLK_N

TDI

TDO

TMS

TRST_B

TXD0

TXD1

TXD2

TXD3

TXD4

TXD5

TXD7

TXER

SOUT_N

SOUT_P

TCK

RXCLK

RXD0

RXDV

TXCLK

VSS_43

AVDD_49

VDDOX_34

GTXCLK

TXEN

MDI0_P

RSET

RESET_B

COMA

INT_B

CLK125

TXD6

RXD7

COL

SIN_N

CONFIG0

CONFIG2

DVDD_118

VDDOH_73

AVDD_44

DVDD_23

DVDD_27

DVDD_17

DVDD_12

DVDD_6

DVDD_2

VDDO_5

VSS_119

VSS_116

VSS_111

VSS_108

VSS_103

VSS_102

VSS_101

VSS_93

VSS_84

VSS_83

VSS_66

VSS_63

VSS_60

VSS_58

VSS_1

VSS_15

VSS_21

VSS_22

VSS_40

VSS_38

VSS_45

VSS_48

VSS_51

VSS_55

VDDO_30

VDDO_11

SEL_OSC

XTAL1

XTAL2

VSSC_74

VSS_94

MDI0_N

MDI1_P

MDI2_P

MDI3_P

HSDAC_P

VDDOH_89

NC_50

VCC2V5

LED_GRN_SMALL_DUAL_STACK

BOT

TOP

LED_GRN_SMALL_DUAL_STACK

BOT

TOP

LED_GRN_SMALL_DUAL_STACK

BOT

TOP

VCC2V5

"RX"

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

111

111

111

PHYADR[1]

PHYADR[4]

PHYADR[2]

ENA_PAUSE

ANEG[0]

ANEG[3]

ENA_XC

PHYADR[3]

ANEG[2] ANEG[1]

DIS_125

DIS_FC DIS_SLEEP

SEL_BDT INT_POL 75/50 OHM

111

010

advertise the PAUSE bit

PHYADR[0]

Bit[0]Pin Bit[1]

VCC2V5

GND

101

100

011

010

001

000

CFG0

CFG1

CFG2

CFG3

CFG4

CFG5

CFG6

HWCFG_MD[0]

HWCFG_MD[3]

HWCFG_MD[1]HWCFG_MD[2]

125 CLK option disabled.

Auto crossover enabled.

all caps; prefer slave.

Auto-Neg en, advertise

GMII to Cu mode.

Fiber/copper auto-

detect diasabled.

Sleep mode disabled.

MDC/MDIO selected.

Active LOW interrupt

50Ohm SERDES option.

Constant Mapping

Pin to

[2:0]

Bit

111

110

Pin

LED_LINK10

LED_LINK100

LED_LINK1000

LED_DUPLEX

LED_RX

LED_TX

and are all bidirectional pins.

The PHY MDIP Pins below are

10/100/1000 PHY

ML605 EVALUATION PLATFORM

Media Dependent Interface Pins (MDIP),

10/100/1000 PHY

000

111 PHYAddr "00111". Don't

"1000"

"TX"

"10"

"DUP"

LED Silkscreen

"100"

Bit[2]

J66, J67 pins 1-2: GMII/MII to Cu

J66, J67 pins 2-3: SGMII to Cu, no clk

J66 pins 1-2, J68 ON: RGMII, modified MII in Cu

1

2

0805

6.3V

X5R

10UF

C235

1

2

0805

6.3V

X5R

10UF

C232

BF

D

04

24 48

9-24-2009_11:19

NC

NC

PHY_LED_TX_R

PHY_LED_RX_R

PHY_LED_LINK10_R

PHY_LED_LINK100_R

24 PHY_LED_LINK10

24PHY_LED_LINK10

24PHY_LED_LINK1000

24PHY_LED_DUPLEX

24PHY_CONFIG4

24PHY_CONFIG4

24 PHY_CONFIG5

PHY_CONFIG5 24

24PHY_CONFIG0

2

1

H-1X2

J68

3

2

1

H-1X3

J67

43

1 2

DS34

21

3 4

DS33

43

1 2

DS35

XTAL1_25MHZ_ENET 24

PHY_LED_TX 24

24PHY_LED_RX

PHY_LED_RX

PHY_LED_LINK100 24

XTAL2_25MHZ_ENET 24

XTAL1_25MHZ_ENET 24

PHY_LED_LINK100024

PHY_LED_RX24

PHY_LED_LINK10024

PHY_LED_TX24

PHY_LED_LINK1024

PHY_LED_DUPLEX24

SGMII_RX_P 10

SGMII_RX_N 10

SGMII_TX_N 10

SGMII_TX_P 10

2

1

FERRITE-220

F5

24SGMII_RX_C_N

24SGMII_RX_C_P

24SGMII_TX_C_N

24SGMII_TX_C_P

9 PHY_TXD7

9 PHY_TXD6

PHY_TXD59

9 PHY_TXD4

9 PHY_TXD3

9 PHY_TXD2

9 PHY_TXD1

9 PHY_TXD0

9 PHY_TXCTL_TXEN

9 PHY_TXCLK

9 PHY_TXER

9 PHY_TXC_GTXCLK

9 PHY_RXD7

9 PHY_RXD6

9 PHY_RXD5

9 PHY_RXD4

9 PHY_RXD3

9 PHY_RXD2

9 PHY_RXD1

9 PHY_RXD0

PHY_RXER9

9 PHY_RXCTL_RXDV

PHY_RXCLK9

PHY_COL9

PHY_CRS9

PHY_RSET

PHY_COMA

PHY_INT9

9 PHY_MDC

9 PHY_MDIO

3 2

4 1

X2

25.00MHZ

50PPM

127

122

117

106

104

96

97

90

85

78

71

64

59

52

65

9

87

82

81

80

79

115

54

95

100

99

98

92

91

35

47

57

62

33

128

126

125

124

123

121

8

113

110

109

67

72

69

68

18

19

20

24

25

26

29

13

105

107

70

7

3

4

10

43

49

34

14

16

41

39

36

37

32

31

28

120

114

112

88

86

118

73

44

23

27

17

12

6

2

5

119

116

111

108

103

102

101

93

84

83

66

63

60

58

1

15

21

22

40

38

45

48

51

55

30

11

77

76

75

50

74

94

42

46

56

61

53

89

U80

M88E1111

1

2

0805

6.3V

X5R

10UF

C233

3

2

6

4

5

8

7

9

1

10 SH1

SH2

P2

RJ45

21

FERRITE-220

F4

1 2 3 4

5678

CP15

0.01UF

16V

X7R

8 7 6 5

4321

X7R

16V

0.01UF

CP16

8 7 6 5

4321 X5R

10V

0.1UF

CP14

1 2 3 4

5678

CP13

0.1UF

10V

X5R

76

5%

4.7K

RP5

1

2

R42

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R41

1

2

R336

4.99K1%

10

6

5%

4.7K

RP5

9 PHY_RESET

NCNC

XTAL2_25MHZ_ENET24

PHY_CONFIG024

2

1

5%0R304

NC

2

1 C332

22PF

50V

NPO

1

2

NPO

50V

22PF

C333

NC

PHY_AVDD0

PHY_AVDD0

PHY_AVDD0

PHY_AVDD0

MDIP0_CAP

68

RP5

4.7K

5%

45

5%47

RP3

36

RP3

475%

27

5%47

RP3

18

RP3

475%

96

5%

4.7K

RP5

45

RP2

475%

36

5%47

RP2

27

RP2

475%

18

5%47

RP2

15

RP5

4.7K

5%

41

5%

4.7K

RP5

13

RP5

4.7K

5%

21

5%

4.7K

RP5

NC

MDIP3_CAP MDIP1_CAPMDIP2_CAP

PHY_MDIN0_N

PHY_MDIN1_N

2

1 C159

0.01UF

16V

X7R

1

2

X7R

50V

1000PF

C2692

1 C267

1000PF

50V

X7R

1

2

X7R

50V

1000PF

C268

NC

1

2 X7R

16V

0.01UF

C160

PHY_MDIP0_P

PHY_MDIP1_P

PHY_MDIP2_P

1

2 X7R

16V

0.01UF

C158

2

1 C161

0.01UF

16V

X7R

NC

NC

NC

NC

2

1 C270

1000PF

50V

X7R

2

1 C271

1000PF

50V

X7R

PHY_MDIN3_N

PHY_MDIP3_P

PHY_MDIN2_N

NC

PHY_AVDD0

1 2

R1

1M

1/8W

5%

1

2

0805

6.3V

X5R

10UF

C234

12

X7R

16V

0.01UF

C165

2 1C164

0.01UF

16V

X7R

12

X7R

16V

0.01UF

C163

2 1C162

0.01UF

16V

X7R

SGMII_RX_C_N24

SGMII_TX_C_N24

SGMII_TX_C_P24

SGMII_RX_C_P24

1

2

R131

DNP

1/16W

1%

215%1/16W

150 R389

215%1/16W

150 R388

215%1/16W

150 R387

1 2

R386150

1/16W 5%

1 2

R385150

1/16W 5%

1 2

R384150

1/16W 5%

PHY_LED_LINK1000_R

PHY_LED_DUPLEX_R

1

2

3

J66

H-1X3

24PHY_LED_DUPLEX

24PHY_LED_LINK1000

NC

NC

Page 25: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC2V5

VCC2V5VCC1V8

VCC2V5

VCC2V5

Y0

A

GND

S

Y1

VCC

VCC2V5

VCC2V5

VCC2V5

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

K

A00

A01

VDDQ

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

NC_A23

VPP

DQ00

DQ01

DQ02

DQ03

DQ04

DQ05

DQ06

DQ07

DQ08

DQ09

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

E

G

RP

WP

W

L

READY_WAIT

VSSQ

NC

NC

NC

NC

NC

NC

NC

NC

NC

VSS

VSS

VDD

VDD

XCF128X-FTG64C

SIT8102

GND OUT

OE VDD

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

ML605

Platform Flash 128 Mb, Config DIPs

Platform Flash 128 Mb, Config DIPs

2 3

1 4

X4

47MHZ

BF

04

3-17-2010_8:28

4825

D

2

1

5%

1/16W

510

R63

1

2

R62

510

1/16W

5%

1

2

R57

510

1/16W

5%

2

1

5%

1/16W

510

R52

1

2

R51

510

1/16W

5%

1 2

R214

33

1/16W

5%

2

1

1%

1/16W

100

R409

1

2

R408

100

1/16W

1%

CCLK_EXTERNAL25

4PLATFLASH_L_B

B6

C6

D5

D6

E6

E8

F6

F7

H2

F1

A1

B1

A6

H3

G4

C1

D1

D2

A2

C2

A3

B3

C3

D3

C4

A5

B5

C5

D7

D8

A7

B7

C7

C8

A8

G1

H8

A4

F2

E2

G3

E4

E5

G5

G6

H7

E1

E3

F3

F4

F5

H5

G7

E7

B4

F8

D4

G2

G8

H1

B8

B2

H6

H4

U27

XCF128X-FTG64C

2

1 C393

0.1UF

10V

X5R

1

2

X5R

10V

0.1UF

C392

2

1 C391

0.1UF

10V

X5R

1

2

X5R

10V

0.1UF

C31

1

2

R49

4.7K

1/16W

5%

SYSACE_CFGMODEPIN13

SYSACE_CFGADDR113

SYSACE_CFGADDR013

4,26FPGA_FOE_B

2

1

5%

1/16W

4.7K

R58

1

2

R43

4.7K

1/16W

5%

5

6

7

8

4

3

2

1

S1

SDMX-4-X

1

2

3

4

5

6

11

12

10

9

8

7

S2

SDMX-6-X

4,26 FLASH_A23

2

1

5%

1/16W

4.7K

R56

25 CCLK_EXTERNAL

P30_CS_SEL9,25

2 FPGA_M0

FPGA_M12

2 FPGA_M2

NC

1

2

R55

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R50

4 FPGA_FCS_B FLASH_CE_B 26

FPGA_FWE_B 4,26

FLASH_A54,26

9,25 P30_CS_SEL PLATFLASH_FCS_B256

3

2

1

4

5

U10

SN74LVC1G18

2,13,31FPGA_INIT_B

1

2

R44

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R45

FLASH_D15 4,26

FLASH_D14 4,26

FLASH_D10 4,26

FLASH_D8 4,26

FLASH_D9 4,26

4,26FLASH_D11

FLASH_D12 4,26

FLASH_D6 4,26

4,26FLASH_D5

FLASH_D3 4,26

FLASH_D1 4,26

NC

NC

NC

NC

NC

NC

NC

NC

NC

FLASH_A224,26

4,26 FLASH_A21

FLASH_A144,26

4,26 FLASH_A15

FLASH_A164,26

4,26 FLASH_A17

FLASH_A184,26

4,26 FLASH_A19

FLASH_A74,26

4,26 FLASH_A8

FLASH_A94,26

4,26 FLASH_A10

FLASH_A114,26

4,26 FLASH_A12

4,26 FLASH_A13

FLASH_A64,26

4,26 FLASH_A4

FLASH_A34,26

4,26 FLASH_A2

FLASH_A14,26

4,26 FLASH_A0

FLASH_A204,26

4,26FLASH_D0

FLASH_D2 4,26

FLASH_D4 4,26

FLASH_D7 4,26

4,26FLASH_D13

1

2

R47

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R48

1

2

R53

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R54

1

2

R59

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R60

1

2

R61

4.7K

1/16W

5%

SYSACE_CFGADDR213

2,13FPGA_PROG_B

1

2

X5R

10V

0.1UF

C394

2

1 C30

0.1UF

10V

X5R

FPGA_CCLK 2,25FPGA_CCLK_R

FPGA_CCLK 2,25

1

2

1/16W

5%

510

R64

1

2

5%

510

R65

1/16W

2

1

5%

1/16W

4.7K

R46

PLATFLASH_FCS_B 25

Page 26: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC1V8

VCC2V5

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC2V5

VCC2V5

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

VCC0

VCC1

VPP

VCCQ

DQ0

DQ1

DQ2

DQ3

DQ4

DQ6

DQ7

DQ5

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

WE

WP

ADV

RST

OE

CE

WAIT

CLK

RFU

VSS0

VSS1

VSS2

A1

A2

A3

A4

A5

A6

A7

A9

A8

RESET_N

GND

MR_N

VDD

SENSE

CT

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

ML605

BPI FLASH

BPI Flash

<Cap Value in nF> = (((<DELAY in S>) - (0.5*0.001)) * 175)

FLASH_WP_B

D

04

9-17-2009_15:42

4826 BF

1

2

R68

DNP

1/16W

1%

4,25 FPGA_FWE_B

1

2

C34

0.1UF

10V

X5R

2

1C314

DNP

10V

X5R

4

2

3

1

5

6

U7

TPS3808G25DBVT

7

6

5

4

3

2

1

55

18

17

16

11

10

9

26

13

33

43

38

34

36

39

41

47

51

53

49

35

37

40

42

48

50

52

54

14

15

46

44

32

30

56

45

27

12

28

31

29

25

24

23

22

21

20

8

19

U4

JS28F256P30

FLASH_WAIT3

FLASH_CE_B25

FLASH_CLK

4,25 FPGA_FOE_B

FLASH_A23 4,25

FLASH_A22 4,25

FLASH_A21 4,25

FLASH_A17 4,25

4,25FLASH_A18

FLASH_A19 4,25

4,25FLASH_A16

FLASH_A20 4,25

1

2

R95

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R91

1

2

R90

4.7K

1/16W

5%

1

2

R75

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R89

2

1

5%

1/16W

4.7K

R71

FLASH_D10_R

FLASH_D7_R

FLASH_D3_R

FLASH_D2_R

FLASH_D1_R

FLASH_D0_R

1 2

R215100 1/16W1%

1

2

R70

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R69

2

1

5%

1/16W

4.7K

R671

2

R66

4.7K

1/16W

5%

1

2

C33

0.1UF10V

X5R

1

2

C36

0.1UF

10V

X5R

2

1

X5R

10V0.1UF

C35

NC

2

1

X5R

10V

0.1UF

C32

2

1 C363

10UF

25V

X5R

FLASH_ADV_B

26 FLASH_RST_B

21

1% 1/16W100 R216

1 2

R217100 1/16W1%

21

1% 1/16W100 R218

1 2

R222100 1/16W1%211% 1/16W100 R221

1 2

R220100 1/16W1%21

1% 1/16W100 R219

21

1% 1/16W100 R226

1 2

R225100 1/16W1%21

1% 1/16W100 R224

1 2

R223100 1/16W1%

1 2

R230100 1/16W1%21

1% 1/16W100 R229

1 2

R228100 1/16W1%21

1% 1/16W100 R227

FLASH_D4_R

FLASH_D5_R

FLASH_D6_R

FLASH_D8_R

FLASH_D9_R

FLASH_D11_R

FLASH_D12_R

FLASH_D13_R

FLASH_D14_R

FLASH_D15_RFLASH_D154,25

4,25 FLASH_D14

FLASH_D134,25

4,25 FLASH_D12

4,25 FLASH_D11

FLASH_D104,25

4,25 FLASH_D9

FLASH_D84,25

FLASH_D74,25

4,25 FLASH_D6

FLASH_D54,25

4,25 FLASH_D4

4,25 FLASH_D3

FLASH_D24,25

FLASH_D04,25

NC

26 FLASH_RST_B

FLASH_D14,25

1

2

R87

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R86

1

2

R85

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R84

1

2

R83

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R82

1

2

R81

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R80

2

1

5%

1/16W

4.7K

R79

1

2

R78

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R77

1

2

R76

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R74

1

2

R73

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R72

FLASH_A15 4,25

FLASH_A14 4,25

FLASH_A13 4,25

FLASH_A12 4,25

FLASH_A11 4,25

FLASH_A10 4,25

FLASH_A9 4,25

FLASH_A8 4,25

FLASH_A7 4,25

FLASH_A6 4,25

FLASH_A5 4,25

FLASH_A4 4,25

FLASH_A3 4,25

FLASH_A2 4,25

FLASH_A0 4,25

FLASH_A1 4,25

1

2

R94

4.7K

1/16W

5%

2

1

5%

1/16W

4.7K

R93

1

2

R92

4.7K

1/16W

5%

1

2

R88

4.7K

1/16W

5%

Page 27: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC3V3

VCC3V3

VCC5

VCC3V3

VCC3V3

VCC3V3

SCL

SDA

A0

A1

A2

WP

VCC

GND

EN OUT2

IN

GND

NC1

FLG

NC2

OUT1

VCC3V3

VCC3V3

VCC3V3

VCC3V3

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND1_51

GPIO19_A0_CS0_52

GPIO18_A2_RTS__53

GPIO17_A1_RXD__54

GPIO16_A0_TXD_PWM0_55

GPIO15_D15_SSI_N_56

GPIO14_D14_57

GPIO13_D13_58

GPIO10_D10_SCK_61

RD_N_62

VCC0_63

WR_N_64

GPIO9_D9_nSSI_65

GPIO8_D8_MISO_66

D15_CTS_67

D14_RTS_68

D13_RXD_69

GND2_75

D8_MISO_74

D9_nSSI_73

D7_76

D6_77

D5_78

D4_79

D3_80

D2_81

D1_82

D0_83

RESET_N_85

GPIO6_D6_87

GPIO7_D7_86

VCC2_88

GPIO5_D5_89

GPIO4_D4_90

GPIO3_D3_91

GPIO2_D2_92

GPIO0_D0_94

GPIO1_D1_93

A17_95

A18_96

BEH_N_98

A16_97

BEL_N_A0_99

GND3_100

1_A1

2_A2

3_A3

4_DM2B

5_DP2B

6_AGND

7_A4

8_A5

9_DM2A

10_DP2A

11_OTGVBUS

12_CSWITCHB

13_CSWITCHA

14_VSWITCH

15_BOOSTGND

16_BOOSTVCC

17_A6

18_DM1B

19_DP1B

20_A7

21_AVCC

23_DP1A

24_A8

25_A9

26_GND0

27_A10

28_XTALOUT

29_XTALIN

30_A11

31_A12

32_A13

33_A14

34_MEMSEL_N

35_ROMSEL_N

36_RAMSEL_N

37_VCC1

38_A15

39_GPIO31_SCK

40_GPIO30_SDA

41_GPIO29_OTGID

42_GPIO28_TX

43_GPIO27_RX

44_GPIO26_CTS_PWM3

45_GPIO25_IRQ1

46_GPIO24_INT_IORDY_IRQ0

47_GPIO23_RD_N_IOR

48_GPIO22_WR_N_IOW

49_GPIO21_CS_N

50_GPIO20_A1_CS1

GPIO12_D12_59

GPIO11_D11_MOSI_60

D11_MOSI_71

D12_TXD_70

D10_SCK_72

RSVD_84

22_DM1A

(DIE UP)

CY7C67300-100AI

NC2

NC1

VCC

D_N

D_P

GNDSH1

SH2

SH3

SH4

GND

SHLD4

VBUS

D_N

D_P

SHLD1

SHLD2

SHLD3

ID

USB_MINI_B

HDR1x5

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

Silkscreen:

Bypass cap for USB chip

"USB Host"

USB Controller

EEPROM larger than 16KB

SDA/SCL lines swapped for an

"Abort Boot"

USB Host Power

Silkscreen:

"USB Peripheral 1"

USB Controller

ML605

BF

04

9-17-2009_15:42

27 48

D

NC

USB_HOST_VCC

1

2

3

4

5

J36

DNP

5

9

1

2

3

678

4

J20

SH4

SH3

1

2

3

4

SH1

SH2

J5

2

1 C43

0.1UF

10V

X5R1

3

4

2

X1

12_000MHZ

30PPM

2

1 1%4.

75KR18

6

51

52

53

54

55

56

57

58

61

62

63

64

65

66

67

68

69

75

74

73

76

77

78

79

80

81

82

83

85

87

86

88

89

90

91

92

94

93

95

96

98

97

99

100

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

59

60

71

70

72

84

22

U81

CYP_USB_HOST

USB_A15

12

J39

1

2

NPO

50V

22PF

C335

2

1 C334

22PF

50V

NPO

USB_D0

32

USB_D1

32

USB_D2

32

USB_D3

32

USB_D5

32

USB_D4

32

USB_D6

32

USB_D7

32

USB_RESET_B

32

USB_D11 32

USB_GPIO25

27

USB_RD_B

32

USB_GPIO29

27

USB_GPIO26

27

USB_INT

32

USB_A1

32

NC

NC

USB_D8 32

USB_D9 32

USB_D10 32

USB_D12 32

USB_D13 32

USB_D15 32

USB_D14 32

USB_A0 32

USB_WR_B

32

USB_CS_B

32

1 2

FERRITE-220

F7

USB_HOST1_D-

USB_HOST1_D+

USB_HOST1_GND

USB_HOST1_D+

USB_HOST1_D-

USB_HOST1_VCC

2

1

TANT

10V

150UF

C255

2

1 C42

0.1UF

10V

X5R

NC

NC

NC

NC

NC

NC

USB_GPIO25 27

USB_GPIO2627

USB_GPIO2927

NC

NC

2

1 1%4.

75KR18

8

NC

1

2

R18

7

4.75

K1%

1

2 X5R

10V

0.1UF

C41

1 8

7

3

4

2

5

6

U16

MIC2025

6

5

1

2

3

7

8

4

U5

M24128-BWDW6TP

IIC_SDA_USB

1

2

X5R

10V

0.1UF

C44

1

2

R20

4

49.9

K1%

1

2

R20

349

.9K

1%

21

1%20.5K

R141

2

1 C37

0.1UF

10V

X5R

1

2

R18

5

4.75

K1%

1

2

X5R

10V

0.1UF

C38

2

1 C39

0.1UF

10V

X5R

1

2

X5R

10V

0.1UF

C40

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

1 2

F6

FERRITE-220

USB_PERI1_VCC

USB_PERI1_D+

USB_PERI1_D-

NC

NC

NC

USB_HOST1_VCC

USB_HOST1_GND

NC

NC

IIC_SCL_USB

NC

NC

NC

Page 28: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC2V5

VCC5

VCC5

VCC5

VCC5

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

GND_VIDEO

GND_VIDEO

GND_VIDEO

GND_VIDEO

GND_VIDEO

GND_VIDEO

VCC5

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

SH_GND1

SH_GND2

AGND1

BLUE

GREEN

RED

DATA0_N

DATA0_P

DATA5_N

DATA5_P

CLK_P

CLK_N

DATA3_N

DATA1_P

DATA1_N

DDC_DATA

DDC_CLK

DATA4_P

DATA4_N

DATA2_P

DATA2_N

VS

SHIELD_CLK

SHIELD_0/5

SHIELD_1/3

SHIELD_2/4

HS

DATA3_P

GND0

VCC5

HPDET

AGND0

DVI_CONN

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

To Video Codec

DVI Bus

To IIC

To Video Codec

To Video Codec

DVI VIDEO CONNECTOR

SCHEM, ROHS COMPLIANT

4828

DVI VIDEO CONNECTOR

04

9-17-2009_15:42

BF

D

IIC_SDA_DVI_F

2

1 C45

0.1UF

10V

X5R

25

26

C6

C3

C2

C1

17

18

20

21

23

24

12

10

9

7

6

5

4

2

1

8

22

19

11

3

C4

13

15

14

16

C5

P3

DVI_CONN

IIC_SCL_DVI4,29

21

3

200MA 40V

BAS40-04

D7

3

12

D6

BAS40-04

40V200MA

21

3

200MA 40V

BAS40-04

D5

21

3

200MA 40V

BAS40-04

D3

3

12

D2

BAS40-04

40V200MA

21

3

200MA 40V

BAS40-04

D1

2

1

1%75

.0

R20

5

DVI_VSYNC29

DVI_CONN_HSYNC

DVI_CONN_HPDET

1 2

F10

FERRITE-220

21

FERRITE-220

F12

DVI_GREEN29

DVI_HSYNC29

DVI_HPDET29

IIC_SDA_DVI4,29

DVI_GRN_TMP

12

R341

1%1.21K

1

2

R153

2.43K1%

2

1

1%2.43K

R152

2

1 C336

22PF

50V

NPO

3

12

D8

BAS40-04

40V200MA

3

12

D4

BAS40-04

40V200MA

2 3

1

NDS331N

Q5

1

32

Q6

NDS331N

21

FERRITE-220

F9

1 2

F8

FERRITE-220

IIC_CLK_DVI_F

1

2

X7R

50V

270PF

C350

2

1 C349

270PF

50V

X7R

21

5%330MA

82NH

L6

1 2

L5

82NH

330MA 5%

1 2

L1

82NH

330MA 5%

21

5%330MA

82NH

L4

21

5%330MA

82NH

L2

1 2

L3

82NH

330MA 5%

DVI_CONN_BLUE

2

1 C346

33PF

50V

NPO

1

2

NPO

50V

33PF

C345

2

1 C344

33PF

50V

NPO

1

2

NPO

50V

22PF

C343

1

2

NPO

50V

22PF

C337

2

1 C338

22PF

50V

NPO

1

2

X5R

10V

0.1UF

C46

1

2

NPO

50V

22PF

C339

2

1 C341

22PF

50V

NPO

1

2

NPO

50V

22PF

C340

2

1 C342

22PF

50V

NPO

DVI_BLUE_TMP

DVI_CONN_RED

DVI_RED_TMP

DVI_CONN_GREEN

NC

DVI_D2_N29

DVI_D2_P29

NC

NC

DVI_D1_N29

DVI_D1_P29

NC

DVI_CLK_N29

DVI_CLK_P29

NC

NC

DVI_D0_P29

DVI_D0_N29

DVI_RED29

DVI_BLUE29

1

2

R20

6

75.0

1%

2

1

1%75

.0

R20

7

DVI_CONN_VSYNC

Page 29: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC2V5

GND_VIDEO

GND_VIDEO

GND_VIDEO

VCC3V3

VCC5

VCC3V3

VCC2V5

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

EN

GND

IN

NR_FB

OUT

NC0

TGND3

DVDD1

DVDD2

DGND2

DGND3

TVDD1

TVDD2

TGND1

TGND2

G B

D10

D11

D1

D2

D3

D4

D5

D6

D7

D8

D9

XCLK_P

DE

H

V

SPD

SPC

GPIO1

GPIO0

AS

TDC0_P R

VSYNC

HSYNC

HPDET

TLC_N

TLC_P

TDC2_P

TDC2_N

TDC1_P

VSWING

NC1

NC5

GND2

GND1

VDD

AGND2

NC3

NC4

NC2

RESET_B

D0

XCLK_N

ISET

TDC0_N

TDC1_N

DVDD3

AVDD

DGND0

VREF

DVDDV

NC6

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

DVI_AS

IIC Address = 0x76

To DVI Connector

Place termination RPs near U37

Near DVI IC

(3.3V)

DVI CODEC

D

BF48

9-17-2009_15:42

29

04

DVI CODEC

SCHEM, ROHS COMPLIANT,

1 2

R231

100 1%

2

1

1%2.43K

R1541

2

R156

2.43K1%

2

1

1%2.43K

R157

1

2

R294

1401%

2

1

1%2.43K

R155

1

2

X5R

10V

0.1UF

C48 1

2

C239

10UF

10V

X5R

21

FERRITE-220

F1009

1 2

F15

FERRITE-220

21

FERRITE-220

F14

2

1

X5R

10V

10UF

C238

2

1 C47

0.1UF

10V

X5R

1

2

X5R

10V

0.1UF

C51

2

1 C52

0.1UF

10V

X5R

1

2

C237

10UF

10V

X5R

1 2

F13

FERRITE-220

21

FERRITE-220

F18

2

1

1%4.75KR189

1

2

R1904.75K1%

1

2

X5R

10V

0.1UF

C54

2

1 C49

0.1UF

10V

X5R

1

2

X5R

10V

0.1UF

C50

16

32

1

12

11

64

23

29

20

26

37

39

51

50

62

61

60

59

58

55

54

53

52

57

2

4

5

14

15

7

8

10

22

38

47

48

931

30

28

27

25

19

36

44

40

34

33

17

42

43

41

13

63

56

35

21

24

49

18

6

3

45

46

U38

CH7301C-TF

2

1 C320

DNP

2

1 C166

0.01UF

16V

X7R

1

2

X5R

10V

1UF

C143

3

2

1

4

5

U15

TPS73633DBVT

DVI_RESET_B32

DVI_GPIO1

4,28IIC_SCL_DVI

4,28IIC_SDA_DVI

1 2

R108

47.5

1/16W

1%

21

1%

1/16W

47.5

R104

1 2

R105

47.5

1/16W

1%

21

1%

1/16W

47.5

R106

1 2

R100

47.5

1/16W

1%

21

1%

1/16W

47.5

R103

1 2

R102

47.5

1/16W

1%

9DVI_D9 21

1%

1/16W

47.5

R101

9DVI_V

9DVI_H

9DVI_DE

9DVI_D0

9DVI_D1

9DVI_D2

9DVI_D3

9DVI_D4

9DVI_D5

DVI_D69

9DVI_D7

DVI_VCCA29

DVI_VDD

DVI_AVDD DVI_VCCA29

DVI_TVDD

DVI_DVDD

DVI_VCCA29

DVI_XCLK_P9

DVI_XCLK_N9

2

1

X5R

10V

10UF

C236

2

1 C53

0.1UF

10V

X5R

NC

NC

DVI_D1_N28

DVI_D0_N28

NC

NC

NC

NC

NC

DVI_D1_P28

DVI_D2_N28

DVI_D2_P28

DVI_CLK_P28

DVI_CLK_N28

DVI_HPDET28

DVI_HSYNC28

DVI_VSYNC28

DVI_RED28

DVI_D0_P28

DVI_BLUE28

DVI_GREEN28

NC

DVI_D109

9DVI_D11

9DVI_D8

1 2

R107

47.5

1/16W

1%

21

1%

1/16W

47.5

R111

1 2

R110

47.5

1/16W

1%

21

1%

1/16W

47.5

R109

21

1%

1/16W

47.5

R112

1 2

R113

47.5

1/16W

1%

21

1%

1/16W

47.5

R114

Page 30: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC2V5

GND1

GND2

GND3

GND4

GND5

GND6

GND7

SIG

GND1

GND2

GND3

GND4

GND5

GND6

GND7

SIG

GND1

GND2

GND3

GND4

GND5

GND6

GND7

SIG

GND1

GND2

GND3

GND4

GND5

GND6

GND7

SIG

VCC2V5

GND1

GND2

GND3

GND4

GND5

GND6

GND7

SIG

GND1

GND2

GND3

GND4

GND5

GND6

GND7

SIG

VCC3V3

GND1

GND2

GND3

GND4

GND5

GND6

GND7

SIG

VCC2V5

GND1

GND2

GND3

GND4

GND5

GND6

GND7

SIG

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND

OE

OUT

VCC

OSC

GND1

GND2

GND3

GND4

GND5

GND6

GND7

SIG

GND1

GND2

GND3

GND4

GND5

GND6

GND7

SIG

VDDA VDD

Q0GND

XTAL_OUT NQ0

OEXTAL_IN

SI500D

NC

GND

VCC

OUT_B

OUT

OE

NC

GND

VCC

OUT_B

OUT

OE

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

125.00 MHz Clock

Ethernet SGMII Clock - 125MHz

ML605

Single Ended User Clock

SMA MGT Connectors

MGT REFCLK

Clocks and MGTs

Clocks and MGTs

USER SMA CLOCK

USER SMA GPIO

Differential System Clock

2

6

5

1

3 4

U11

200MHZ

2

3

6

5

4

1

U89

DNP

BF

3-17-2010_8:28

30 48

04

D

SGMIICLK_QO_C_P

SGMIICLK_QO_C_N

21

NPO

50V

33PF

C347

1 2

F1029

FERRITE-220

1 2

FERRITE-220

F1030

21

5%10R202

2

1

X7R

16V

0.01UF

C167

2

1 C168

0.01UF

16V

X7R

2

1

X5R

10V

10UF

C240

1

2

R132

DNP

1/16W

1%

X3

25.000MHZ

1 8

72

3 6

54

U82

ICS844021I

2

3

4

5

6

7

8

1

J29 32K10K-400E3

2

3

4

5

6

7

8

1

32K10K-400E3J28

1

2 X5R

10V

0.1UF

C64

1

2

R96

4.7K

1/16W

5%

4

1

5

8

X5

110880

1

2 X5R

10V

0.1UF

C395

2

1 C63

0.1UF

10V

X5R

USER_SMA_CLOCK_N4

USER_SMA_GPIO_P2

USER_SMA_GPIO_N2

USER_SMA_CLOCK_P4

SYSCLK_P 4,30

1

8

7

6

5

4

3

232K10K-400E3J30

SYSCLK_N 4,30

4USER_CLOCK

10 SMA_REFCLK_N

10 SMA_REFCLK_P

SMA_RX_C_N

SMA_RX_C_P

21

0.1UF

C57

10V

X5R

1 2

X5R

10V

C58

0.1UF

21

0.1UF

C56

10V

X5R

10 SMA_RX_N

10 SMA_RX_P

SGMIICLK_QO_N 10

SGMIICLK_QO_P 10

VDDA_SGMIICLK

2

3

4

5

6

7

8

1

J27 32K10K-400E3

21

X5R

10V

C55

0.1UF

SGMIICLK_XTAL_OUT

GND_SGMIICLK

GND_SGMIICLK

VDD_SGMIICLK VDDA_SGMIICLK

GND_SGMIICLK

VDD_SGMIICLK

SGMIICLK_XTAL_IN

21C348

33PF

50V

NPO

2

3

4

5

6

7

8

1

32K10K-400E3J26SMA_TX_P10

SMA_TX_N10

SMA_REFCLK_C_N

1

8

7

6

5

4

3

2J31 32K10K-400E3

21

0.1UF

C62

10V

X5R

1 2

X5R

10V

C61

0.1UF

SMA_REFCLK_C_P

NC

2

3

4

5

6

7

8

1

32K10K-400E3J58

1

8

7

6

5

4

3

2J57 32K10K-400E3

1

8

7

6

5

4

3

232K10K-400E3J56

2

3

4

5

6

7

8

1

J55 32K10K-400E3

NC SYSCLK_N 4,30

SYSCLK_P 4,30

Page 31: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC2V5

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC2V5

P2

P1

P3

P4

Pushbutton

P2

P1

P3

P4

Pushbutton

P2

P1

P3

P4

Pushbutton

P2

P1

P3

P4

Pushbutton

P2

P1

P3

P4

Pushbutton

G1

P2

P1

P3

P4

Pushbutton

G2

VCC2V5

NDS336P

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

GPIO LEDs and Buttons

West EastCenter

South

North

LEDs:

0 1 2 3 4 765

GPIOGPIO Buttons, LEDs, Switches,

ML605

GPIO - Buttons, LEDs, Switches

ML605 Power Good

1

23

Q14

D3-25-2010_10:38

4831

04

BF

23

1

NDS331N

Q2

1

2

C382

0.1UF

10V

X5R

8

3

6

5

4

U86

SN74LVC2G08DCU

GPIO_LED_N_R

GPIO_LED_S_R

GPIO_LED_E_R

GPIO_LED_W_R

GPIO_LED_C_R

21

5%

1/16W

4.7K

R402

1 2

R401

4.7K

1/16W

5%

4

3

1

2

SW10

7

2

1

U86

SN74LVC2G08DCU

2

1R241

200

1/16W

5%

21

LED-GRN-SMT

DS2

2

1

3

4

SW9

4

3

1

2

SW8

2

1

3

4

SW7

4

3

1

2

SW6

2

1

3

4

SW5

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

SW1

SDMX-8-X

GPIO_LED_74,31

GPIO_LED_64,31

GPIO_LED_54,31

GPIO_LED_44,31

GPIO_LED_34,31

GPIO_LED_24,31

GPIO_LED_14,31

GPIO_LED_04,31

8

7

6

1

2

3

4

5

J62

H-1X8

4,31 GPIO_LED_7

4,31 GPIO_LED_6

4,31 GPIO_LED_5

4,31 GPIO_LED_4

4,31 GPIO_LED_3

4,31 GPIO_LED_2

4,31 GPIO_LED_1

4,31 GPIO_LED_0

VCC3V3

NC

MGT_TI_PWRGOOD40

TI_PWRGOOD35

FPGA_INIT_B2,13,25

12

LED-RED-SMT

DS31

VCC1V5

VCC1V5

CPU_RESET5

12

DS22

LED-GRN-SMT

2

1R6

27.4

1/16W

1%

VCC1V5

VCC1V5

12

DS21

LED-GRN-SMT

GPIO_LED_C8

GPIO_LED_W8

GPIO_LED_E8

GPIO_LED_N8

GPIO_LED_S8

1

2

1%

1/16W

27.4

R151

2

1%

1/16W

27.4

R13

GPIO_SW_N6

GPIO_SW_S6

GPIO_SW_E6

GPIO_SW_W6

5 GPIO_SW_C

GPIO_DIP_SW16

76

RP7

4.7K

5%

13

5%

4.7KR

P7

21

RP7

4.7K

5%

21

DS18

LED-GRN-SMT

12

LED-GRN-SMT

DS19

12

LED-GRN-SMT

DS17

21

DS16

LED-GRN-SMT

GPIO_DIP_SW86

GPIO_DIP_SW76

GPIO_DIP_SW66

GPIO_DIP_SW56

GPIO_DIP_SW36

GPIO_DIP_SW46

GPIO_DIP_SW26

21

DS20

LED-GRN-SMT

68

5%

4.7KR

P7

96

RP7

4.7K

5%

610

5%

4.7KR

P7

41

RP7

4.7K

5%

15

5%

4.7KR

P7

21

LED-GRN-SMT

DS10

21

LED-GRN-SMT

DS9

12

DS12

LED-GRN-SMT

12

DS11

LED-GRN-SMT

1

2

1%

1/16W

27.4

R41

2

1%

1/16W

27.4

R51

2

1%

1/16W

27.4

R8

2

1R7

27.4

1/16W

1%

2

1R10

27.4

1/16W

1%

1

2

1%

1/16W

27.4

R91

2

1%

1/16W

27.4

R12

2

1R11

27.4

1/16W

1%

2

1R14

27.4

1/16W

1%

2

1R16

27.4

1/16W

1%

1

2

1%

1/16W

27.4

R17

21

LED-GRN-SMT

DS13

21

LED-GRN-SMT

DS14

12

DS15

LED-GRN-SMT

VCC1V5

VCC1V5

VCC1V5

2

1R3

27.4

1/16W

1%

NC

NC

1 2

R403

4.7K

1/16W

5%

21

5%

1/16W

4.7K

R404

1 2

R405

4.7K

1/16W

5%

21

5%

1/16W

4.7K

R406

1

2

R419

330

1/16W

5%

FPGA_DONE2

Page 32: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC2V5

VCC2V5

VCC2V5 VCC3V3

VCC2V5

VCC2V5

VCC2V5

VCC3V3

VCC2V5

VCC3V3VCC2V5

VCC2V5

VCC3V3

VCC3V3VCC3V3

VCC3V3

VCC2V5

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC2V5

VCC2V5 VCC2V5

GND

IOVCC1

IOVCC2

IOVCC3

IOVCC4

IOVCC5

IOVCC6

IOVCC7

IOVCC8

IOVL1

IOVL2

IOVL3

IOVL4

IOVL5

IOVL6

IOVL7

IOVL8

OE

VCCVL

GND

IOVCC1

IOVCC2

IOVCC3

IOVCC4

IOVCC5

IOVCC6

IOVCC7

IOVCC8

IOVL1

IOVL2

IOVL3

IOVL4

IOVL5

IOVL6

IOVL7

IOVL8

OE

VCCVL

GND

IOVCC1

IOVCC2

IOVCC3

IOVCC4

IOVCC5

IOVCC6

IOVCC7

IOVCC8

IOVL1

IOVL2

IOVL3

IOVL4

IOVL5

IOVL6

IOVL7

IOVL8

OE

VCCVL

SCL

SDA

A0

A1

A2

WP

VCC

GND

GND

IOVCC1

IOVCC2

IOVCC3

IOVCC4

IOVCC5

IOVCC6

IOVCC7

IOVCC8

IOVL1

IOVL2

IOVL3

IOVL4

IOVL5

IOVL6

IOVL7

IOVL8

OE

VCCVL

GND

IOVCC1

IOVCC2

IOVCC3

IOVCC4

IOVCC5

IOVCC6

IOVCC7

IOVCC8

IOVL1

IOVL2

IOVL3

IOVL4

IOVL5

IOVL6

IOVL7

IOVL8

OE

VCCVL

VCC5

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

IIC EEPROM

3.3V to 2.5V Level Shifters

Misc - LCD, Level Shifters

ML605

LCD, Level Shifters

IIC Address = 0b1010100

D

04

9-24-2009_11:19

4832 BF

1

2

X5R

6.3V

1UF

C187

1

2

R305

DNP

1/16W

1%

2

1

5%

0R133

1

2

1%

1/16W

DNP

R412

16,17,20DVI_GPIO1_FMC_C2M_PG

IIC_SDA_MAIN15,16,32

IIC_SCL_MAIN15,16,32 21

5%

1/16W0

R413

NC

DVI_GPIO1_FMC_C2M_PG_LS4

9DVI_RESET_B_LS

23

1

NDS331N

Q18

1

3 2

Q15

NDS331N

23

1

NDS331N

Q16

1

3 2

Q17

NDS331N

PMBUS_DATA_LS 435,40 PMBUS_DATA

35,40 PMBUS_ALERT

9FMC_LPC_IIC_SDA_LS

FMC_LPC_IIC_SCL_LS 9

20

12

3

19

6

7

13

15

5

11

9

17

10

8

14

16

4

18

2

1

U32

2

1 C67

0.1UF

10V

X5R

1

2

X5R

10V

0.1UF

C66

2

1 C183

1UF

6.3V

X5R

2

1 C73

0.1UF

10V

X5R

2

1 C74

0.1UF

10V

X5R

1

2

X5R

10V

0.1UF

C75

1

2

18

4

16

14

8

10

17

9

11

5

15

13

7

6

19

3

12

20

U33

2

1 C65

0.1UF

10V

X5R

6

5

1

2

3

7

8

4

U6

M24C08-WDW6TP

20 FMC_LPC_IIC_SCL

2

1 C69

0.1UF

10V

X5R

1

2

X5R

10V

0.1UF

C68

2

1 C184

1UF

6.3V

X5R

2

1 C185

1UF

6.3V

X5R

1

2

X5R

10V

0.1UF

C70

2

1 C71

0.1UF

10V

X5R

2

1 C186

1UF

6.3V

X5R

2

1

X5R

10V

0.1UF

C72

1

2

18

4

16

14

8

10

17

9

11

5

15

13

7

6

19

3

12

20

U31

20

12

3

19

6

7

13

15

5

11

9

17

10

8

14

16

4

18

2

1

U30

1

2

18

4

16

14

8

10

17

9

11

5

15

13

7

6

19

3

12

20

U29

3 FMC_HPC_PG_M2C_LS FMC_HPC_PG_M2C 17

4IIC_SDA_MAIN_LS

IIC_SCL_MAIN_LS 4

IIC_SDA_MAIN15,16,32

15,16,32 IIC_SCL_MAIN

1

3 2

Q19

NDS331N

PMBUS_ALERT_LS 4

PMBUS_CTRL_LS 4

4PMBUS_CLK_LSPMBUS_CLK35,40

35,40 PMBUS_CTRL

LCD_DB733

LCD_RS 33LCD_RS_LS2

LCD_DB6_LS9

LCD_E33

LCD_RW33

LCD_DB433

LCD_DB533

LCD_DB633

LCD_E_LS9

LCD_DB4_LS9

LCD_DB7_LS9

2 USB_D15_LS

2 USB_D7_LS

2 USB_RESET_B_LS

2 USB_A0_LS

27USB_D7

27USB_RESET_B

27USB_A0

27USB_D15

27USB_D14

27USB_D13

27USB_D12

27USB_D112 USB_D11_LS

2 USB_D12_LS

2 USB_D13_LS

2 USB_D14_LS

9 PCIE_PERST_B_LS

21

PCIE_PERST_B

PCIE_WAKE_B_LS4

DVI_RESET_B29

LCD_DB5_LS9

LCD_RW_LS9

2 USB_RD_B_LS

2 USB_WR_B_LS

2 USB_CS_B_LS

2 USB_INT_LS

2 USB_D8_LS 27USB_D8

27USB_D9

27USB_D10

27USB_INT

27USB_A1

27USB_CS_B

27USB_WR_B

27USB_RD_B

2 USB_D10_LS

2 USB_D9_LS

2 USB_A1_LS

2 USB_D2_LS

27USB_D1

27USB_D0

27USB_D2

27USB_D3

NC

27USB_D4

27USB_D5

27USB_D6

NC

2 USB_D0_LS

2 USB_D1_LS

2 USB_D3_LS

2 USB_D4_LS

2 USB_D5_LS

2 USB_D6_LS

23

1

NDS331N

Q20

NC

NCNC NC NC

1

3 2

Q27

NDS331N

23

1

NDS331N

Q26

FMC_LPC_IIC_SDA20

NC NC

1 2

R414 0

1/16W

5%

PCIE_WAKE_B 21

Page 33: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC5

VCC5

VCC2V5

REGIN

CN

R_G

ND

RT

S_O

_B

DT

R_O

_B

DC

D_I

_B

NC

1

NC10

NC

2

NC

3

NC4

GPIO3

GPIO2

GPIO1

GPIO0

NC9

RS

T_B

RX

D_I

TX

D_O

SU

SP

EN

D

SU

SP

EN

D_B

DS

R_I

_B

VB

US

VDD

CT

R_G

ND

CT

S_I

_B

D+

D-

GND1

VIO

RI_I_B

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND

SHLD4

VBUS

D_N

D_P

SHLD1

SHLD2

SHLD3

ID

USB_MINI_B

SSW-107-01-T-D

LCD Standoffs

Silkscreen:

"LCD Contrast"

LCD Header

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

Bridge

USB to RS232

CP2103 USB Self-Powered

(26mA max)

CP2103GM

The VIO voltage must match the appropriate bank IO voltage

USB UART, LCD Header

D

BF48

9-17-2009_15:42

33

04

SCHEM, ROHS COMPLIANT,

USB UART, LCD HEADER

1 2

3 4

5 6

7 8

9 10

11 12

13 14

J41

NC

5

9

1

2

3

678

4

J21

LCD_E32

21

1%6.81K

R158

2

31

R270

0-2K

1/2W

20%

1

2 3

4

X6

SP0503BAHT

225MW

7

29

23

27

28

10

21

13

14

15

16

17

18

19

20

9

24

25

12

11

26

8

6

30

22

3

4

2

5

1

U34

CP2103GM

VCC3V3

1

2 X5R

10V

0.1UF

C76

2

1C188

1UF

6.3V

X5R

1

2

X5R

6.3V

1UF

C189

2

1 C77

0.1UF

10V

X5R

USB_1_DATA_N

NC

2

1

5%

1/16W

4.7K

R97

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

USB_1_VBUS

USB_1_DATA_P

USB_1_TX 4

4USB_1_RX

4USB_1_RTS

4USB_1_CTS

NC

1

J16

1

J15

LCD_RS32

LCD_DB732

LCD_DB532

NC

LCD_DB6 32

LCD_RW 32

NC

NC

NC

LCD_DB4 32

LCD_VEE

NC

NC

NC

Page 34: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC5

VCC5

VCC2V5

IN OUT

GND

REF3012

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

Battery

Rechargeable

System Monitor Header for probing

place 100 ohm resistors and

0.01 cap near FPGA

Default setting:

To Measure VCCINT:

Jumper on 1-2, 3-4

Jumper on 9-11, 10-12

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

Default Setting:

SYSMON HEADER / AVDD VREFP SUPPLY / Battery

C383 and C78 must

be placed close to the FPGA

Jumper on pins 1-2

(Approx 2.1V)

SYSMON HEADER / AVDD VREFP SUPPLY / BATTERY

D

BF48

9-17-2009_15:42

34

04

SCHEM, ROHS COMPLIANT,

1

2

R161

4.75K1%

1

2

R191

4.75K1%

1

2

3

H-1X3

J19

VCC1_SENSE_PVCC1_SENSE_N

2

1

3D9

BAS40-04

40V

200MA

2

1

B1

TEST_MON_AVDD2,34

GND_TESTMON2,34

1 2

3

U23

REF3012AIDBZT

GND_TESTMON 2,34

1

2

X5R

10V

0.1UF

C383

1

2

X5R

10V

0.1UF

C78

2

1 C79

0.1UF

10V

X5R

21

F3

HZ0805E601R-10

2

1 C169

0.01UF

16V

X7RGND_TESTMON2,34

FPGA_DX_N2

FPGA_DX_P2

NC

NC

TEST_MON_AVDD2,3434

ADR_VREFP

1 2

3

5 6

7 8

9 10

4

1211

J35

H-2X6

2TEST_MON_VP0_P

2TEST_MON_VN0_N

1

2

X5R

6.3V

1UF

C191

2

1 C190

1UF

6.3V

X5R

1 2

R232

100

1/16W

1%

21

1%

1/16W

100

R233

1 2

HZ0805E601R-10

F2

34ADR_VREFP

2,34GND_TESTMON

TEST_MON_VREFP2

NC

FPGA_VBATT2

Page 35: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

9240

DGND1

9240

DGND1

9240

DGND1

9240

DGND1

9240

AGND1

9240

AGND1

9240

AGND1

VCC12_P

IN OUT

GNDTAB

GND

SNS_ADJSHDN_B

A4

A6

A

A7

A5

E_B

VEE

GND S2

S1

S0

A3

A0

A1

A2

VCC

VCC12_P

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC5

/RESET

/TRST

ADC_REF

ADDRSEN0ADDRSEN1

AG

ND

1A

GN

D2

AG

ND

3

AUX-IN_AD13AUX-IN_AD14

BPCAP

CS-1ACS-1B

CS-2ACS-2B

CS-3ACS-3B

CS-4ACS-4B

DG

ND

1D

GN

D2

DG

ND

3

DIAG-LED

DPWM-1ADPWM-1B

DPWM-2ADPWM-2B

DPWM-3ADPWM-3B

DPWM-4ADPWM-4B

EAN1

EAN2

EAN3

EAN4

EAP1

EAP2

EAP3

EAP4

FAN-PWMFAN-TACH

FAULT-1AFAULT-1B

FAULT-2AFAULT-2B

FAULT-3AFAULT-3B

FAULT-4AFAULT-4B

PMBUS_ALERT

PMBUS_CLKPMBUS_CTRL

PMBUS_DATA

PWRGOOD

SRE-1ASRE-1B

SRE-2ASRE-2B

SRE-3ASRE-3B

SRE-4ASRE-4B

SYNC-INSYNC-OUT

TCK

TDITDO

TEMP

TMS

TMUX0TMUX1TMUX2

TRCK

V33

AV

33D

V33

DIO

1V

33D

IO2

V33

FB

VIN

VTRACK

9240

AGND1

9240

AGND1

9240

AGND1

9240

AGND1

9240

AGND1

9240

DGND1

0603_SHORT 0603_SHORT

9240

DGND1

9240

AGND1

9240

AGND1

9240

AGND1

5V @ 1.5A

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

VCCxxxx_EAP/N are remote sense

pairs wired back from power plane

PMBus Connector

connections at FPGA

PMBus Address is calculated as follows:

ADDRSENxRPMBusValue

11109876543210Short

Open -

-

Note:

FPGA PMBus Regulator Shutdown(shuts off regulators)

SCHEM, ROHS COMPLIANT

FPGA UCD9240 PMBus Controller

TI UCD9240 Power System

158k115k84.5k63.4k47.5k36.5k

210k

27.4k21.5k16.9k13.0k10.2k

PMBus Address = 12 × Value(ADDRSEN1) + Value(ADDRSEN0)

Example: ADDRSEN1 R=27.4k and ADDRSEN0 R=27.4k

PMBus Address = (12 x 4) + 4 = 52 decimal

Do not use PMBus Addresses 0, 1, 2, 3, 12, 126 or 127

AGND should be a copper island underneaththe 9240 and every associated module

TI_TCK

2

1

J8

1

2

J9

9-24-2009_11:19

4835 BF

D

04

2

1R301

2.0K

1/16W

5%

2

1R299

2.0K

1/16W

5%

2

1R300

2.0K

1/16W

5%

VCC3V3A

1 2

F1111

FERRITE-220

VCC3V3A

TEMP35

1 2Z2

21Z1

TI_V3P3

2

1 C421

0.1UF

16V

X7R1

32

Q12

1

2

X7R

16V

0.1UF

C173

1

2

X5R

10V

0.1UF

C84

1

2

R247

10.0K

1/16W

1%

1

2

X5R

10V

0.1UF

C83

2

1 C82

0.1UF

10V

X5R

2

1

X5R

10V

4.7UF

C351

13

48

1

77

76

61

60

80

72

71

59

75

79

4

78

3

74

2

73

9 34

55

10

21

22

23

24

25

26

27

28

63

65

67

69

62

64

66

68

53

32

15

16

17

18

29

41

42

43

35

19

36

20

49

12

11

51

37

38

52

33

50

31

30

44

46

45

7

47

39

40

54

14

58

57

8

56

70

5

6

U24

UCD9240PFC

2

1 C248

4.7UF

16V

Y5V

21

FERRITE-220

F1112

2

1 C117

10UF

16V

X5R

2

1 C305

0.1UF

16V

X7R

40VCC4B_FLT21

5%

1/16W0

R418

40VCC3B_FLT1 2

R417 0

1/16W

5%

40VCC1B_FLT1 2

R415 0

1/16W

5%

VCC2B_FLT 4021

5%

1/16W0

R416

VCC3A_CS 38

VCC2A_CS 37

VCC1A_CS 36

NC

36VCC1A_FLT

TI_V3P3

1

2

1%

1/16W

27.4K

R174

2

1

1%

1/16W

27.4K

R271

1 2

R160

2.15K

1/16W

1%

1 2

R159

6.81K

1/16W

1%

NC

NC

NC

TEMP3 38

1

2

X5R

10V

0.068UF

C253

1 2

R318

1.00K

1/16W

1%VCC3_EA_N 38

VCC3_EA_P 38

NC

38VCC3A_SRE

NC

VCC3A_PWM 38

9

7

1 2

3

5 6

4

8

10

J3

HDR_BOX_2X5

2

1

1%

1/16W

10.0K

R382

1 2

R379

2.0K

1/16W

5%

32,40 PMBUS_DATA

32,40 PMBUS_ALERT

32,40 PMBUS_CLK

31TI_PWRGOOD

39FAN_TACH

VCC2A_FLT 37

VCC2A_SRE 37

37VCC2A_PWM

32,40 PMBUS_CTRL

2

1 C362

0.47UF

10V

X5R

2

1 C306

0.1UF

16V

X7R

NC

NC

TI_RESET_B

1

2

X5R

10V

0.068UF

C251

1

2

J11

1

2

R98

4.7K

1/16W

5%

TI_V3P3

2

1

J10

21C352

4.7UF

10V

X5R

1

2

R252

10.0K

1/16W

1%

2

1

1%

1/16W

10.0K

R251

21

D14

BZT52C5V1-TP

5.1V

500MW

1 2

R317

1.00K

1/16W

1%

1

2

R335

1.0M

1/16W

5%

1

2

R250

10.0K

1/16W

1%

2

1

1%

1/16W

10.0K

R2491

2

R248

10.0K

1/16W

1%

2

1 C172

0.01UF

16V

X7R

2

1 C81

0.1UF

10V

X5R

1

2

1%

1/16W

10.0K

R246

1

2

1%

1/16W

10.0K

R245

1

2

3

4

J6

DNP

TI_V3P3

21

C80

0.1UF

10V

X5R

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16

U2

CD74HC4051

2

1 C250

0.068UF

10V

X5R

PWR_INH 36,37,38,41,42,43,44

NC

NC

NC

NC

NC

NC NC

TEMP1 36

37TEMP2

35TMUX0

35TMUX1

TMUX2 35

NC

NC

NC

NC

NC

35 TMUX2

TMUX135

35 TMUX0

35 TEMP

VCC1A_SRE 36

39FAN_PWM

VCC2_EA_P 37

VCC1_EA_P 36

37VCC2_EA_N

VCC1_EA_N 36

VCC1A_PWM 36

NC

TRST_B

TI_TDO

TI_TDI

TI_TMS

2

1 C304

0.1UF

16V

X7R

NC

NC

2 4

63

51

U8

TL1963AKTTR

NC

NC NC

21

1%

1/16W

1.00K

R400

2

1 C411

0.068UF

10V

X5R

NC

NC

VCC3A_FLT 38

Page 36: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCCINT

VCC12_P

INH

FAULT

SRE

PWM

GND_1

GND_0

TEMP

IOUT

AGND

VOVI

VBIAS

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

0.005R

3W

0.1%

I2I1

E1 E2

VCCINT_FPGA

VCCINT_FPGA

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

VCC5

AGND1

0603_SHORT

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

PTD08A020W 20A Max. Power Channel

<=1.5V : DNP

>1.5V = 787 ohms

PTD08A020W 20A Max. Power Channel

VCCINT @ 20A

BF36 48

9-17-2009_15:42 D

04

1 2Z3

4 5

63

2 7

81

INA333

U74

2

1 C315

820PF

25V

X7R

1

2

R134

DNP

1/16W

1%

21

1%

1/16W

1.00K

R306

1

2

C277

330UF

16V

ELEC

I2I1

E1 E2

R208

VCC1_SENSE_P

21

1%

1/16W

4.22K

R117

1

2

C272

330UF

10V

TANT

VCC1_SENSE_N

2

1 C144

22UF

25V

X5R

1

2

C299

47UF

6.3V

TANT

8910

11

32 5 6 7

41

12

U42

PTD08A020W

35 VCC1_EA_N

VCC1_EA_P35

35VCC1A_CS

TEMP135

35VCC1A_FLT

35VCC1A_SRE

VCC1A_PWM 35

35,37,38,41,42,43,44PWR_INH

NC

Page 37: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC5

VCC2V5

VCC12_P

INH

FAULT

SRE

PWM

GND_1

GND_0

TEMP

IOUT

AGND

VOVI

VBIAS

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC2V5_FPGA

VCC2V5_FPGA

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

0.005R

3W

0.1%

I2I1

E1 E2

0603_SHORT

AGND2

<=1.5V : DNP

>1.5V = 787 ohms

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

PTD08A020W 20A Max. Power Channel

PTD08A020W 20A Max. Power Channel

VCC2V5 @ 20A

04

D9-17-2009_15:42

4837 BF

1 2Z4

1

2

R142

1.80K

1/16W

1%

1 2

R320

2.21K

1/16W

1%

2

1 C316

820PF

25V

X7R

1

2

C278

330UF

16V

ELEC

I2I1

E1 E2

R365

1

2

C301

47UF

6.3V

TANT

1

2

C274

330UF

10V

TANT

21

1%

1/16W

4.22K

R119

4 5

63

2 7

81

INA333

U76

35VCC2A_FLT

35VCC2A_SRE

VCC2A_PWM 35

12

1 4

7652 3

11

10

9 8

PTD08A020W

U43

TEMP235

NC

35,36,38,41,42,43,44PWR_INH

VCC2_EA_P35

35 VCC2_EA_N

2

1 C145

22UF

25V

X5R

VCC2_SENSE_P

VCC2_SENSE_N

35VCC2A_CS

Page 38: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

AGND3RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

VCC12_P

INH

FAULT

SRE

PWM

GND_1

GND_0

TEMP

IOUT

AGND

VOVI

VBIAS

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

0.005R

1W

0.1%

I2I1

E1 E2

VCC5

0603_SHORT

VCCAUX

VCCAUX

VCCAUX @ 10A

<=1.5V : DNP

>1.5V = 787 ohms

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

PTD08A010W 10A Max. Power Channel

PTD08A010W 10A Max. Power Channel

04

D

BF38 48

9-17-2009_15:42

1 2Z5

1

2

R392

787

1/16W

1%

21

1%

1/16W

1.00K

R396

2

1 C409

820PF

25V

X7R

I2I1

E1 E2

R395

VCC3_EA_P35

TEMP335

8910

11

32 5 6 7

41

12

U91

PTD08A010W

1 2

R390

4.22K

1/16W

1%

2

1

TANT

6.3V

47UF

C407 1

2

C403

330UF

10V

TANT

1 8

72

3 6

54

U93

INA333

2

1 C400

22UF

25V

X5R

1

2

ELEC

16V

330UF

C405

VCC3_SENSE_P

35VCC3A_CS

35VCC3A_FLT

35VCC3A_SRE

VCC3A_PWM 35

NC

35,36,37,41,42,43,44PWR_INH

VCC3_SENSE_N

35 VCC3_EA_N

Page 39: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

G

DT

S

D2

0

VCC12_P

SC70-6

INA213

REF

IN_N

OUT

IN_PV_P

GND

VCC12_P

VCC12_P

IN_P

VCC_N

OUT

IN_N

VCC_P

+ -

VCC2V5

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

12V

5V

COM

COM

EC

B

COM

N/C

12V

12V

N/C

COM

3W

I2I1

E1 E2

DPDT

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

TI UCD9240 Power System

ATX Peripheral Cable

as a 100 ohm differential pair

Route VAUX_VOLT_R and VAUX_COMMON_R

as a 100 ohm differential pair

refer to the System Monitor User Guide

refer to the System Monitor User Guide

Route VAUX_CURR_R and VAUX_COMMON_R

12V Power Jacks, 12V Fan

UCD9420 Fan Circuit System Monitor Fan Circuit

1

3

2

4

6

5

SW2

1201M2S3AQE2

04

D10-14-2009_14:48

4839 BF

1

2

R377

24K

1/10W

1%

I2I1

E1 E2

R346

Y14880R00100B09R

0.001R0.5%

3

2

1

J33

1

2

3

J59

1

2

C280

330UF

16V

ELEC

NC

1

4

3

6

2

5

J60

39-30-1060

34

1 Q1

MJD200

1

2

3

4

J25

350211-1

3

2

1

4

5

U41

TS321IDBVR

2

1

1%

1/16W

1.00K

R375

1

2

X7R

16V

0.01UF

C375

21

1%

1/16W

1.00K

R376

1 2

R374

1.00K

1/16W

1%

2

1 C374

0.01UF

16V

X7R

1

2

X5R

10V

0.1UF

C370

2

1 C85

0.1UF

10V

X5R

1

2

R323

1.00K

1/16W

1% 2

1 C313

1UF

16V

X5R

TI_V3P3

1 2

R2

33.2K

1/16W

1%

1 2

R329

1.3K

1/16W

5%

1

2

R254

10.0K

1/16W

1%

35FAN_TACH

FAN_PWM35

NC

NC

21

DS25

LED-GRN-SMT

2

1

1%

1/16W

1.00K

R322

1

5

6

43

2

U85

21

D16

1N4148

75V

500MW

1

2

R367

10.0K

1/16W

1%

1

4

3

2

Q24 NDT3055L

1.1W

21

1%

1/16W

10.0K

R368

2

1

1%4.75K

R358

2

1

1%

1/16W

10.0K

R369

SM_FAN_PWM4

SM_FAN_TACH4

VAUX_VOLT_R 3

VAUX_COMMON_R 3

VAUX_CURR_R 3

NC

NC

VCC12_P_IN

Page 40: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

9240

AGND2

9240

AGND2

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

/RESET

/TRST

ADC_REF

ADDRSEN0ADDRSEN1

AG

ND

1A

GN

D2

AG

ND

3

AUX-IN_AD13AUX-IN_AD14

BPCAP

CS-1ACS-1B

CS-2ACS-2B

CS-3ACS-3B

CS-4ACS-4B

DG

ND

1D

GN

D2

DG

ND

3

DIAG-LED

DPWM-1ADPWM-1B

DPWM-2ADPWM-2B

DPWM-3ADPWM-3B

DPWM-4ADPWM-4B

EAN1

EAN2

EAN3

EAN4

EAP1

EAP2

EAP3

EAP4

FAN-PWMFAN-TACH

FAULT-1AFAULT-1B

FAULT-2AFAULT-2B

FAULT-3AFAULT-3B

FAULT-4AFAULT-4B

PMBUS_ALERT

PMBUS_CLKPMBUS_CTRL

PMBUS_DATA

PWRGOOD

SRE-1ASRE-1B

SRE-2ASRE-2B

SRE-3ASRE-3B

SRE-4ASRE-4B

SYNC-INSYNC-OUT

TCK

TDITDO

TEMP

TMS

TMUX0TMUX1TMUX2

TRCK

V33

AV

33D

V33

DIO

1V

33D

IO2

V33

FB

VIN

VTRACK

A4

A6

A

A7

A5

E_B

VEE

GND S2

S1

S0

A3

A0

A1

A2

VCC

0603_SHORT

9240

DGND2

9240

AGND2

9240

AGND2

9240

AGND2

9240

AGND2

VCC12_P

9240

AGND2

9240

DGND2

9240

AGND2

9240

DGND2

9240

DGND2

9240

DGND2

9240

DGND2

9240

AGND2

9240

AGND2

0603_SHORT

PMBus Address is calculated as follows:

ADDRSENxRPMBusValue

11109876543210Short

Open -

-

Note:

158k115k84.5k63.4k47.5k36.5k

210k

27.4k21.5k16.9k13.0k10.2k

PMBus Address = 12 × Value(ADDRSEN1) + Value(ADDRSEN0)

Example: ADDRSEN1 R=27.4k and ADDRSEN0 R=27.4k

PMBus Address = (12 x 4) + 4 = 52 decimal

Do not use PMBus Addresses 0, 1, 2, 3, 12, 126 or 127

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

VCCxxxx_EAP/N are remote sense

pairs wired back from power plane

PMBus Connector

connections at FPGA

SCHEM, ROHS COMPLIANT

TI UCD9240 Power System

FPGA UCD9240 PMBus Controller

AGND should be a copper island underneaththe 9240 and every associated module

BF40 48

9-24-2009_11:19 D

04

21Z7

MGT_VCC3V3A

MGT_VCC3V3A

1

2

X5R

10V

0.1UF

C420

2

1 C87

0.1UF

10V

X5R

2

1 C249

4.7UF

16V

Y5V

21

FERRITE-220

F1114

2

1

X5R

10V

4.7UF

C2001

2

X7R

16V

0.1UF

C176

2

1 C118

10UF

16V

X5R

1 2

F1113

FERRITE-220

1 2Z6

NC

NC

NC

NC

NC

41MGT_VCC1A_SRE

1

2

R99

36.5K

1/16W

1%

1

2

1%

1/16W

27.4K

R272

42MGT_VCC2A_CS

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16

U3

CD74HC4051

13

48

1

77

76

61

60

80

72

71

59

75

79

4

78

3

74

2

73

9 34

55

10

21

22

23

24

25

26

27

28

63

65

67

69

62

64

66

68

53

32

15

16

17

18

29

41

42

43

35

19

36

20

49

12

11

51

37

38

52

33

50

31

30

44

46

45

7

47

39

40

54

14

58

57

8

56

70

5

6

U25

UCD9240PFC

40 MGT_TMUX2

MGT_TMUX140

MGT_TMUX040

40MGT_TMUX2

MGT_TMUX1 40

MGT_TMUX0 40

1

32

Q13

2

1

1%

1/16W

10.0K

R3831

2

R257

10.0K

1/16W

1%

31MGT_TI_PWRGOOD

32,35 PMBUS_CTRL

PMBUS_CLK32,35

32,35 PMBUS_DATA

32,35 PMBUS_ALERT

NC

43MGT_VCC3_EA_N

43MGT_VCC3_EA_P

43MGT_VCC3A_FLT

43MGT_VCC3A_SRE

43MGT_VCC3A_PWM

NC

MGT_VCC1A_CS 41

2

1 C321

6800PF

25V

X7R

1 2

R324

1.00K

1/16W

1%41MGT_VCC1_EA_N

41MGT_VCC1_EA_P

41MGT_VCC1A_FLT

41MGT_VCC1A_PWM

NC

1

2

3

4

J7

DNP

MGT_TI_TDO

MGT_TI_TDI

MGT_TI_TMS

42MGT_VCC2_EA_N

MGT_VCC2A_FLT 42

MGT_VCC2A_SRE 42

42MGT_VCC2A_PWM

MGT_TI_V3P3

2

1 C322

6800PF

25V

X7R

1 2

R325

1.00K

1/16W

1%

2

1

J14

21C353

4.7UF

10V

X5R

1

2

R263

10.0K

1/16W

1%

1

2

J13

2

1

1%

1/16W

10.0K

R262

21

D15

BZT52C5V1-TP

5.1V

500MW

1

2

X5R

10V

0.1UF

C89

1

2

R260

10.0K

1/16W

1%

2

1

1%

1/16W

10.0K

R2591

2

R258

10.0K

1/16W

1%

2

1 C175

0.01UF

16V

X7R

1

2

X5R

10V

0.1UF

C88

2

1 C86

0.1UF

10V

X5R

1

2

1%

1/16W

10.0K

R256

1

2

1%

1/16W

10.0K

R255

2

1

J12

MGT_TI_V3P3

MGT_VCC2_EA_P 42

MGT_TI_RESET_B

MGT_TRST_B

MGT_TI_TCK

NC

NC

NC

NC

NC

NC

NC

NC

2

1 C308

0.1UF

16V

X7R

21

C90

0.1UF

10V

X5R

2

1 C254

0.068UF

10V

X5R

NC

MGT_TEMP1 43

NC

NC

MGT_TEMP

NC

MGT_TEMP2 44

NC

NC

44MGT_VCC4A_PWM

44MGT_VCC4A_SRE

44MGT_VCC4A_FLT

44MGT_VCC4_EA_P

44MGT_VCC4_EA_N

1 2

R380

2.0K

1/16W

5%

2

1 C410

6800PF

25V

X7R

1 2

R399

1.00K

1/16W

1%

MGT_VCC3A_CS 43

VCC1B_FLT 35

35VCC2B_FLT

VCC3B_FLT 35

35VCC4B_FLT

2

1 C307

0.1UF

16V

X7R

Page 41: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

AGND5

AGND5

AGND5

G1

G2

DR74-2R2

VCC12_P

VCC12_P

VCC12_P

VCC2V5

VDD

SW

SRE

PWRPAD

PVDD

POS

PGND OUT2

OUT1

NEG

IO

IN

ILIM

DLY

CS+

CLF

CBIAS

BST

AGND

A0

3V3

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

D2

G2

S2

1.3W

SI4944DY

1.3W

S1

G1

D1

SI4944DY

AGND5

0603_SHORT

AGND5

AGND5

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

TI UCD9240/UCD7230 Power System

SCHEM, ROHS COMPLIANT

UCD7230 6A Max. Power Channel

Local AGND to be tied to local GNDSee UCD7230 datasheet layout recommendations

41 48

9-17-2009_15:42

BF

D

04

21Z8

1

2

87

Q3

3

4

65

Q3

1

2

R410

DNP

1/16W

1%

1

2

R172

51K

1/16W

5%

1

2

C418

330UF

10V

TANT

MGT_AVCC21

1%

1/16W

1.00K

R330

2

1 C327

820PF

25V

X7R

1

2

R162

DNP

1/16W

1%

1 2

R237

100

1/16W

1%

1

2

X5R

25V

22UF

C149

2

1 C148

22UF

25V

X5R

21

C310

0.1UF

16V

X7R

2

1 C147

22UF

25V

X5R

2

1 C309

0.1UF

16V

X7R1

2

X5R

10V

0.1UF

C93

MGT_AVCC

18

15

19

21

12

8

10 11

14

9

6

20

4

3

17

5

16

13

2

7

1

U35

UCD7230RGWR

1

32

Q9

NDS331N

2

1

1%

1/16W

10.0K

R265

21

DS27

LED-GRN-SMT

1

2

R194

1.0

1/10W

1%

2 1

1%

1/16W

10.0K

R264

2

1 C355

4.7UF

10V

X5R

21

D11

MBR0520LT1G

20V

500MA

2 1

500MA

20V

MBR0520LT1G

D10

1 2

R193

1.0

1/10W

1%

1 2

R115

0.006

0.5W

1.0%

1 2

L7

2.2UH

4.76A

20%

21

1%

1/16W

10.0

R176

1

2

R175

10.0

1/16W

1%

1

2

R337

215

1/16W

1%

1

2

R199

2.2

1/10W

1%

1

2

R197

33.0

1/16W

1%2

1 C140

100PF

50V

NPO

2

1 C325

2700PF

50V

X7R

21C258

0.22UF

10V

X5R

2

1 C257

0.22UF

10V

X5R

1

2

X5R

6.3V

1UF

C192

2

1 C241

10UF

10V

X5R

2

1 C263

22UF

10V

X5R

2

1 C262

22UF

10V

X5R

2

1 C261

22UF

10V

X5R

2

1 C354

4.7UF

10V

X5R

2

1 C178

0.01UF

16V

X7R

1

2

X5R

10V

0.1UF

C92 1

2

X5R

10V

0.1UF

C91

21

1%

1/16W

100

R236

1 2

R235

100

1/16W

1%

8

3

6

5

4

U12

SN74LVC2G08DCU

7

2

1

U12

SN74LVC2G08DCU

MGT_VCC1_EA_P40

35,36,37,38,42,43,44

PWR_INH

MGT_VCC1A_PWM40

MGT_VCC1A_SRE40

MGT_VCC1A_CS40

MGT_VCC1A_FLT40

MGT_VCC1_CS_N

MGT_VCC1_CS_P

MGT_AVCC

1

2

1%

1/16W

27.4

R19

1

2

R135

DNP

1/16W

1%

1

2

R136

DNP

1/16W

1%

40 MGT_VCC1_EA_N

Page 42: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

AGND6

AGND6

0603_SHORT

G1

G2

DR74-2R2

VDD

SW

SRE

PWRPAD

PVDD

POS

PGND OUT2

OUT1

NEG

IO

IN

ILIM

DLY

CS+

CLF

CBIAS

BST

AGND

A0

3V3VCC12_P

VCC12_P

VCC12_P

VCC2V5

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

D2

G2

S2

1.3W

SI4944DY

1.3W

S1

G1

D1

SI4944DY

AGND6

AGND6 AGND6

AGND6

Local AGND to be tied to local GNDSee UCD7230 datasheet layout recommendations

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

TI UCD9240 Power System

UCD7230 6A Max. Power Channel

04

D

BF

9-17-2009_15:42

4842

1

2

87

Q4

3

4

65

Q4

1

2

R411

DNP

1/16W

1%

1

2

R173

51K

1/16W

5%

21

1%

1/16W

1.00K

R331

2

1 C328

820PF

25V

X7R

1

2

R163

DNP

1/16W

1%

PWR_INH

35,36,37,38,41,43,44

MGT_AVTT

1

32

Q10

NDS331N

2

1

1%

1/16W

10.0K

R267

21

DS28

LED-GRN-SMT

1

2

R196

1.0

1/10W

1%

18

15

19

21

12

8

10 11

14

9

6

20

4

3

17

5

16

13

2

7

1

U36

UCD7230RGWR

2 1

1%

1/16W

10.0K

R266

2

1 C357

4.7UF

10V

X5R

21

D13

MBR0520LT1G

20V

500MA

2 1

500MA

20V

MBR0520LT1G

D12

1 2

R195

1.0

1/10W

1%

1 2

R116

0.006

0.5W

1.0%

1 2

L8

2.2UH

4.76A

20%

21

1%

1/16W

10.0

R180

1

2

R179

10.0

1/16W

1%

1

2

R338

215

1/16W

1%

1

2

R200

2.2

1/10W

1%

1

2

R198

33.0

1/16W

1%

1 2

R240

100

1/16W

1%

2

1 C141

100PF

50V

NPO

2

1 C326

2700PF

50V

X7R

21C260

0.22UF

10V

X5R

2

1 C259

0.22UF

10V

X5R

1

2

X5R

6.3V

1UF

C195

2

1 C242

10UF

10V

X5R

2

1 C266

22UF

10V

X5R

2

1 C265

22UF

10V

X5R

2

1 C264

22UF

10V

X5R

1

2

X5R

10V

0.1UF

C96

2

1 C356

4.7UF

10V

X5R

2

1 C179

0.01UF

16V

X7R

1

2

X5R

10V

0.1UF

C95 1

2

X5R

10V

0.1UF

C9421

1%

1/16W

100

R239

1 2

R238

100

1/16W

1%

8

3

6

5

4

U13

SN74LVC2G08DCU

7

2

1

U13

SN74LVC2G08DCU

MGT_VCC2_EA_P40

40 MGT_VCC2_EA_N

40 MGT_VCC2A_FLT

40 MGT_VCC2A_PWM

40 MGT_VCC2A_CS

40 MGT_VCC2A_SRE

MGT_VCC2_CS_N

MGT_VCC2_CS_P

MGT_AVTT

1

2

X5R

25V

22UF

C152

2

1 C151

22UF

25V

X5R

21

C312

0.1UF

16V

X7R

2

1 C150

22UF

25V

X5R

2

1 C311

0.1UF

16V

X7R

1

2

1%

1/16W

27.4

R20

1

2

R137

DNP

1/16W

1%

1

2

R138

DNP

1/16W

1%

1

2

C419

330UF

10V

TANT

MGT_AVTT

21Z9

Page 43: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC5

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

VCC12_P

INH

FAULT

SRE

PWM

GND_1

GND_0

TEMP

IOUT

AGND

VOVI

VBIAS

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC1V5_FPGA

0.005R

1W

0.1%

I2I1

E1 E2

VCC1V5_FPGA

AGND7

0603_SHORT

<=1.5V : DNP

>1.5V = 787 ohms

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

VCC1V5 @ 10A

SCHEM, ROHS COMPLIANT

PTD08A010W 10A Max. Power Channel

PTD08A010W 10A Max. Power Channel

9-17-2009_15:42

4843 BF

D

04

21Z10

2

1 C318

820PF

25V

X7R

1

2

R139

DNP

1/16W

1%

1 2

R311

1.00K

1/16W

1%

1

2

C281

330UF

16V

ELEC

MGT_VCC3_SENSE_N

40MGT_VCC3A_CS

I2I1

E1 E2

R398

VCC1V5

MGT_TEMP140

40MGT_VCC3A_FLT

40MGT_VCC3A_SRE

MGT_VCC3A_PWM 40

8910

11

32 5 6 7

41

12

U20

PTD08A010W

2

1

TANT

6.3V

47UF

C302 1

2

C275

330UF

10V

TANT

NC

35,36,37,38,41,42,44PWR_INH

MGT_VCC3_EA_P40

40 MGT_VCC3_EA_N

2

1 C153

22UF

25V

X5R

1 2

R397

4.22K

1/16W

1%

1 8

72

3 6

54

U94

INA333

MGT_VCC3_SENSE_P

Page 44: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC12_P

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

INH

FAULT

SRE

PWM

GND_1

GND_0

TEMP

IOUT

AGND

VOVI

VBIAS

0603_SHORT

AGND8

<=1.5V : DNP

>1.5V = 787 ohms

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

VCC3V3 @ 10A

PTD08A010W 10A Max. Power Channel

PTD08A010W 10A Max. Power Channel

04

D9-17-2009_15:42

4844 BF

21Z11

1

2

R144

1.60K

1/16W

1%

1 2

R328

2.21K

1/16W

1%

2

1 C319

820PF

25V

X7R

1

2

C282

330UF

16V

ELEC

8910

11

32 5 6 7

41

12

U21

PTD08A010W

VCC3V3

VCC3V3

MGT_VCC4_EA_N40

40 MGT_VCC4_EA_P

40 MGT_TEMP2

MGT_VCC4A_SRE 40

40MGT_VCC4A_PWM

2

1

TANT

6.3V

47UF

C303 1

2

C276

330UF

10V

TANT

NC

PWR_INH 35,36,37,38,41,42,43

MGT_VCC4A_FLT 40

2

1 C154

22UF

25V

X5R

Page 45: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCCINT_FPGA

VCCINT_FPGA VCC2V5

VCC2V5

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VTTDDR

VCC2V5

VCC1V8

VCC2V5VCC2V5

VTTVREF

VIN

PGOOD

GND

REFOUT

EN

REFIN

VLDOIN

VO

PGND

VOSNS

PWRPAD

CON_SMA_SCREW_ON

CON_SMA_SCREW_ON

SOT223-6

SHDN_N

IN

GND1 OUT

SNS_ADJ

GND2

TL1963A-18DCQR

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

VCC1V8 @ 500mA

DDR3 Termination Regulator

DDR3 Termination Regulator, power probes

MGT Power Probe Channels

DDR3 Power Good

VCCINT_FPGA, VCCAUX Power Probe Channels

BF45 48

9-17-2009_15:42 D

04

1

2

3 4

5

6

U79

1

2 3

J46

DNP

1

2 3

J45

DNP

2 3 4 5 6 7 8 9

10

11

12

13

14

15

1

J48

DNP

1

15

14

13

12

11

1098765432

DNP

J47

1

15

14

13

12

11

1098765432

DNP

J44

2 3 4 5 6 7 8 9

10

11

12

13

14

15

1

J43

DNP

10

9

8

6

7

1

2

3

4

5

11U17

TPS51200DRCT

MGT_AVCC

2

1 C97

0.1UF

10V

X5R

2

1 C199

1UF

6.3V

X5R

1

2

X7R

16V

0.01UF

C180

2

1 C181

0.01UF

16V

X7R

2

1 C246

10UF

10V

Y5V

1

2

Y5V

10V

10UF

C245 1

2

Y5V

10V

10UF

C243

2

1 C247

10UF

10V

Y5V

2

1 C244

10UF

10V

Y5V

21

1%

1/16W

10.0K

R269

1 2

R268

10.0K

1/16W

1%

2

1 C256

1000PF

50V

X7R

2

1 C358

4.7UF

10V

X5R

1

2

R302

100K

1/16W

5%

VCC1V5

21

DS29

LED-GRN-SMT

1

32

Q11

NDS331N

2

1 C198

1UF

6.3V

X5R

VCC3V3

1

2

1%

1/16W

27.4

R21

MGT_AVTT

Page 46: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

B1

E

P

B1

B1

B1

A

B

C

D

1234

D

C

B

A

4 3 2 1

Drawing Number:

Date:

Sheet Size: D

Sheet of

Ver:

Rev:

Drawn By

E

F

G

H

E

F

G

H

5678

5678

LAST REVISION:

B1

B1

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

GND;2,19,21,39,48,50

GND;65,75,94,99

TQFP100

AGND

AVCC

BKPT

CLKOUT

CTL0_FLAGA

CTL1_FLAGB

CTL2_FLAGC

CTL3

CTL4

CTL5

D+

D-

IFCLK

INT4

NC1

NC2

NC3

PA0_INT0

PA1_INT1

PA2_SLOE

PA3_WU2

PA4_FIFOADR0

PA5_FIFOADR1

PA6_PKTEND

PA7_FLAGD

PB0_FD0

PB1_FD1

PB2_FD2

PB3_FD3

PB4_FD4

PB5_FD5

PB6_FD6

PB7_FD7

PC0_GPIFADR0

PC1_GPIFADR1

PC2_GPIFADR2

PC3_GPIFADR3

PC4_GPIFADR4

PC5_GPIFADR5

PC6_GPIFADR6

PC7_GPIFADR7

PD0_FD8

PD1_FD9

PD2_FD10

PD3_FD11

PD4_FD12

PD5_FD13

PD6_FD14

PD7_FD15

PE0_T0OUT

PE1_TIOUT

PE2_T2OUT

PE3_RXD0OUT

PE4_RXD1OUT

PE5_INT6

PE6_T2EX

PE7_GPIFADR8

RDY0

RDY1

RDY2

RDY3

RDY4

RDY5

RESERVED

RXD0

RXD1

SCL

SDA

T0

T1

T2

TXD0

TXD1

WAKEUP

XTALIN

XTALOUT

INT5

RD

RESET

WR

PORT E

PORT A

PORT C

PORT D

PORT B

VCCINT

GPIF

GPIF

PORT E

PORT A

PORT E

GND

SHLD4

VBUS

D_N

D_P

SHLD1

SHLD2

SHLD3

ID

USB_MINI_B

VQFP100

GND;21,25,31,62

GND;69,75,84,100

BIT_CLOCK

BUFFER_OE

BUS_ENABLE

COUNT0

COUNT1

COUNT2

COUNT3

COUNT4

CTRL1

CTRL2

DONE

DONE_INH

DONE_SM0

DONE_SM1

DONE_SM2

DOWN_CNT0

DOWN_CNT1

DOWN_CNT2

DOWN_CNT3

DOWN_CNT4

EXTEND

GPIF_D00

GPIF_D01

GPIF_D02

GPIF_D03

GPIF_D04

GPIF_D05

GPIF_D06

GPIF_D07

GPIF_D08

GPIF_D09

GPIF_D10

GPIF_D11

GPIF_D12

GPIF_D13

GPIF_D14

GPIF_D15

IDLE_FLAG

INIT_IN

INIT_OUT

JTP_CMD0

JTP_CMD1

JTP_CMD2

LAST_BIT

LAST_WORD

RDY1

RDY2

SHIFT_CLK

SPARE_COM

SPARE_P065

SPARE_P071

SPARE_P073

SPARE_P074

SPARE_P076

SPARE_P077

SPARE_P078

SPARE_P079

SPARE_P080

SPARE_P081

SPARE_P082

SPARE_P085

SPARE_P086

SPARE_P087

SPARE_P089

SPARE_P090

SPARE_P091

SPARE_P092

SPARE_P099

START

TAP_STATE0

TAP_STATE1

TAP_STATE2

TAP_STATE3

TCK

TCK_CCLK

TDI

TDI_DIN

TDO

TDO_B

TDO_SAMPLE_CLOCK

TMS

TMS_LEVEL

TMS_PROG

VERSION

BANK 2

BANK 1

BANK 1

BANK 1

BANK 1

BANK 1

BANK 2

VCCINT

VAUX

VCCIO1

VCCIO2

TAP

BANK 2

BANK 2

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

FPGA_TCK

LEGEND:

COMPONENTS TO BE LOADED FOR THE PRODUCTION

ASSEMBLY VERSION ONLY.

LOCAL 2MM CABEL CONNECTOR J1.

OPTIONAL NETS ROUTED IN PARALLEL TO

AND/OR DIAGNOSTICS.

OPTIONAL COMPONENTS THAT SUPPORT DEBUG

SCHWEIGLER

USB TYPE B

RECEPTACLE

USB

CONVERTER

6 PLACES

3 PLACES

USB CONTROLLER

CONNECTOR

PARALLEL TO SERIAL

NOTE: EMBEDDED VERSION

2 PLACES

N/C

FROM JTAGTO

LAST DEVICE TDO

FIRST DEVICE TDI

TARGET INTERFACE CONNNECTIONS

3.3V INTERFACE TO LOCAL JTAG OR SLAVE-SERIAL DEVICE CHAIN.

AND EMBEDDED_TMS WITH LVDS BUFFERS.

14-JUNE-2006

IS NOT BUS POWERED

TCK ALL DEVICES

TMS ALL DEVICES

FOR LONG CHAINS OR TRACES, DISTRIBUTE EMBEDDED_TCK

OF THE NETS MARKED TO FACILITATE FASTER IN-CIRCUIT

RE-PROGRAMMING OF THE CPLD DURING BOARD TEST.

ASSEMBLY FOOTPRINT IS RECOMMENDED FOR THE PWB LAYOUT.

NOTE:

J1 DOES NOT NEED TO BE POPULATED DURING PRODUCTION, BUT THE

0381242

MAKE PARALLEL CONNECTIONS TO J1 (OPTION B) AT EACH

3 PLACES

FPGA_TMS

USB_HEADER_TDI

JTAG_TDO

EMBEDDED_INIT NO CONNECTION

FPGA_TCK

Embedded USB JTAG: USB Controller, CPLD

The Embedded USB JTAG Download circuit on this page is for reference only!This circuit should not be designed into an end customer product or solution.Xilinx will not provide support on this embedded USB JTAG Download circuit.

2

1 C142

3.3UF

10V

22

61

2

14

15

16

17

18

54

55

63

8

3

6

7

97

96

95

94

93

24

77

76

74

73

72

71

85

86

87

89

65

99

11

1

92

91

90

13

10

12

82

78

79

80

81

32

33

34

35

36

37

39

40

41

42

43

44

46

49

50

52

28

70

19

29

30

4

58

64

59

9

53

48

66

45

68

47

60

67

56

83

27

23

U22

PART_NUMBER=XC2C256

VCC3V3;20,38,51

VCC3V3;88,98

VCC3V3;5

VCC1V8;26,57

04

B

46 489-24-2009_11:19

NC

NC

5

9

1

2

3

678

4

J22

12

9

28

54

55

56

51

52

76

17

18

22

13

14

15

67

68

69

70

71

72

73

74

34

35

36

37

44

45

46

47

57

58

59

60

61

62

63

64

80

81

82

83

95

96

97

98

86

87

88

89

90

91

92

93

3

4

5

6

7

8

27

41

43

29

30

23

24

25

40

42

79

11

10

84

31

77

32

100

26

U26

PART_NUMBER=CY7C68013A

VCC3V3;1,16,20,33,38

VCC3V3;49,53,66,78,85

16JTAG_TMS

16JTAG_TCK

JTAG_TDO 13

JTAG_TDI16

1

2

R290

10K

1/16W

5%

USBHDR_TDI_R

USBHDR_TMS_R

USBHDR_TCK_R

NC

NC

NC

SPARE_COM

CPLD_TDO47

CPLD_TDI47

CPLD_TMS47

CPLD_TCK47

2

1R279

10K

1/16W

5%

2

1 C98

0.1UF

10V

X5R

1

2

NPO

50V

11PF

C331

2

1 C330

11PF

50V

NPO

21

Y1

24MHZ

21R151

15

1/16W

5%

1 2

5%

1/16W

15

R150

21R149

15

1/16W

5%

EMBEDDED_INIT

1

2

R297

20K

1/16W

5%

2

1R278

10K

1/16W

5%

POR47

USB_SDA47

USB_SCL47

LED_GRN47

LED_RED47

SERIAL_NUMBER47

NC

NC

NC

NC

NC

NC

NC

1

2

R295

20K

1/16W

5%

2

1R289

10K

1/16W

5%

12

5%

1/16W

10K

R284

2 1R287

10K

1/16W

5%

12

5%

1/16W

10K

R286

2 1R283

10K

1/16W

5%

2

1R282

10K

1/16W

5%

2

1R281

10K

1/16W

5%

2 1R277

10K

1/16W

5%

12

R276

2 1R275

GPIF_DONE

GPIF_START

JTP_CMD3

VREF_DETECT

VERSION_REQUEST

TDO_SAMPLE_CLK

LAST_WORD

TMS_LEVEL

GPIF_D15

GPIF_D00

GPIF_D01

GPIF_D02

GPIF_D03

GPIF_D04

GPIF_D05

GPIF_D06

GPIF_D07

GPIF_D08

GPIF_D09

GPIF_D10

GPIF_D11

GPIF_D12

GPIF_D13

GPIF_D14

CTRL2

CTRL3

COUNT0

COUNT1

COUNT2

COUNT3

COUNT4

JTP_CMD0

JTP_CMD1

JTP_CMD2

RDY1

RDY2

BIT_CLOCK

1

2

5%

1/16W

10K

R280

2 1R285

10K

1/16W

5%

12

5%

1/16W

10K

R288

2

1

5%

1/16W

20K

R296

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

2

1

5%

1/16W

10K

R291

NC

2

1 1%4.

75KR19

2

BUFFER_OE

NC

Page 47: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

VCC3V3

E

E E

P

A

B

C

D

1234

D

C

B

A

4 3 2 1

Drawing Number:

Date:

Sheet Size: D

Sheet of

Ver:

Rev:

Drawn By

E

F

G

H

E

F

G

H

5678

5678

LAST REVISION:

E

VCC3V3

VCC3V3

VCC3V3

VCC3V3 VCC1V8

VCC3V3

VCC3V3

E

E

GND

SCL

SDA

VCC

NC

NC

NC

NC

GR

MAX6412UK22

GND

VCC

MR

RESET

SRT

SUPERVISORY

POWER

DS2411

I/O

GND

VCC

NC

NC

NC

TSM_107_01_L_DV

GND

GND

GND

GND

GND

TDI

GND

TMS

VTST

VREF

TCK

INIT

GTST

TDO

The Embedded USB JTAG Download circuit on this page is for reference only!This circuit should not be designed into an end customer product or solution.Xilinx will not provide support on this embedded USB JTAG Download circuit.

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

VENDOR ID

PRODUCT ID

DATA FIELD

I2C EEPROM

LED

SCHWEIGLER

STATUS

DEFAULT

CYPRESS

0x004B4

0x8613

0x03FD

XILINX

EMBEDDED

14-JUNE-2006

DEFAULT PID/VID EEPROM

POWER-ON RESET

BYPASS CAPACITORS

NOTE: PRODUCES 5MS POWER-ON RESET

STATUS LEDS (OPTION A)

PC4 JTAG CONNECTOR (OPTION B)

ELECTRONIC SERIAL NUMBER

0x000D

PROM PRIOR TO ASSEMBLY.

LOW POWER BOOT CONDITIONS

0381242

USE FILE 1080058 (HEX) TO PROGRAM THE I2C

Embedded USB JTAG: IIC, POR, Decoupling, LED, JTAG Header, Serial Number

B

48479-24-2009_11:19

04

1

10

11

12

13

14

2

3

4

5

6

7

8

9

J24

DNP

5

3

42

1

6

U18

2

5

3

1

4

U40

1 2

3

DS23

SSL-LX15IGC

12

H-1X2J40

USB_SDA46

2

1

1%

1/16W

100K

R303

1

2 X7R

16V

0.01UF

C182

2

1 C329

1800PF

50V

X7R

7

4

3 6

5

81

2

U3924LC00T-SN

2

1R243

2.0K

1/16W

5%

USB_SCL46

1

2

R298

20K

1/16W

5%

LED_RED46

LED_GRN46

SERIAL_NUMBER46

POR 46

1

2

C227

3.3UF

25V

TANT

1

2

R333

270

1/16W

5%

1

2

R332

360

1/16W

5%

2

1 C116

0.1UF

10V

X5R

2

1 C109

0.1UF

10V

X5R

1

2

X5R

10V

0.1UF

C99 1

2

X5R

10V

0.1UF

C106

2

1 C103

0.1UF

10V

X5R

1

2

X5R

10V

0.1UF

C102

2

1 C100

0.1UF

10V

X5R

21

5%

1/16W0

R312

NC

2

1R244

2.0K

1/16W

5%

2

1R242

2.0K

1/16W

5%

NC

NC

NC

NC

NC

NC

1

2

X5R

10V

0.1UF

C101 1

2

X5R

10V

0.1UF

C104

2

1 C105

0.1UF

10V

X5R

2

1 C107

0.1UF

10V

X5R

1

2

X5R

10V

0.1UF

C108

1

2

X5R

10V

0.1UF

C110

2

1 C112

0.1UF

10V

X5R

1

2

X5R

10V

0.1UF

C111 1

2

X5R

10V

0.1UF

C114

2

1 C113

0.1UF

10V

X5R

1

2

X5R

10V

0.1UF

C115

CPLD_TDO46

CPLD_TCK46

CPLD_TMS46

NC

NC

46CPLD_TDI

Page 48: Xilinx XTP052 – ML605 Schematics (Rev D) · Xilinx XTP052 – ML605 Schematics (Rev D) ... b

SFP_BOT_CAGE

SFP_TOP_CAGE

RUBBER_BUMPER

JUMPER_BLOCK_2-PIN JUMPER_BLOCK_2-PINJUMPER_BLOCK_2-PIN

RUBBER_BUMPER

RUBBER_BUMPER

ofSheet

Date:

Title:

Ver:

A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

RUBBER_BUMPER

JUMPER_BLOCK_2-PIN

RUBBER_BUMPER

110V Prong Power Brick

Power Cord

LCD Display

USB A

USB Mini-B Cable

USB Mini-B

12v Power Brick

12V Fan / Heatsink

WASHER

1ZB34

0250446

PCIE

POWER

OE

GND

VCC

OUT

OSC

MACHINE_SCREW_SS_PHILHD_4-40_X_3-8

MACHINE_SCREW_SS_PHILHD_4-40_X_3-8

MACHINE_SCREW_SS_PHILHD_4-40_X_3-8

MACHINE_SCREW_SS_PHILHD_4-40_X_3-8

MACHINE_SCREW_SS_PHILHD_4-40_X_3-8

NUT_SS_4-40

NUT_SS_4-40

NUT_SS_4-40

NUT_SS_4-40

NUT_SS_4-40

ASSY P/N: 0431540

PCB P/N: 1280479

SCH P/N: 0381311

SCHEM, ROHS COMPLIANT

SSO Testpoints, FPGA 1.5V BanksMechanical Components

Mechanical Components

04

D

BF48 48

9-24-2009_11:19

MN4

MN2

MN3

MN5

MN1

MS3

MS2

MS4

MS5

MS1

1

4

8

5

MX?

MBH2100H-66.000MHZ

MSTK?

MS?

MN?

PL1

MMD1

HS1

PB1

CBL2

LCD1

CBL1

MRB1MSO1

MJB4

MJS1

MSO5 MRB5

1

MH_125_250

MH6

1

MH_125_250

MH4

1

MH3

MH_125_250

1

MH_125_250

MH2

1

MH1

MH_125_250

MSO3

MRB3

MRB2

MSO2

MJS2

MJB3 MJB2MJB1

MSO4MRB4

PB?

CG?