Indian Journal of Pure & Applied Physics

Vol. 45, April 2007, pp. 311-316

Wafer bonding — A powerful tool for MEMS

K N Bhat+, A Das Gupta, P R S Rao, N Das Gupta, E Bhattacharya, K Sivakumar, V Vinoth Kumar,

L Helen Anitha, J D Joseph, S P Madhavi & K Natarajan*

Electrical Engineering Department, Indian Institute of Technology Madras, Chennai 600 036

+Present address: ECE Department, Indian Institute of Science Bangalore 560 012

*Bharat Electronics Ltd, Jalahalli, Bangalore 560 013

Received 7 June 2006; accepted 16 October 2006

Wafer bonding techniques play a key role in the present day silicon bulk micromachining for MEMS based sensors and

actuators. Various silicon wafer bonding techniques and their role on MEMS devices such as pressure sensors,

accelerometers and micropump have been discussed. The results on the piezoresistive pressure sensors monolithically

integrated with a MOSFET differential amplifier circuit have been presented to demonstrate the important role played by the

Silicon Fusion Bonding technique for integration of sensors with electronics on a single chip.

Keywords: Silicon fusion bonding, Silicon on insulator, Piezoresitive pressure sensor, MOSFET amplifier integration with

sensor

IPC Code: B81B7/02

1 Introduction Wafer- level bonding of a silicon wafer to another

silicon substrate or to a glass wafer plays a key role in

all the leading-edge Micro-Electro-Mechanical

Systems (MEMS). When used along with the wet or

dry etching techniques, the wafer bonding technique

can be used to realize (1) membranes of thickness

varying from couple of microns to several microns,

suitable for pressure sensors over a wide range of

pressures, (2) complicated three dimensional

structures for accelerometers for sensing acceleration

and (3) multilayered device structures such as

micropump suitable for biomedical and microfluidic

applications, and (4) high aspect ratio structures

which can compete with the LIGA process. The

manufacturers of MEMS require wafer-level bonding

of one silicon wafer to another silicon substrate or a

glass wafer. This provides a first level packaging

solution that makes these processes economically

viable. In this paper we first discuss the various

silicon wafer bonding techniques and illustrate their

role on MEMS devices such as pressure sensors,

accelerometers and micropump. The results obtained

in our laboratory on the piezoresistive pressure

sensors monolithically integrated with a MOSFET

differential amplifier circuit are presented to

demonstrate the important role played by the Silicon

Fusion Bonding technique for the integration of

sensors with electronics on a single chip.

2 Wafer Bonding Techniques for MEMS Silicon wafer

1 bonding for MEMS is achieved by

several different approaches such as (1) anodic

bonding, (2) direct bonding and (3) intermediate layer

bonding which includes eutectic and glass-frit bonds.

Even though, the process conditions used for all the

three bonding techniques vary, the general process of

the wafer bonding follows a three step sequence

consisting of surface preparation, contacting and

annealing.

Anodic bonding involves bonding a silicon wafer

and a glass wafer with a high content of sodium. Fig.1

shows the schematic of the anodic bonding

arrangement. The anodic bonding is carried out at

450°C by applying a high voltage in the range

500 -1000 V as shown in Fig. 1 to attract NA+ ions to

the negative electrode where they are neutralized.

This leads to the formation of a space charge at the

Fig. 1 — Silicon –glass anodic bonding arrangement

INDIAN J PURE & APPL PHYS, VOL 45, APRIL 2007

312

glass silicon interface, thus creating a strong

electrostatic attraction between glass and silicon

wafer, enabling the transport of oxygen from the glass

to the glass-silicon interface and converts silicon to

SiO2 creating a permanent bond. Processes for anodic

bonding of silicon to bulk glass and silicon to

silicon using thin glass layer2 have been reported.

Typically Pyrex 7740 or Schott 8330 glass are

used. The Thermal Expansion Coefficient (TEC) of

these glasses match closely matches with the

TEC of silicon, resulting in low stress in the bonded

devices.

Silicon Direct Bonding (SDB) which is usually

referred to as Silicon Fusion Bonding (SFB) is used

for bonding two or more silicon wafers and is based

on the initial bonding by hydroxyl radicals present on

the silicon wafer surfaces prepared by standard RCA

clean prior to bonding3. Mechanical spacers are

placed at the edges of the wafers as in Fig.2 (a) to

maintain physical separation, so that pressing the

middle of the wafers creates an initial point contact

that originates the bond . Removing the mechanical

spacers as in Fig.2 (b) allows a single bonding wave

to propagate from the center of the wafers. The

mechanical spacers are important in establishing a

single bond front that propagates outward because

multiple bonding waves lead to warpage and gases

can be trapped in pockets formed by multiple waves,

and result in areas of poor bonding. After this pre-

bonding step, subsequent annealing is carried out at

temperatures in excess of 1000°C. During this

annealing step, the hydroxyl groups from water

molecules create Si-O-Si bond as hydrogen diffuses

away. Oxygen also diffuses into the crystal lattice to

create a bond interface that is not distinguishable from

the rest of the silicon structure. Although the high

annealing temperature involved in this process is a

drawback for some applications, the silicon fusion

bonding technique permits the formation of cavities,

as well as all- silicon, stress free bonded structures. It

has been reported4 that surface activation methods

such as argon beam etching to create a clean surface

prior to bonding result in excellent bond strengths of

10-12 MPa even when the Si-Si bonding is carried out

at room temperature.

Intermediate-layer bonding techniques involve

deposition of either metallic or glass intermediate

films prior to bonding and they are referred to as

glass-frit bonding and the eutectic bonding. The

eutectic bonding makes use of the existence of a

eutectic melting temperature which is considerably

lower than the melting point of individual constituent

elements. For gold and silicon system, the eutectic

melting point is 363°C and corresponds to a eutectic

composition of 3.16% silicon and 96.84% gold by

weight (19 % silicon and 81% gold by atomic per

cent). The eutectic bond is performed by evaporating

and plating gold on to one of the silicon wafers and

then exposing the gold to UV light just before

bonding to remove organic contaminants that

preclude gold surface contact with the second silicon

wafer into which it is bonded. To accomplish good

bond, the second silicon wafer surface preparation

must remove any oxide film that can hamper diffusion

of gold into silicon. The eutectic bonding method uses

pressure applied with the wafers held at a temperature

slightly higher than the eutectic temperature. A

detailed optimization study5 has revealed that

maximum bond strength of 18 MPa can be achieved

with the bonding temperature of 400°C and the gold

layer thickness of 1.0 µm. In the glass-frit bonding

process a thin glass layer such as lead borate is

deposited on the silicon substrate. The wafers are

then brought into contact under pressure at the

melting temperature of the glass, which is generally

< 600°C.

Fig. 2 — Silicon fusion bonding (a) Wafers placed in position

with spacers (b) Wafers are bonded by removing the mechanical

spacers and pressurizing

BHAT et al.: WAFER BONDING

313

3 MEMS Devices using Silicon Fusion Bonding

and Etching

Among the various wafer bonding methods, Silicon

Fusion Bonding (SFB) approach results in stress free

bonds with bond strength as high as that of silicon

itself. This approach has attracted wide interest for

MEMS as well as for microelectronics and has

opened up new avenues to realize complicated

structures with multiple wafer bonding along with

Deep Reactive Ion Etching (DRIE) and wet chemical

etching of silicon . We illustrate the impact of this

powerful technology for microstructures with

examples drawn from literature as well as from the

structures realized in our laboratory.

Figure 3 shows a generalized process flow reported

in the literature6 for building very tall suspended

structures made entirely from single crystal silicon

using SFB and DRIE. Figure 3(a) shows a spacer

cavity etched into a bottom wafer. A second silicon

wafer is bonded on to the cavity wafer by SFB and it

is then thinned down to the desired thickness

Fig. 3(b). This is followed by patterning as shown in

Fig. 3(c) for DRIE. The micromechanical structure

shown in Fig. 3(d) is released by etching through the

top silicon wafer by DRIE into the buried cavity.

Silicon Fusion Bonding enables increased

complexity in device design by allowing multiple

silicon wafers to be stacked on top of each other and

bonded .to each other. The complexity that can be

achieved using SFB is illustrated by a micropump7 as

shown in Fig. 4. This device is realized using four

silicon wafers, three of which have been

micromachined by wet chemical anisotropic etching

prior to bonding. This device operates by electrostatic

actuation as follows. When an attractive potential is

applied to the counter electrode, the membrane

deflects upwards, decreasing chamber pressure, thus

opening the inlet check valve and drawing fluid into

the chamber through the inlet port. When the voltage

is removed, the membrane relaxes, increasing the

chamber pressure, and forcing the fluid out of the

chamber through the outlet port.

In the above structure, the reliability of operation is

limited due to the clogging of the mechanical check

valve and due to the fatigue and failure of the moving

part in this valve. In order to overcome this problem,

valve less micropumps have been designed and

reported in the literature8. However the actuation

voltages required for the operation of the micropumps

reported in the literature were rather high in the range

of 50 to 60 V. Actuation voltages need to be low for

applications in drug delivery and drug dosage control

for biomedical applications. Figure 5 shows a

schematic structure of the micropump we have

designed for operation below 10 V. In this structure,

the inlet and outlet to the pump chamber are realized

by nozzle and diffuser type dynamic valves prepared

by etching the silicon substrate which is bonded to the

silicon membrane having the chamber cavity as

shown in the Fig. 5. When the membrane deflects

downwards due to electrostatic actuation, the ‘outlet’

marked in the figure acts as a nozzle and allows more

fluid flow out of the chamber as compared to the fluid

flow outward through the duct marked ‘inlet’ which

acts as a diffuser to this direction of flow. When the

voltage is brought down to zero, the chamber volume

increases causing a drop in its pressure, causing the

flow through the inlet (which now acts as the nozzle)

into the chamber to be more than the fluid flow out of

the chamber through the ‘outlet’ (which is now

behaving like a diffuser). Thus during one stroke

Fig. 3 — Process flow for realizing a suspended mass using SFB

and DRIE (Ref.6)

Fig. 4 — Schematic structure of the micropump with valves

(Ref.7)

INDIAN J PURE & APPL PHYS, VOL 45, APRIL 2007

314

cycle, the pump delivers a net fluid corresponding to

the stroke volume. The pump - chamber height in our

design is reduced to a small value of 0.2 µm choosing

the lateral dimensions of the chamber to be

5 mm×5 mm. This gives rise to a stroke volume of 0.5

nano-liters and a flow rate of 1.5 micro-liters/minutes

when actuated by a 50 Hz, 6V pulse voltage. The

structure has been designed and fabricated in our

laboratory to show the proof of concept. Further study

is in progress to fully demonstrate the working of the

Micropump with fluid flow.

4 MOS Integrated Pressure Sensors on a

Monolithic Chip using Silicon Fusion Bonding

and SOI Approach One of the many important applications of silicon

fusion bonding is the realization of Silicon on

Insulator (SOI) wafers which have received

considerable attention for microelectronics

applications. In this section we show that the SOI

approach is very attractive to integrate MEMS devices

and electronics on the same SOI wafer. In this

approach, the thickness of the SOI layer is chosen

from the requirements of the mechanical

considerations such as the pressure sensor membrane,

and the doping concentration of the SOI layer is

decided as per the requirements of the MOSFET

threshold voltage for the electronics portion of the

integrated sensor. We have designed and processed

this integrated pressure sensor in three stages as

follows: (a) First the polysilicon piezoresistive

pressure sensors were designed for operation up to a

maximum pressure of 15 bar, and fabricated on SOI

wafers prepared in-house in our laboratory by SFB

and back etching the top wafer to the required

thickness (b) Next the common source MOSFET

differential amplifier has been designed for a

differential gain of 5 and fabricated on bulk silicon

wafers to standardize the process so that it can be

made compatible with the process steps of the

pressure sensor. (c) Once the processes (a) and (b)

were stabilized with reasonably good results, the

integrated sensor was designed with optimized

minimum number of process steps, fabricated on SOI

wafers, packaged and tested.

The schematic cross-section of the polycrystalline

silicon piezoresitive pressure sensor integrated with

MOSFET differential amplifier fabricated in our

laboratory on SOI wafer is shown in Fig.6. It may be

noted that the piezoresistors are laid out on the oxide

grown on the SOI membrane, realized by KOH

etching from the backside of the SOI wafer. The

buried oxide of the SOI wafer serves as an etch stop

during the anisotropic etching process. The

electronics portion of the integrated sensor is laid out

on the SOI layer outside the membrane region. The

circuit diagram of the integrated pressure sensor is

shown in the Fig. 7. The sensor portion consists of

four polysilicon piezoresistors arranged in the form of

a Wheatstone bridge on the oxide grown on the

membrane and the output of the Wheatstone bridge is

connected to the input of the common source

MOSFET differential amplifier.

Fig. 5 — Schematic of a valve less Micropump fabricated using

SFB and wet etching

Fig. 6 — Schematic cross sectional view of MOSFET integrated

pressure sensor

Fig. 7 — Circuit diagram of the pressure sensor integrated with

MOSFET amplifier on an SOI wafer

BHAT et al.: WAFER BONDING

315

Fig. 8 — Layout of four piezoresistors for polysilicon pressure

sensor

Polysilicon piezoresistors are used for the pressure

sensor because, as the polysilicon piezoresistors are

laid out on the oxide, excellent isolation between the

resistors is achieved. The doping concentration of the

polysilicon resistors is adjusted by ion implantation of

appropriate boron dose to minimize the temperature

coefficient of resistance of these resistors.

The aspect ratio of the membrane is designed to be

500×1000 µm and the polysilicon piezoresistors are

laid out as shown in Fig. 8 to achieve the best

sensitivity for the membrane thickness of 11 µm

which is same as the thickness of the SOI layer. When

a pressure is applied over the membrane the resistors

R1 and R3 located at the edges of the membrane

experience longitudinal tensile stress and the resistors

R2 and R4 located near the center of the membrane

experience longitudinal compressive stress. This will

result in an increase in the resistance of the resistors

R1 and R3 and decrease in resistance of the resistors

R2 and R4. This imbalances the Wheatstone bridge

and hence the output voltage changes with applied

pressure. The offset voltage (output voltage when the

differential pressure is zero) of the pressure sensor

fabricated using these masks are small since the

contact resistance between the resistor and the metal

is equal for all the four resistors.

The composite mask layout of the integrated

pressure sensor designed and fabricated in our

laboratory is shown in Fig. 9. The differential

amplifier has been designed using SPICE simulation

by considering 500 mV threshold voltages for the

MOSFET with 10 V supply to the drain. The drain

and source resistance values have been designed by

simulation and found to be 10 kΩ and 4 kΩ

respectively for achieving a differential voltage gain

of 5. The polysilicon resistors of the amplifier circuit

are processed simultaneously along with the process

steps of the piezoresistors so as to minimize the

number of photolithography and process steps. After

realizing the polysilicon piezoresistors and the

amplifier resistors, the MOSFET amplifier portion is

processed. During these process steps of source drain

diffusion etc, the resistor regions are protected with

PECVD silicon dioxide. After completing all the

process steps, contact windows are opened in the

regions shown in Fig. 9. This is followed by

aluminium metal evaporation and patterning as in

Fig. 9. The wafer is diced and then packaged in a

TO39 header.

A photograph of the integrated pressure sensor

mounted on the header and wire bonded to the posts is

shown in Fig.10(a) and the same device with a cap

welded in position is shown in Fig.10(b). The

packaged MOS integrated pressure sensor is mounted

in a specially fabricated jig for the purpose of testing

and characterizing the device and pressure is applied

from a nitrogen cylinder. The applied pressure is

Fig.9 Composite mask layout of MOSFET integrated pressure

sensor

Fig. 10 — Photograph of the integrated pressures sensor chip

mounted on a header. (a) Without the cap and (b) With the cap

having a pressure port hole welded on to the header

INDIAN J PURE & APPL PHYS, VOL 45, APRIL 2007

316

measured using a digital pressure gauge. An input of

10 V is given to both the sensor and the drain supply

of the differential amplifier. The measured voltages at

the sensor output and differential amplifier output up

to 7 bar pressure are shown in Fig. 11. The offset

voltage (output voltage when the differential pressure

is zero) at the integrated sensor output is nullified by

connecting an external resistor across one of the drain

resistors of the differential amplifier. Sensitivity of

316 mV per bar with the on chip amplifier gain of 4.5

has been achieved in these devices. The output at the

sensor and amplifier are linear up to 7 bar pressure

with a maximum non linearity of 1%.

5 Summary and Conclusions In this paper we have shown that the silicon Fusion

Bonding is a powerful technique when used along

with either DRIE or wet chemical etching methods.

From the results available in the literature it is shown

that complicated 3-D structures such as micropump

with micromachined multilayer silicon wafers and

very tall suspended structures made entirely from

single crystal silicon can be realized with this

approach. It is also shown from our own experiments

that Integration of Piezoresistive pressure sensors

with electronics circuits can be easily achieved on a

monolithic chip using Silicon on Insulator (SOI)

wafers which are realized with Silicon Fusion

Bonding and Etch Back technique. The pressure

sensors thus integrated with MOSFET differential

amplifier have been packaged, tested and

characterized. Excellent linearity with a maximum

nonlinearity of 1% has been seen in these devices. It

is concluded that the SOI approach using silicon

wafer bonding holds tremendous promise for

integration of mechanical sensor s and actuators with

electronics circuits.

References 1 Mirza A R & Aydon A A, Solid State Technology, (1999) 72.

2 Weichel Steen, Reus Roger de & Lindahl Michael, Sensors &

Actuators, A70 (1998) 179.

3 Takao Abe, Tokio Takeia, Uchiyama Tsuo, Yoshizawa Katsuo

& N Yasuaki, Japanese Journal; of Applied Physics, 29 (1990)

2311.

4 Takagi Hideki, Maeda Ryutaro, Ryong Chang Teak & Suga

Tadatomo, Sensors & Actuators, A70 (1998) 164.

5 Nai S M L, Wei J, Lim P C & Wong C K, Proceedings of the

Electronics Packaging Technology Conference, (2003) 119.

6 Klaasen E H, Petersen K, Noworolski J M, Logan J, Maluf N

I, Brown J, Storment C, McCulley W and Kovacs G T A,

Sensors & Actuators, A52 (1996) 132.

7 Zengerle R, Richter A & Sandmair H, Proc. IEEE Micro

Electro Mechanical System Workshop, , Travemunde,

Germany, (1992) 19.

8 Gerlach Torsten & Wurmus Helmut, Sensors & Actuators,

A50 (1995) 135.

Fig. 11 — Pressure versus output voltage of the MOSFET

integrated pressure sensor