VLSI Project With Spice and VHDL

7/27/2019 VLSI Project With Spice and VHDL

http://slidepdf.com/reader/full/vlsi-project-with-spice-and-vhdl 1/26

1

ECE559 Project #1

Methodology for Designing a CMOS

VLSI ALU Chip

XIAOLAN ZHANG

ALI EMIR BAYRAKTAR

TASNIM MORBIWALA



2

ABSTRACT

In this project our goal was to design an Arithmetic Logic Unit (ALU) which performs four basic

operations according to selective inputs. The ALU contains 4 basic cells; AND, OR, NOT and D-Flip

Flop. The first step in the design was to make the basic cells using TannerEDA Software Tools. After

designing the basic cells, the “Synopsys Library” file had been generated. This file defines the functions

of the cells which will be further used to perform a standard cell placement and routing. The next step

was to generate the VHDL code which defines the logic operations that will be performed by the ALU.

The final step would be to link the components of the project like the standard cells, Library file and

VHDL code to perform routing and standard cell placement.



3

INDEX

1. MISSIONS........................................................................................................................................... 5

2. STEPS OVERVIEW............................................................................................................................ 5

3. DETAILED STEPS ............................................................................................................................. 7

3.1 Design Cell Circuit .................................................................................................................... 7

3.1.1 Parameter Calculation ..................................................................................................... 8

3.1.2 Schematics ...................................................................................................................... 8

3.1.3 Simulation Result.......................................................................................................... 13

3.2 Create Synopsis Library........................................................................................................... 13

3.2.1 Decide Technology ....................................................................................................... 14

3.2.2 Declare Cells ................................................................................................................. 14

3.3 Design ALU in VHDL............................................................................................................. 15

3.3.1 Programming................................................................................................................. 15

3.3.2 Simulation ..................................................................................................................... 15

3.4 Create Tanner Cell Pad Library............................................................................................... 16

3.4.1 Environment Settings.................................................................................................... 16

3.4.2 Design ........................................................................................................................... 17

3.4.3 Design Rule Check Settings.......................................................................................... 18

3.4.4 Standard Cells ............................................................................................................... 18

3.5 Synthesize................................................................................................................................ 19

3.5.1 Setup Tools ................................................................................................................... 20

3.5.2 Library Compilation...................................................................................................... 20

3.5.3 VHDL Compilation....................................................................................................... 20

3.5.4 Synthesis Result ............................................................................................................ 20



4

3.6 Route in Tanner ....................................................................................................................... 20

3.6.1 Create New Layout and Setup....................................................................................... 21

3.6.2 Place and Route Setup and Core Generate.................................................................... 22

4. FINAL WORK................................................................................................................................... 25

5. SUMMARY....................................................................................................................................... 25

6. REFERENCES .................................................................................................................................. 26



5

1. MISSIONSIn this project our mission is to design a complete, ready to manufacture ALU that meets certain

conditions provided by the process requirements and performs a dedicated operation. The design will

be done using EDA Tanner Software and it has to compatible with a list of industry standards. All the

results will be verified by using either the inside check tools of Tanner or other simulation software like

PSPICE. The overall mission can be summarized as the generation of the GDS file that includes all the

data to turn a pure silicon wafer in to a semi-conductor digital device.

2. STEPS OVERVIEW

The first step of the project is to design the standard cell library components. These components are a

NOT Gate, an OR Gate, an AND Gate and finally a D-Flip Flop Gate with an asynchronous reset. The

gates have to meet the specification that the rise time and the fall time are 5ns given a 5pF load. The

important MOSFET design parameters like Vt, Ids etc. are also documented and any unknown values

like Na will be chosen from reasonable values from the text book. For this part of the project, the use of

simulation software is recommended and we will use PSPICE for the simulation of the standard cells.

The second step is to design the Synopsys Library file that support Synopsys synthesis tools. The library

holds the technical characteristics and schematic symbols. The content of the library is strong relation

with the precise of the synthesis. Adding known design values about each cell to the library improves

the synthesis. The library has to be compiled before it is usable.

The third step is to write a VHDL code describing the logic operation of the ALU. The ALU performs

four basic operations and which operation to be performed is decided by four selective inputs. Whenthe inputs are “00” the ALU will perform the operation (A+B). In the case of a “01” input, the

performed operation will be (A-B). The operation (A AND B) will be performed if the inputs are “10”

and finally if the inputs are “11” the resulting operation will be (A OR B).

The results of the first three missions are to be used for the fourth mission. This step utilizes the

standard cell library components, takes the specifications and characteristics of the cells from the

compiled library, reads the operational structure of the ALU from the compiled VHDL net file and



6

performs a standard cell placement and routing operation using TannerEDA tools. The result of this

mission is GDS file that contains all the necessary information for the production of the ALU.

The submission of a report documenting all of our work and including our experiences and discussions

completes the mission for this project. This paper will include the detailed explanations of all steps

gone through the process.

Figure 1 Steps overview

VHDL(*.vhd)

Synopsys

Synthesis Simulation

Library (*.db)

Synopsys

Library (*.lib)

EDIF, Netlist (*.edf)

TannerEDA

(Place & Route) Standard Cell

Librar *.tdb

Cell core (*.tdb)

Specifications



7

3. DETAILED STEPS

3.1 Design Cell Circuit

Our first task is to design the standard cells. The best way to do is to use simulation software which

enables you to determine the required circuit characteristics to meet the design criteria. For this project

we have utilized the PSPICE circuit simulator. Before we proceed to the design of the circuit we have

created PSPICE models and simulated them by submitting the required parameters. The powerful

analysis tools of PSPICE have given us the opportunity to make required corrections over our circuits

and verify our results. As we have used PSPICE in some other steps of the project too, we want to

provide some information about this process.

PSPICE is powerful circuit simulator software which enables you to model your devices according to

your specifications. Each circuit element has a model which is determined by the process and

technology used to manufacture the circuit element. Additional to the model, each device has also some

attribute values which give specific information about one discrete part only. For simple circuit devices

like resistors and capacitors we haven’t provided any models other than the default models. For this

parts we have just given the attribute values; the value of the resistances and capacitances. We have

started to use the real strength of PSPICE by modeling the transistors. Being able to use our own model

has enabled us to specify very critical data like the mobility of carriers, threshold voltage of the gate

and etc. PSPICE has three levels of models. The first level uses the linear and quadratic equations to

simulate the circuit which is very close to hand calculations. The second level provides more complex

equations and more values are involved with the calculation. But the most precise results are obtained

using the Level-3. The Level-3 model works with empiric equations and if we consider the results that

it provides we can say it is like taking direct results from a virtual circuit. For getting the best results we

can, we have preferred using the Level-3 model. In our case, we have one model for the NMOS

transistors and another model for the PMOS transistors. On the other hand each device has its own

attributes which were in our case the width and length of the gate. Choosing the same model for the all

transistors has reduced our unknown variables into 2, the W and L. So, by providing some feedback

from the simulation results has guided us in a few steps what the ideal W and L values should be. This

simulation policy has also provided us consistency and flexibility for the design process.



8

3.1.1 Parameter Calculation

Before we started to design our circuits we had to decide on our design parameters. The mission

criterion doesn’t provide any parameter. We had to calculate the parameters and we have also chosen

reasonable values for some parameters that were unknown. All these calculated and accepted values for

NMOS and PMOS transistor have built our simulation models. A complete list and calculation of all

design parameters are given in below.

NMOS PMOS Unit Value

KP 8 *10E-5 2.5 *10E-5 A/V2

Transconduc.

UO 500 180 cm2/V*s Mobility

NSUB 10E16 10E16 cm-3 Doping

TOX 2 *10E-8 2 *10E-8 meter Oxide Thick.

LAMBDA 0.01 0.01 V-1 Channel Length

LD 0.1*E-6 0.1*E-6 meter Lateral

GAMMA 0.337 0.337 V1/2

Bulk Threshold

PHI 0.6953 0.6953 V Surface Inv. Pot

Table 1 Process Parameters for PSpice

Єsi = 1.06 10-12 F/cm Єox =3.9 8.85 10-14 F/cm

GAMMA γ = (1/ Cox) (2q Єsi NA) ½ = 0.337 V ½

Cox= 1.726 10-7 F/cm2

PHI φs = 2 φ b φ b = 0.3476 V PHI φs= 0.6953 V

3.1.2 Schematics

After we had the required model parameters we have built the circuit schematics. The schematic of

PSPICE is like a virtual breadboard where you can place the parts, run the circuit and see the results.

All voltage and current values are displayed on the circuit.



9

3.1.2.1 Inverter

The first cell that we have built is the inverter. For the inverter we have implemented one PMOS and

one NMOS device. For the input signal we have used a waveform generator which gives a very close

output to a step function. First we have tested our device without any capacitive load. This simulation

has enabled us to measure the signal delay from the input to the output. After that a capacitive load of

5pF has been connected to the output. A transient analysis has been performed. Our initial values for

the W and L of the transistors were as followed: NMOS W=5u L=2u PMOS W=5u L=1u The

simulation results of these values didn’t meet our criteria so we increased the values using the try-error

method. Our first values that provided acceptable results were as NMOS W=6u L=1u PMOS W=16u

L=1u. We have used these values until we started to use TannerEDA. The setup of TannerEDA

software forced us to bring our W and L values to the multiplicands of 0.3u, so we had to change to

values for the second time. Our new values were NMOS W=6.6u L=0.9u PMOS W=16.8u L=0.9u.

With the given values our inverter circuit met the design specifications. The rise time was tr =4.96ns and

the fall time was tf =4.23ns. However we had to change these values for the last again because of the

TannerEDA software which requires perfect consistency between standard cells. The values were not

good enough for the D-Flip Flop. We had bigger transistor for it but TannerEDA forced us to use the

same transistor size in each of the cells. As we had to make our transistor bigger than required our final

results were far beyond of the design specifications. Our final values followed as NMOS W=12u

L=0.9u PMOS W=27.6u L=0.9u. These values have been our final results and have been used in all of

the cells. In other words the D-Flip Flop was one of the parameters that determined the geometry of our

transistors. Table 2 gives an overview of the values that have been tried and why they had to be

changed.

NMOS PMOS Criteria

W L W L Delay TannerEDA

Values #1 5u 2u 5u 1u X X

Values #2 6u 1u 16u 1u √ X

Values #3 6.6u 0.9u 16.8u 0.9u √ X



10

Values #4 12u 0.9u 27.6u 0.9u √ √

Table 2 W/L ratio for transistors in PSpice

Using our final values we have built the schematics and simulated it on PSPICE. The rise and fall time

values for the inverter are given as follows: the rise time t r =3.09ns the fall time tf =2.70ns. The circuit

schematic of the inverter is given in Figure 2.

Figure 2 The Schematic of the Inverter in PSpice

3.1.2.2 AND Gate

The second cell that we have built is the AND gate. Also for this gate we have followed the same steps.

The AND gate consists of 6 transistors in total. 3 of them are NMOS transistors and the rest is PMOS

transistors. For this design we have actually implemented a NAND gate and connected it in serial with

an inverter which gave us an AND gate. This is a good reason to understand why manufacturers

produce NAND and NOR gates instead of AND and NOR gates. For the input we have used the same

function generator of the first simulation. First we have checked the circuit without any load connected



11

for the functionality. After this test is passed we connected a load of 5pF and measured the rise and fall

times. Figure 3 shows the schematic of the AND gate.

Figure 3 The schematic of AND gate in PSpice



12

Figure 4 The schematic of OR Gate in PSpice

3.1.2.3 OR Gate

The third cell that we have designed is the OR gate. The procedure of the OR gate was very similar to

the AND gate. The only difference was that PMOS transistors were connected in series and the NMOS

transistors were connected in parallel. Again in this design we have implemented a NOR gate and

connected it in serial with an inverter which resulted in an OR gate. Our input waveform generator was

the same of the previous simulations. Figure 4 is the schematic of the OR gate.

D Flip Flop

The most difficult part of the design was the D- Flip Flop. This cell consists of 20 transistors in total

and the PSPICE allows us to simulate to circuit that include up to ten transistors only. As our design

has a master-slave combination we have divided our circuit into two parts which were perfectly

symmetrical. We have simulated the half-circuit and we have added the delays in order to calculate the

delay of the complete circuit. The design of the D-Flip Flop has been the main factor over the whole

process. It was our last cell design but as TannerEDA wanted all of the cells to be constructed with the

same size of transistors, we had to revise our previous cells according to the design of the D-Flip Flop.



13

The simulation results of the D-Flip Flop was just in the limits with bigger transistors, on the other

hand the other cells performed much better than required. Figure 5 is the schematic of our half-circuit

D- Flip Flop on PSPICE.

Figure 5 The schematic of D Flip Flop in PSpice

3.1.3 Simulation Resul t

With the design of all the gates we had all the required information and data to build our standard cells

using the TannerEDA software. We have verified our results on PSPICE software and they were all

consistent. Table 3 provides an overview of our simulation results.

INVERTER AND OR D-FLIP FLOP

tr [rise time] 3.09ns 3.13ns 3.27ns 6.01ns

tf [fall time] 2.70ns 2.71ns 2.65ns 2.6ns

Table 3 Rise and Fall Times for Standard Cells

3.2 Create Synopsis Library

The Synopsys library is a text file which describes the standard cell library components. It is created to

support Synopsys synthesis tools by providing data about values that are used to synthesize the cells.



14

The library development procedure includes the Library description (.lib file), the compilation of this

file and obtaining the library (.db file). The library description file has its own programming syntax to

be followed. In our tries we have seen that most of the errors occur because of the syntax errors.

3.2.1 Decide Technology The first thing to design the library is to decide on the technology. There are two possibilities, CMOS

and FPGA. CMOS is the default technology, so we didn’t define it. The next step is to decide on a

series of default values. All of these default values are about timing and delay constraints and they are

only used if for a certain cell the according value is not defined. In order to improve the synthesis the

designer can add as many known values as he wants. In our cases for the cells, we have defined the

following values: intrinsic rise, intrinsic fall, rise resistance, fall resistance, slope rise, slope fall. The

designer has also to specify what the unit values will be; the time unit is 1ns, the voltage unit is 1V, the

current unit is 1uA, etc. The ranges for the input and output voltages are also design parameters. The

designer can define a set of operating conditions to test the compatibility with different environments.

The environments that we defined are Commercial, Industrial and Military. After the setup of all these

environment variables we can declare our cells.

3.2.2 Declare Cells For the declaration of the core cells we have to obtain several data about the cell. The easiest way is to

use the simulation software PSPICE. We have obtained the timing values for our cells from the

simulation results of PSPICE. If the designer use the parts from another company or designer it is

possible to involve data referring to the data sheets of the manufacturer. Another important parameter

to be declared is the area of the cell. Its default value is zero but defining it as zero makes the routing

process more difficult. The area parameter is used to provide information to the routing software so it

can decide what the best place to locate a cell is. The most important parameters on the cells are the pins. For every pin of the cell we have to declare the direction and the timing information. The direction

can be either input or output. If the direction is input, the declaration is simpler because it contains just

the capacitance value. On the other hand if the direction is output we have to declare what the output

function is. And according to the pins that are involved with the output function, we have to declare

timing information related with each pin. A typical cell declaration in the cell library looks like this:

cell(AND2)

{



15

area : 2;

pin(A)

{

direction : input;

capacitance :1;

}

pin(Z)

{

direction : output;

function : “A*B”;

}

timing(){

……………

related_pin : “A B”;

}

}

3.3 Design ALU in VHDL

3.3.1 Programming

The VHDL code defines the logic operations which will be performed by the ALU. We had to design

our VHDL code as per the following design given to us for the ALU:

ALU option “00” is “result<=A + B “

ALU option “01” is “result<=A - B “

ALU option “10” is “result<=A AND B “

ALU option “11” is “result<=A OR B “

The code uses basically variables like:

1. “a”, “b” for defining the inputs

2. “se” for select lines

3. “clock” and “reset” lines

4. “f” which is an output vector.

3.3.2 Simulation

The simulation of the VHDL code can be done using either “Model Sim” or the “Synopsis” tool. The

commands used in both cases to run the files would be:



16

For Model Sim:- vcom -93 <filename.vhd>

For Synopsis:- vhdlan<filename.vhd>

In order to check that our design works as per the functions, which have been designed, we “force” thevalues of the above-defined variables by using the “force” command.

For example “To force the Inputs”

Force a 0000 0000 0 , 0000 0001 1 , 0000 0010 3 , 0000 0011 5

The process can be briefly described as :

5. go to Model Sim

6. go to “ design”

7. “Load Design”

8. go to “View” menu

9. go to “Source”, “Signals”, “List”, “Process”, ”Wave”

The above process will open graphical windows where we can view each signal. These signals are

mainly the “clock”, “reset”, “a”, “b”, “se” and “f”.

3.4 Create Tanner Cell Pad LibraryAfter we have verified our theoretical values on PSPICE we had to design our cells on TannerEDA.

This powerful software integrates layout editing, verification, and place & route in one powerful suite

of tools, so designers can quickly and easily maneuver through the entire design flow. In general it has

an easy to use interface but in addition to that it also requires very precise setups and rules in order to

obtain results. It is not a “minimum result with minimum effort” kind of software; it gives professional

results with very much effort. [2]

3.4.1 Environment Settings

The first step of designing a cell in TannerEDA is to setup the environment. Every design files contains

basic information such as a layer list, technology settings and model specific options SPR (Standard

Placement & Routing), DRC (Design Rule Check) and Extract. The information is stored in a file with

a *.tdb extension which stands for Tanner Database. With this setup information the L-Edit is ready to

design the cell. [2]



17

The setup file wants you to give certain data like Technology name, units, internal units (Lambda) and

its real equivalent. All required information is given using the “Setup Design” window. Besides of

important technology information, it is also possible to determine display features like Grid, Selection

and Drawing. Figure 6 shows a sample Setup Design window from our design. [2]

Figure 6 L-Edit Setup Design Window

3.4.2 Design After the setup of environment is completed we have to specify some rules for our cell rules. The cells

in a standard library must meet certain constraints of dimensions and port positions. In general there are

two types of cells; standard cells and pad cells. Each kind of cells has its own design rules. The rules

for the standard cells are as follows:

1. Abutment ports must have the same height.

2. Power port has height 8, width 0, must against the abutment, all at metal1 layer.

3. Signal port has height 0, and the width must be larger than 3, also ported to abutment if possible,

all at the same layer (metal2), and the name of ports are consistent with those in the synopsis



18

library.

4. Cross port marks in some cell where can be crossed vertically. This feature is used to minimize the

cell size during routing

5. The power port, well and p/n select are the same height and the same horizontal position related to

the abutment.

3.4.3 Design Rule Check Setti ngs The next step is to determine what DRC (Design Rule Check) settings will be. DRC is used to examine

the design whether it meets the specified requirements of the process. All of these rules are distances

given in lambda. The designer is free to choose the rules to be enabled or disabled, but in general

increased number of rules improves the overall quality of the design but makes it more difficult to deal

with. The design rules are listed in a text file with .rul extension. Our ALU_lib.rul file consists of

almost 100 rules and our design passed of this rules that were enabled. General rules are listed as

follows:

1. N well rules

2. Active rules

3. Poly rules

4. N/P select rules

5. Active contact rules

6. Metal 1 rules

7. Via1 rules

8. Metal 2 rules

3.4.4 Standard Cells After all these steps we can design our cells. We have four basic cells to design; Inverter, AND gate,OR gate and finally the D-Flip Flop. Besides, there are cells for routing blocks and channels. Extra cells

TIEHIGH and TIELOW are used for connect VDD, GND between channels. The ROWCROSSER

provides extra channel to go across a block.

Even the design of a simple transistor requires many detailed steps, so the explanation of through which

steps we did go is beyond the content of this paper. On the other hand there are some rules that we have

considered during the design process. First of all our goal was to make the cells as small as possible.



19

Some times we had to change the regular layout of the cell like flipping it. It is also another important

point that we have tried to combine as many areas as we can; i.e. the source and drains of the transistors.

We have also used Metal2 layers to avoid excessive routing pads, so using an additional layer made our

cells more compact. It was another issue to connect external signals to the ports. The solution that we

found was to placing as much signaling ports as we can. This increased the number of our possible

connection locations and enabled us to keep the size of the cell smaller. Considering all of these design

policies we have designed our four basic cells.

3.5 Synthesize

After we declared our library we have to compile it before it is usable. The library compilation is

performed by a program provided by Synopsys and it is called Library Compiler. For the compilation of

the library we have used the executable command sets that are already given but subject to be changed.

The first file to be changed was the synopsys_dc.setup file. This file specifies where and under which

name should be target library and link library saved. This information is given by the attributes set

target_library and set link_library. The second file that we had to change was the dc_shell.ioc. Again in

this file we have made only minor changes. First we have declared the name of our db file and we have

also specified what the name of the resulting EDIF file would be. The third file that we had was

dc_shell.makelib_db. We haven’t done any changes on this file. It was actually only two lines of source

code and it was consistent with our files. All of this three files consist of several lines of commands and

all of this commands have to be executed to compile the library and VHDL file. If we think that we had

to do this many times it would be quite inefficient to type the same commands again and again. In order

to make things easier we have utilized to scripts that executes these all commands by giving a single

command. These scripts were the syn_tool_alu11 and lib_tool_alu11. Again these two files were

consistent with our designs and file names, so we just executed tham without making any changes. The

lib_tool_alu11 file executed the commands to copmpile the library and the syn_tool_alu11 file executed

the commands to make the synchronization between the standard cell library and VHDL design. The

After all these steps the result of the library compilation is Tanner Database file with the file extension

*.db. After that we executed the command which generates an EDIF file. The EDIF file combines the

data from the compiled library with the data from the VHDL file; we can also say that it synchronizes

the structure of the circuit with the characteristics of the circuit elements. Figure 6 shows an overview



20

of the entire library compilation process and further more the cell placement and routing process.

3.5.1 Setup Tools

1. Pre execute synopsys environment setup commands

source /export/home1/mknieser/do_synopsys

2. change dc_shell.makelib_db

3. creat lib_tool_alu11

4. chang .synopsys_dc.setup

5. creat dc_shell.ioc

6. creat syn_tool_alu11

3.5.2 L ibrary Compilation

lib_tool_alu11 | tee liboutput

3.5.3 VHDL Compilation

syn_tool_alu11 | tee output.

3.5.4 Synthesis Result Library output: ALU11.db

Synthesis output: ALU11_compile.edf

3.6 Route in Tanner

The cell placement and routing part of this project is the time to combine all of the previous work

and generate something that is ready to produce and use. For the routing we have used the standard

placement and routing tool of TannerEDA. Using this tool makes the entire process fully automated.

The required netlist data is provided by the EDIF file that was a result of the Synopsys synthesis. To run

the SPR (Standard Cell Place and Route) tool, three files are needed. These are a design file *.tdb, a

netlist file *.edf and finally the standard cell library that has been created. As we had all these three files

ready went to the placement and routing process.



21

3.6.1 Create New Layout and Setup In this section what we have done is basically just to follow the list that was submitted. First of all

we have created a new layout. In this step we have chosen our *.tdb file as the new layout process. This

step is shown in Figure 7. After that we have initialized the place and route setup. In this step we had to

specify our standard cell library and netlist file. Again in the same window, as the power signal and

ground signal has to be consistent with the standard cell library, we have changed them to VDD and

GND respectively. Before we initialize the setup we usually ran the mapping table to map synopsis

library cells’ port to the name of tanner cells’ port. This is quite useful if you make any changes in your

cell library and run the SPR again. In some cases TannerEDA software just requires this step to make

the new changes effective. After this step we are ready to initialize the setup.

Figure 7 Create new layout consistent with library



22

Figure 8 New Layout Window

3.6.2 Place and Route Setup and Core Generate Our next step is to run the Core Setup. The Core Setup window enables you to define TIEHIGH,

TIELOW, ABUT, CROSS and ROWCROSSER parameters and again all these values have to be

consistent with the cell library. The Core Setup also allows you to choose how many layers to use for

the routing. Our choice was 2-layer routing. After that we have to run the Padframe Setup. In the

Pedframe Setup we haven’t done any major changes, we have just changed the name of the chip cell to

ALU. This window is shown in Figure 8. After this final we are to finalize the Place and Route process.

We have to mention that TannerEDA software has some unwritten rules like: You have to save the

current work just before starting the placement; otherwise most probably the software crashes. If there

is no error in the design and everything works well it is time to see the result. The software also

generates a summary file which gives information about the size of the cell, number of parts and etc. In

other words, if the previous steps are strong enough the placement and routing process is quite straight-



23

forward. On the other hand we have to admit that we had to make about 100 tries before we could get

the results. Most of the failures were due to being unfamiliar with the software. There is an optional

final step which enables you to rescale the cell proportionally. Using this tool it is possible to make

cells smaller but you have to make sure that the manufacturer supports techniques for slim wires. [2]

Figure 9 SPR Core Setup General



24

Figure 10 SPR Core Setup Layer



25

Figure 11 SPR Pad Route Setup General

After this step our project is completed. The result of our final setup is ALU.tdb file, by using this we

can generate a GDS file which includes all the required information to produce the ALU implemented

on a semi-conductor chip.. Although the entire process has been quite tedious being able to see solid

results is a challenging experience.

4. FINAL WORK

Below are the pin map from left top corner counter clockwise.

Pin Signal Pin Signal Pin Signal Pin Signal

0 VDD 8 se_0 16 f_2 24 b_0

1 b_5 9 f_3 17 f_6 25 b_4

2 b_1 10 f_1 18 se_1 26 a_3

3 b_3 11 f_5 19 reset 27 a_5

4 b_7 12 f_4 20 a_4 28 a_6

5 a_0 13 f_0 21 b_6 29 a_7

6 a_2 14 clock 22 b_2

7 f_7 15 GND 23 a_1

Table 4 Pin Map of Core Cell

5. SUMMARY

This project has been very useful to have a good understanding of the entire production process of a

semi-conductor chip; from the initial hand calculations to the final complete design. We have started

with easy to deal calculations and implemented them on the simulation software. Even in this first step

we had many errors, but being able to find and correct them has improved our understanding. We have

worked with software that we had previous experience on them, like PSPICE and VHDL. On the other

hand our work with the TannerEDA software was probably the most important section of this project.

This software is one of the industry standards and being able to use it efficiently will be a very



26

important reference for future work. Most probably we haven’t used most of the powerful features of

this software, but it’s certain that its basic working principle is very clear now.

Finally, we want to mention our special thanks to Dr. Michael Knieser for his endless helps and

corrections during the entire project.

6. REFERENCES

[1] Handouts given by Dr. Michael Knieser

[2] L-Edit User Guide L-Edit ProVersion 10.1

[3] VHDL Programming by Example, Douglas L. Perry, 2002 McGraw-Hill

[4] PRINCIPLES OF CMOS VLSI DESIGN, Weste & Eshraghian, 1992 Addison-Wesley

[5] CMOS DIGITAL INTEGRATED CIRCUITS, Kang & Leblebici, 1996 McGraw-Hill

Documents

VLSI Project With Spice and VHDL