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1 VLSI Design Styles Basic Concepts in VLSI Ph sical Basic Concepts in VLSI Physical Design Automation

VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Page 1: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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VLSI Design Styles

Basic Concepts in VLSI Ph sicalBasic Concepts in VLSI Physical Design Automation

Page 2: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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VLSI Design Cycle

• Large number of devices

• Optimization requirementsSystem

S ifi ti• Optimization requirements for high performance

• Time-to-market competition

• Cost

Specifications

Manual Automation

3

Chip

VLSI Design Cycle (contd.)

1. System specification

2 Functional design2. Functional design

3. Logic design

4. Circuit design

5. Physical design

6. Design verification

7 Fabrication

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7. Fabrication

8. Packaging, testing, and debugging

Page 3: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Physical Design

• Converts a circuit description into a geometric descriptiondescription.

– This description is used for fabrication of the chip.

• Basic steps in the physical design cycle:1. Partitioning

2. Floorplanning and placement

3. Routing

4 Compaction

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4. Compaction

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Page 4: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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n-channel Transistor

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n-channel Transistor Operation

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Page 5: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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n-channel Transistor Layout

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p-channel MOS Transistor

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Page 6: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Fabrication Layers

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MOS Transistor Behavior

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Page 7: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Summary of VLSI Layers

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VLSI Fabrication

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Page 8: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Silicon Wafer

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General Design Rules

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Page 9: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Types of Fabrication Errors

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Width/Spacing Rules (MOSIS)

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Page 10: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Poly-Diffusion Interaction

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Contacts

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Page 11: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Contact Spacing

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M2 Contact (Via)

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Page 12: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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CMOS Layout Example

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Stick Diagrams

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Page 13: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Static CMOS Inverter

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Static CMOS NAND Gate

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Page 14: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Static CMOS NOR Gate

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Static CMOS Design :: General Rule

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Page 15: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Simple Static CMOS Design Example

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Static CMOS Design Example Layout

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Page 16: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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VLSI Design Styles

• Programmable Logic Devices– Programmable Logic Device (PLD)

– Field Programmable Gate Array (FPGA)

– Gate Array

• Standard Cell (Semi-Custom Design)

• Full-Custom Design

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Field Programmable Gate ArrayField Programmable Gate Array (FPGA)

Page 17: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Introduction

• User / Field Programmability.

A f l i ll t d i ti h l• Array of logic cells connected via routing channels.

• Different types of cells:– Special I/O cells.

– Logic cells.• Mainly lookup tables (LUT) with associated registers.

• Interconnection between cells:– Using SRAM based switches.

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– Using antifuse elements.

Xilinx XC4000 Architecture

CLB CLB

Switch

SlewRate

Control

PassivePull-Up,

Pull-Down

Vcc

CLB CLB

Matrix

ProgrammableInterconnect I/O Blocks (IOBs)

D Q

Delay

OutputBuffer

InputBuffer

Q D

Pad

S/RControl

G4

C4C1 C2 C3

H1 DIN S/R EC

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ConfigurableLogic Blocks (CLBs)

D QSD

RDEC

D QSD

RD

EC

S/RControl

1

1

F'

G'

H'

DIN

F'

G'

H'

DIN

F'

G'

H'

H'

HFunc.Gen.

GFunc.Gen.

FFunc.Gen.

G4G3G2G1

F4F3F2F1

K

Y

X

Page 18: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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XC4000E Configurable Logic Blocks

S/R

C4C1 C2 C3

H1 DIN S/R EC

D Q

SD

RD

EC

Control

S/R

Control

1

F'

G'

H'

DIN

G'

H'H

Func.Gen.

GFunc.Gen.

F

G4G3G2G1

F4

YQ

Y

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D Q

SD

RD

EC

1

F'

G'

H'

DIN

F'

H'

FFunc.Gen.

F3F2F1

K

XQ

X

CLB Functionalities

• Two 4-input function generatorsI l t d i L k T bl i 16 1 RAM– Implemented using Lookup Tables using 16x1 RAM.

– Can also implement 16x1 memory.

• Two Registers– Each can be configured as flip-flop or latch.– Independent clock polarity.– Synchronous and asynchronous Set / Reset.

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Page 19: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Look Up Tables• Combinatorial Logic is stored in 16x1 SRAM Look Up

Tables (LUTs) in a CLB

• Example:Look Up Table

Combinatorial Logic4-bit address

Capacity is limited by number of inputs, not complexity

A B C D Z

0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 1 0 0 10 1 0 1 1

. . .

Combinatorial Logic

AB

CD

Z

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Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM

1 1 0 0 01 1 0 1 01 1 1 0 01 1 1 1 1

GFunc.Gen.

G4G3G2G1

WE

XC4000X I/O Block Diagram

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Page 20: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Xilinx FPGA Routing

1) Fast Direct Interconnect - CLB to CLB

2) General Purpose Interconnect - Uses switch matrix

CLB CLB

SwitchMatrix

SwitchMatrix

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CLB CLB

FPGA Design Flow

• Design Entry – In schematic, VHDL, or Verilog. g

• Implementation– Placement & Routing

– Bitstream generation

– Analyze timing, view layout, simulation, etc.

• Download– Directly to Xilinx hardware devices with unlimited

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Directly to Xilinx hardware devices with unlimited reconfigurations.

Page 21: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Gate Array

Introduction

• In view of the fast prototyping capability, the gate array (GA) comes after the FPGA. – Design implementation of

• FPGA chip is done with user programming,

• Gate array is done with metal mask design and processing.

• Gate array implementation requires a two-step manufacturing process: a) The first phase, which is based on generic (standard) masks,

results in an array of uncommitted transistors on each GA chip.

b) Th itt d hi b t i d l t hi h i

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b) These uncommitted chips can be customized later, which is completed by defining the metal interconnects between the transistors of the array.

Page 22: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Channeled vs. Channel-less (SoG) Approaches

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Page 23: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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• The GA chip utilization factor is higher than that of FPGA.– The used chip area divided by the total chip area.

• Chip speed is also higher.– More customized design can be achieved with metal mask

designs.

• Current gate array chips can implement as many as hundreds of thousands of logic gates.

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g g

Standard Cell Based Design

Page 24: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Introduction

• One of the most prevalent custom design styles.– Also called semi-custom design style.g y

– Requires developing full custom mask set.

• Basic idea:– All of the commonly used logic cells are developed,

characterized, and stored in a standard cell library.

– A typical library may contain a few hundred cells.

• Inverters, NAND gates, NOR gates, complex AOI, OAI f f

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gates, D-latches, and flip-flops.

Characteristic of the Cells

• Each cell is designed with a fixed height.– To enable automated placement of the cells, and p

– Routing of inter-cell connections.

– A number of cells can be abutted side-by-side to form rows.

• The power and ground rails typically run parallel to upper and lower boundaries of cell.– Neighboring cells share a common power and ground bus.

– nMOS transistors are located closer to the ground rail while

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the pMOS transistors are placed closer to the power rail.

• The input and output pins are located on the upper and lower boundaries of the cell.

Page 25: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Standard Cells

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Standard Cell Layout

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Page 26: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Floorplan for Standard Cell Design

• Inside the I/O frame which is reserved for I/O cells, the chip area contains rows or columns of standard

llcells. – Between cell rows are channels for dedicated inter-cell

routing. – Over-the-cell routing is also possible.

• The physical design and layout of logic cells ensure that – When placed into rows, their heights match.

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– Neighboring cells can be abutted side-by-side, which provides natural connections for power and ground lines in each row.

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Page 27: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Full Custom Design

Introduction

• The standard-cells based design is often called semi custom design.g– The cells are pre-designed for general use and the same

cells are utilized in many different chip designs.

• In the full custom design, the entire mask design is done anew without use of any library. – The development cost of such a design style is

prohibitively high.

f

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– The concept of design reuse is becoming popular to reduce design cycle time and cost.

Page 28: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Contd.

• The most rigorous full custom design can be the design of a memory cell.g y– Static or dynamic.

– Since the same layout design is replicated, there would not be any alternative to high density memory chip design.

• For logic chip design, a good compromise can be achieved by using a combination of different design styles on the same chip.

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– Standard cells, data-path cells and PLAs.

• In real full-custom layout in which the geometry, orientation and placement of every transistor is p ydone individually by the designer,– Design productivity is usually very low.

• Typically 10 to 20 transistors per day, per designer.

• In digital CMOS VLSI, full-custom design is rarely used due to the high labor cost. – Exceptions to this include the design of high-volume

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products such as memory chips, high-performance microprocessors and FPGA masters.

Page 29: VLSI Design Styles - facweb.iitkgp.ac.inisg/VLSI/VLSI-design-styles.pdf · – Since the same layout design is replicated, there would not be any alternative to high density memory

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Comparison Among Various Design Styles

Design Style

FPGA Gate array Standard cell

Full c stomcell custom

Cell size Fixed Fixed Fixed height

Variable

Cell type Programmable

Fixed Variable Variable

Cell placement Fixed Fixed In row Variable

Interconnect Programm Variable Variable Variable

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Interconnect Programmable

Variable Variable Variable

Design time Very fast Fast Medium Slow