VLSI DESIGN EDA Tools

Lecture by Prof.R.V.B.Chary

Director, Center for VLSI DESIGNCVR Engg College.

(Former Head and BOS Chairman of ECE,OU)

VLSI DESIGN

FRONT-END DESIGN BACK-END DESIGN

VLSI DESIGN METHODOLOGIES

TOP-DOWN DESIGN APPROACH BOTTOM-UP DESIGN APPROACH

CURRENT VLSI IMPLEMENTATION TECHNOLOGY

TECHNOLOGY : CMOS Channel Length

MICRON CMOS > 1 um SUB-MICRON CMOS >0.18um DEEP SUB-MICRON CMOS

VLSIIMPLEMENTATION

METHODS

FULL-CUSTOM SEMI -CUSTOM

Standard CellLibrary Based FPGA Based

COMPARISON

LOWMEDIUMHIGHCOST

HIGHMEDIUMLOWSPEED

HIGHMEDIUMLOWDENSITY

LONGMORELESSTIME TO MARKET

FULL CUSTOM

STANDARD CELLBASED

FPGA BASED

Design Flow

Full Custom CMOS Chip Design Flow

Semi-Custmom FPGA Based Design Flow

Semi-Custom Standard Cell Library Based CMOS Chip Design Flow

FULL CUSTOM CMOS CHIP DESIGN USING CADENCE TOOLS

Requirements:

CMOS Physical Design Kit (PDK) NMOS / PMOS Device spice models & symbols DRC Rule File Extraction Rule File L V S Rule File

Tool: Integrated Circuit Front-End to Back-End [ICFB]

CADENCE FULL CUSTOM DESIGN TOOL ICFB

ICFB consists of : VIRTUOSO SCHEMATIC COMPOSER

VIRTUOSO LAYOUT EDITOR

Assura / DIVA DRC, EXTRACT, LVS Physical Design VERIFICATION TOOLS

SPECTRE SPICE SIMULATOR (ANALOG SIMULATOR) for Schematic and Layout design

CMOS TECHNOLOGY FILES AVAILABLE AT CENTER FOR VLSI DESIGN

1.2 um CMOS Physical Design Kit of SCL Semiconductor Complex Limited, (CHIP INDIA)

S C L 1.2 um Digital Standard Cell Library

0.2 um CMOS Generic PDK Kit from Cadence website

NCSU Cadence PDK Kit 0.18, 0.2um, 0.3um, CMOS PDK - TSMC 0.6 um, 1.6 um, CMOS PDK - AMI

FULL CUSTOM CMOS IC-DESIGN FLOW USING CADENCE TOOLS

DESIGN SPECIFICATIONS ARCHITECTURE(FUNCTIONAL BLOCKS &

LEAF CELLS) CMOS LEAF CELL DESIGN FLOW

CMOS TRANSISTOR LEVEL CIRCUIT DESIGN FOR LEAF CELL

SYMBOL CREATION TEST BENCH FOR SPICE SIMULATION PHYSICAL (LAYOUT) DESIGN DESIGN RULE CHECK (DRC) EXTRACTION LAYOUT Vs SCHEMATIC VERIFICATION (LVS) POST LAYOUT SIMULATION

FULL CUSTOM CMOS CHIP DESIGN EXERCISE USING

CADENCE TOOLS

UG Final Year Project (2005-2006)

Signed/Unsigned Array Multiplier CMOS CHIP Design

CMOS Leaf Cells Design FlowCMOS Inverter SCHEMATIC

Inverter Symbol Creation

Inverter Testbench for Schematic

Inverter Schematic SPICE Simulation

Inverter Layout

Inverter Extracted View without Parasitics

Inverter Extracted Layout View With Parasitics

Inverter Post Layout Simulation

CMOS Nand Schematic

Nand Symbol

Nand Layout Design

Full Adder Schematic

FULL ADDER Symbol

Full Adder Layout Design

D Flip Flop Schematic

D Flip Flop Layout Design

4 Bit Register Schematic

4-Bit Register Symbol

4-Bit Register Layout

Top Level CORE Schematic

Top Level CORE Schematic with I/O Pads

Top Level CORE Layout Without Pads

Top Level CHIP Layout With Pads for Silicon Foundry

CMOS FUNCTIONAL BLOCKS DESIGN USING LEAF CELLS

CMOS CIRCUIT DESIGN, SYMBOL CREATION & SPICE SIMULATION

CMOS LAYOUT DESIGN MANUAL PLACE AND Routing using designed LEAF CELLS PHYSICAL VERIFICATION(D R C, EXTRACTION, LVS) POST-LAYOUT SIMULATION

TOP LEVEL FULL CUSTOM CMOS CHIP ASSEMBLING

Top level Schematic circuit Symbol Creation SPICE Simulation Top level Layout design using Functional Layout blocks(Manual

Place and Route) Physical Verification (DRC, Extraction LVS) Postlayout Simulation for SIGNOFF

GDS File Generation to forward to Silicon Foundry

SEMI CUSTOM FPGA BASED DESIGN FLOW

FRONT END DESIGN FLOW

BACK END DESIGN FLOW

FRONT-END DESIGN FLOW FOR CPLD / FPGA IMPLEMENTATION

Design Idea / Specifications Architecture VHDL / Verilog Modelling Functional Simulation Logic Synthesis Post Synthesis SimulationNote : This is to arrive at Gate Level VHDL /

Verilog Netlist and Gate Level circuit for Vendor FPGA Technology Library

FRONT END DESIGNEDA TOOLS FOR FPGA/CPLD

POPULAR VHDL/VERILOG SIMULATORS Modelsim Simulator Active HDL Simulator Speedwave Silos for Verilog Simulation

POPULAR CPLD / FPGA SYNTHESIS TOOLS Synplify Pro FPGA Express Leonardo Spectrum

FRONT-END DESIGN EXERCISE FOR FPGA IMPLEMENTATION

SPECIFICATIONSSYNCHRONOUS 4-BIT COUNTERASYNCHRONOUS RESET

BLOCK DIAGRAM OF THE COUNTER

COUNTERCLK

RESET

Q(3:0)

OUTPUT

COUNTER VHDL MODEL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(clk,reset:in std_logic; q:out std_logic_vector(3 downto 0)); end counter; architecture behv of counter is signal qi :std_logic_vector(3 downto 0); begin process(clk,reset) begin if reset = '1' then qi

VHDL SIMULATION ENVIRONMENT

VHDL COMPILERVHDL

MODELFILE

INTERMEDIATECODE FOR

VHDL MODEL

IEEE LIBRARY

VHDL SIMULATOR

APPLY STIMULUS

WAVE FORM WINDOW

WORK LIBRARY

SIMULATION RESULTS

FPGA LOGIC SYNTHESIS

VHDLMODEL

FILE

SYNPLIFY PROSYNTHESIS TOOL

VHDLNETLIST

FILE

FPGA TECH FILE

CONSTRAINTS

SYNTHESIS RESULTS

SAMPLE NET LIST FROM SYNTHESIS Written by Synplicity -- Wed Dec 21 10:34:28 2005 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library synplify; use synplify.components.all;

entity L1_2 is port( Z : out std_logic; I0 : in std_logic); end L1_2;

architecture beh of L1_2 is signal GND : std_logic ; signal VCC : std_logic ; begin GND

BACK END DESIGN FOR FPGA

PLACE AND ROUTING THE NET LIST TO GENERATE BITMAP FILES

NET-LIST FILE PLACE AND ROUTE BIT-MAP FILE

FPGA DEVICE

DOWNLOAD TO

POPULAR FPGA DESIGN KITS

ALTERA FPGA DESIGN KITS

MAX+ PLUS II FPGA DEVELOPMENT KIT QUARTUS FPGA DEVELOPMENT KIT XILINX ISE FPGA DESIGN KIT

ISE FPGA DESIGN KITISE EMBEDDED KIT

These Kits Comprises VHDL/VERILOG HDL SIMULATOR VHDL/VERILOG SYNTHESIS TOOL PLACE AND ROUTE CPLD/FPGA PROGRAMMER BOARDS

SEMI-CUSTOM STANDARD CELL LIBRARY BASED CMOS IC

DESIGN FLOW USING CADENCE TOOLS

Front End Design Flow

Back End Design Flow

Front End Design Flow

Design Idea / Specifications Architecture VHDL / Verilog Modelling Functional Simulation Logic Synthesis Post Synthesis SimulationNote : This is to arrive at Gate Level VHDL /

Verilog Netlist and Gate Level circuit Vendor Standard Cell Library

FRONT-END DESIGN FLOW and CADENCE EDA TOOLS

NCVHDL / NC VERILOG SIMULATOR

VHDL / VERILOGMODELFILE

RTL COMPILER /BUILD GATESSYNTHESIS TOOL

VENDOR STANDARD

CELL LIBRARY

CONSTRAINTS

CONTD

VHDL/VERILOGNET LIST

POST SYNTHESIS SIMULATION USING

NC VHDL / NC VERILOGSIMULATORS

BACK-END DESIGN FLOW AND CADENCE TOOLSVERILOG NETLIST

FILE

SOC ENCOUNTER / SILICON ENSEMBLE TOOL(LAY-OUT LEVEL AUTO PLACE AND

ROUTE)

STANDARD CELLSLIBRARY LEF

FILE

GDS II DATA FILE

CONTD

THIS GDS FILE CONTAINS ABSTRACT VIEW OF THE STANDARD CELLS AND WHOSE CONNECTIVITY WITH METAL LAYERS

To ICFB TOOL for SIGNOFF

CONTD

I C F B TOOL(IC FRONT-END TO BACK-END TOOL)

VERILOG NET LIST

FILEGDS II FILE

ASSURA / DIVA DESIGN RULE CHECKEXTRACTION

LVS Verification

CONTD

POST LAY-OUT SIMULATIONSPECTRE SPICE SIMULATOR

(ANALOG SIMULATOR)

GDS II DATA FILE(TAPE OUT)

SILICON FOUNDRY

SIGN OFF STAGE

Example Demo for Standard Cell Based Semi-custom Counter

Design FlowCounter Verilog Code

module counter(clk,rst,qout);

output [3:0] qout;

input clk,rst;

reg [3:0] qout;

always@(posedge clk or posedge rst)beginif(rst)qout

Counter Test Benchmodule tb_counter;reg clk,rst;wire [3:0] qout;

counter u0 (clk,rst,qout);

initialbegin$sdf_annotate ("/home/chalapathi/rc/rc52lab/work/counter_sdf.sdf.X", u0);clk = 1'b0;rst = 1'b0;

#10 rst = 1'b1;#20 rst = 1'b0;

end

always#10 clk = ~ clk ;endmodule

Functional Simulation Results

Gate Level Circuit Generated by RTL Compiler Synthesis Tool

Post Synthesis Simulation Results

Auto Place and Route using SOC Encounter at Layout Abstract Level

EDA TOOLS AT

CENTER FOR VLSI DESIGN , C V R ENGG. COLLEGE

EDA Tools & Systems available at Center for

VLSI Design:

Cadence EDA Tools for Semi Custom & Full Custom VLSI Design:

1) NC-VHDL Simulator2) NC- Verilog Simulator3) Build Gates Extreme synthesis tool4) Silicon Ensemble/ SoC encounter for

Auto Place & Route.

Contd.

5) Virtuoso Schematic Capture6) Virtuoso Layout Editor7) Diva/ Assura Layout verification for

i. Design Rule Check.ii. Extractor

iii. Layout Vs Schematic Checker8) Analog Simulator: Spectre Spice

EDA Tools under ALTERA University

Program:

Modelsim for VHDL/Verilog Simulation

Quartus FPGA Developer Software

Max Plus II CPLD/FPGA Developer Software

CPLD/FPGA Programmer Boards

EDA Tools under XILINX University

Program:

ISE 8.1 FPGA Development Software

Chip Scope Software

ISE Embedded Development Software Kit.

SPARTAN-3 FPGA Programmer Boards.

PICO Blaze & Micro Blaze Micro Controller Verilog/ VHDL Soft cores.

Synplify Pro Synthesis tool for CPLD/ FGPA devices.

Multisim 7 Spice simulator. Texas DSP trainer Kits.

License Servers:

Cadence Server ALTERA Server Synplify Pro Server

Workstations:

Sun SPARC Systems. Linux / Windows XP Systems.

FINAL YEAR UG PROJECTS CARRIED OUT

AT

CENTER FOR VLSI DESIGN

DURING

ACADEMIC YEAR 2005-06.

1. PROGRAMMABLE BAUD RATE GENERATOR CMOS CHIP DESIGN USING CADENCE TOOLS

by

Mr. M.Raghavendra, Roll No. 02B81A0446&

Ms. C.Sahaja , Roll No. 02B81A0457

2. ALU CMOS CHIP DESIGN USING CADENCE TOOLS

by

Mr. N.Vijaya Bhaskara, Roll No. 02B81A0488&

Mr. Debhasis Chand, Roll No.02B81A0411

3. ARRAY MULTIPLIER CMOS CHIP DESIGN USING CADENCE TOOLS

by

Mr. Gaurav Bhatia, Roll No. 02B81A0415&

Mr. Ashwin Kumar, Roll No.02B81A0407

4. SERIAL ADDER CMOS CHIP DESIGN USING CADENCE TOOLS

by

Ms. Preethi Tiwari, Roll No. 02B81A0414

&Ms.Hetal Patel, Roll No.02B81A0418

5. UNIVERSAL SHIFT REGISTER CMOS CHIP DESIGN USING CADENCE TOOLS

by

Ms. M. Hima, Roll No. 02B81A0419&

Ms. E. Saritha, Roll No.02B81A0460

6. 8-BIT ACCUMULATOR CMOS CHIP DESIGN USING CADENCE TOOLS

by

Mr. K.Rakesh,Roll No. 02B81A0448&

Mr. S. Ravi Kumar , Roll No.02B81A0451

7. PROGRAMMABLE SYNCHRONOUS UP-DOWN COUNTER WITH PARELLEL LOAD CMOS CHIP DESIGN USING CADENCE TOOLS

by

Ms. K.Manga,Roll No. 02B81A0433&

Ms. V.Anusha , Roll No.02B81A0404

8. SERIAL MULTIPLIER CMOS CHIP DESIGN USING CADENCE TOOLS

by

Ms. N.Ramya Reddy,Roll No. 02B81A0450&

Ms. D.Parvathi , Roll No.03B85A0404

9. FPGA BASED MAC CHIP DESIGN AND VERIFICATION USING XILINX TOOLS

by

Mr. S.A Mahesh Kumar,Roll No. 02B81A0430

Ongoing UG Projects [ 2006-07]

Single Cycle 32 Bit RISC Processor VHDL Design and Synthesis

16 Bit CPU Verilog HDL Design and Synthesis

16 Bit CPU VHDL Design and Synthesis UART Verilog HDL Design and Synthesis Peripheral Interface Chip SemiCustom

and Full Custom Design

..contd

Full Custom Flash ADC CMOS Chip design

Full Custom Complex Multiplier CMOS Chip Design

Full Custom Stop-Watch CMOS Chip Design

FPGA based Embedded System using Picoblaze RISC Processor IP