VLSI Circuit Design - UP jcf/ensino/disciplinas/mieec/pcvlsi/2015-16/00-start...¢  VLSI Circuit Design
VLSI Circuit Design - UP jcf/ensino/disciplinas/mieec/pcvlsi/2015-16/00-start...¢  VLSI Circuit Design
VLSI Circuit Design - UP jcf/ensino/disciplinas/mieec/pcvlsi/2015-16/00-start...¢  VLSI Circuit Design
VLSI Circuit Design - UP jcf/ensino/disciplinas/mieec/pcvlsi/2015-16/00-start...¢  VLSI Circuit Design
VLSI Circuit Design - UP jcf/ensino/disciplinas/mieec/pcvlsi/2015-16/00-start...¢  VLSI Circuit Design

VLSI Circuit Design - UP jcf/ensino/disciplinas/mieec/pcvlsi/2015-16/00-start...¢  VLSI Circuit Design

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  • VLSI Circuit Design

    UltraSparc T2 (8 cores, 65 nm) [Source: http://blogs.sun.com/ontherecord/entry/ultrasparc_t1_world_s_fastest]

    João Canas Ferreira (FEUP) PCVL 2016-02-17 1 / 5

    http://blogs.sun.com/ontherecord/entry/ultrasparc_t1_world_s_fastest

  • VLSI Circuit Design

    Topics

    I Integrated circuit (IC) design flow I Design of CMOS digital circuits

    I MOS transistor modeling I Fabrication process and design rules I MOS logic families (incl. transmission gates, dynamic families) I Sizing of logic gates I Latches and flip-flops I Interconnect modeling I Low-power circuits I FPGA architetcture

    I IC Design I Project: Full-custom layout ⇒ Fabrication data I Circuit analysis and exercises (lab classes)

    João Canas Ferreira (FEUP) PCVL 2016-02-17 2 / 5

  • Readings

    I Digital Integrated Circuits: A Design Perspective Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic Prentice-Hall, 2nd ed.

    I Application-Specific Integrated Circuits Michael J. S. Smith; Addison-Wesley

    I CMOS VLSI Design: A Circuits and Systems Perspective, 4/E Neil Weste & David Harris; Addison-Wesley (alternative to Rabaey et al.)

    I Digital VLSI Chip Design with Cadence and Synopsys CAD Tools Erik Brunvand; Addison Wesley

    I Lecture slides (concise; take notes)

    I Solved exams and additional info at paginas.fe.up.pt/~jcf/ensino/disciplinas/mieec/pcvlsi/2015-16

    João Canas Ferreira (FEUP) PCVL 2016-02-17 3 / 5

    paginas.fe.up.pt/~jcf/ensino/disciplinas/mieec/pcvlsi/2015-16

  • Class work and grading

    I One design project: P I One test on circuit analysis: T I Exam: E

    Distributed evaluation

    NDist = 0.7× P + 0.3× T

    Minimum grade: NDist >= 8.0

    Final grade

    NFinal = 0.6× NDist + 0.4× E

    Conditions: E >= 6.0 and NFinal >= 10.

    João Canas Ferreira (FEUP) PCVL 2016-02-17 4 / 5

  • Contacts

    I João Canas Ferreira Email: jcf@fe.up.pt Room I237 Office hours: Thursdays, 11:00–13:00 and by appointment

    João Canas Ferreira (FEUP) PCVL 2016-02-17 5 / 5