N e t w o r k i n g C o m m u n i c a t i o n s

B l o c k D i a g r a m

VIPSingle-Chip VLSI ISDN Subscriber Processor

O V E R V I E WThe VLSI ISDN Subscriber Processor(VIP) offers in a single device a powerful programmable engine forISDN subscriber communications.It includes most of the circuitryrequired to implement a full featured ISDN terminal, making it themost highly integrated and cost competitive solution.

F E A T U R E S• Full static operation• 32-bit RISC ARM processor running

at 36.8 MHz• 3 Kbytes of on-chip high speed

cache SRAM• Programmable clock speed• Programmable power-down with

event wake-up• Support of 8/16/32-bit wide external

SRAM/ ROM/ DRAM (54ns to 1.2µsaccess time)

• Fast Interrupt controller, fully maskable for all peripherals

• On-chip SO-Interface transceivercontaining AFE, data/clock recoveryand framing circuitry (conformingto the ITU spec. l.430)

• Low level D-channel data link con-troller providing Layer 1 and basicLayer 2 functions in hardware

• G.711 PCM CODEC, complete withProgrammable AFE, tone ringer out-

S y s t e m C o n f i g u r a t i o n

put, additional input and output together with sophisti-cated powerdown modes• Internal 14-bit linear PCM format

A P P L I C A T I O N S• ISDN terminal equipment· Domestic and digital PABX

telephones· H.320 videophones· Integrated PC communications

ISDN-to-DECT· domestic and business

applications• ISDN-to-PCMCIA com

munication cards

ISDN Interface ConfigurationsThe VIP is designed to facilitate theintegration of basic-rate ISDN terminalequipment. The device supports two64 Kbit/s and one 16 Kbit/s channels(ie. 2B+D), and interfaces to the ISDNnetwork via an on-chip SO-Interface.Fig(2) shows the application area forVIP in relation to the standard ISDN network termination reference points.In this figure, the SO-Interface definesthe interface for connection of individ-ual ISDN terminals. It separates theuser terminal equipment from the net-work related communications func-tions. The U-Interface defines the fullduplex signal on the digital subscriber line.

F U N C T I O N A LD E S C R I P T I O NThe VIP is a highly integrated solutionfacilitating the implementation of ISDNterminal equipment such as feature-phones and terminal adapters. Thedevice has been designed using VLSI’sFSB™ methodology. Each of these FSB™ elements will now be discussedin turn.

ARM RISC CoreAt the heart of VIP is the ARM RISCprocessor. This high performance, lowpower CPU allows many of the func-tions previously implemented in hard-ware to be performed in software,thereby reducing silicon area and cost.

On-Chip MemoryThe VIP contains 3 Kbytes of on-chipcache memory. This allows-speed criti-cal routines to run at maximum speed.

Memory InterfaceThe Memory Interface allows the connection of external 8-, 16- or 32- Bit static RAM/ROM. An internal DRAM timing controller supports non sequential and fast page modeDRAM access.

SO-InterfaceThe SO-interface transceiver allows direct connection to the SO-InterfaceBus. It contains all the Layer 1 func-tions defined in the ITU I.430 specifi-cation. The D-channel data link con-troller provides the Layer 1 and thebasic Layer 2 frame formatting. Theremaining Layer 2 functions are per-formed by software running on theARM. All bits in the So-Frame areaccessible to the ARM.

10M2 Interface For communication with other serialdevices such as CODEC’s DSP’s orperipherals, the VIP incorporates afuII duplex serial port with a 64-bitserial - parallel converter to drivestandard 8-bit telecom or 14-bit linear CODEC’s.

Audio CODEC The G.711 PCM CODEC contains ananalog front end (AFE) that allowsdirect connection to both a telephonehandset as well as a handsfree micro-phone and speaker. A tone ringer out-put is also provided for call alert etc.

UARTThe ACTIS includes an on-chip UART,allowing serial communications with apersonal computer etc. This simplefull duplex serial interface has a com-plexity equivalent to an 8251 UART.Baud rates are programmable from1.2 kBaud up to a maximum of 115.2

kBaud Keypad Interface The keypadinterface consists of 6 inputs withinternal pull-down resistors and an Or-Gate. The row lines are derivedusing a number of I/O ports. Theoccurrence of a key action – push andrelease – can generate a maskableinterrupt, which under the control ofthe ARM can be used to determine thekey depressed.

Power ManagementA flexible power management con-troller enables the system clock speedto programmed down to stop.

I/O PortsAll Ports are bi-directional and can beprogrammed to have special functionsin the various configurations support-ed by the VIP.

TechnologyThe VIP has been designed usingVLSI’s 0.6µ CMOS, triple-layer metal,mixed-signal technology, and is avail-able in a 144 pin MQFP package.

I S D N I n t e r f a c e C o n f i g u r a t i o n

With respect to the information in this document, VLSITechnology, Inc. (VLSI) makes no guarantee or warranty of itsaccuracy or that the use of such information will not infringeupon the intellectual rights of third parties. VLSI shall not beresponsible for any loss or damage of whatever nature result-ing from the use of, or reliance upon it and no patent orother license is implied hereby. This document does not inany way extend or modify VLSI’s warranty on any productbeyond that set forth in its standard terms and conditions ofsale. VLSI reserves the right to make changes in its productsand specifications at any time and without notice.

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© 1997 VLSI Technology, Inc. Printed in USA Document Control: PB-VIP V1.0 October 97

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S e r i a l I n t e r f a c e

DEVELOPMENT E N V I R O N M E N TTo support the integration of applica-tions based on the VIP, VLSI offers acomplete set of hard w a re develop-ment tools as well as demonstrationand evaluation systems. Fig(3) showsa typical development environment.

Since both VIP and ACTIS(Single-

chip VLSI ISDN data processor) use a compatible design methodology,the same development tool environ-ment can be used to develop e i t h e rISDN data communications equipmentor ISDN Terminals, thereby maintain-ing our objective of a common plat-form for different applications. This is mandatory to reduce time-to-market.

ACTIS/VIP Development BoardThe Development Board,(VNS80000/DB) serves the dual function of product evaluation anddevelopment. From a hardware pointof view it functions as and ISDN telephone and can be used as a hard-ware & software development platformconnecting to the ISDN S0-bus asdefined by the ITU I.430 and ETSI,ETS 300 012 specifications.