VI. Transistor ampli ers: Biasing and Small Signal Modelaries.ucsd.edu/NAJMABADI/CLASS/ECE65/06-S/NOTES/transistor-2.pdfVI. Transistor ampli ers: Biasing and Small Signal Model 6.1

VI. Transistor amplifiers: Biasing and Small Signal Model

6.1 Introduction

Transistor amplifiers utilizing BJT or FET are similar in design and analysis. Accordingly

we will discuss BJT amplifiers thoroughly. Then, similar FET circuits are briefly reviewed.

Consider the circuit below. The operating point of the BJT is shown in the iCvCE space.

vCE

BR

VBB

VCC

RC

i C

i B

vBE

+

_+

_

i E

Let us add a sinusoidal source with an amplitude of ∆VBB in series with VBB . In response to

this additional source, the base current will become iB +∆iB leading to the collector current

of iC + ∆iC and CE voltage of vCE + ∆vCE .

vCE

BR

VBB

VCC

RCvCE

i B

i C i C

i B

VBB

vBEvBE

+

_+

_∆

+∆

+∆+∆

+∆

~−+

For example, assume without the sinusoidal source, the base current is 150 µA, iC = 22 mA,

and vCE = 7 V (the Q point). If the amplitude of ∆iB is 40 µA, then with the addition of

the sinusoidal source iB + ∆iB = 150 + 40 cos(ωt) and varies from 110 to 190 µA. The BJT

operating point should remain on the load line and collector current and CE voltage change

with changing base current while remaining on the load line. For example when base current

is 190 µA, the collector current is 28.6 mA and CE voltage is about 4.5 V. As can be seen

from the figure above, the collector current will approximately be iC +∆iC = 22+6.6 cos(ωt)

and CE voltage is vCE + ∆vCE = 7 − 2.5 cos(ωt).

The above example shows that the signal from the sinusoidal source ∆VBB is greatly amplified

and appears as signals in collector current and CE voltage. It is clear from the figure that

this happens as long as the BJT stays in the active-linear state. As the amplitude of ∆iB

ECE65 Lecture Notes (F. Najmabadi), Winter 2006 158

is increased, the swings of BJT operating point along the load line become larger and larger

and, at some value of ∆iB, BJT will enter either the cut-off or saturation state and the

output signals will not be a sinusoidal function. Note: An important observation is that

one should locate the Q point in the middle of the load line if we want to have the largest

output signal.

The above circuit, however, has two major problems: 1) The input signal, ∆VBB , is in

series with the VBB DC voltage making design of previous two-port network difficult, and

2) The output signal is usually taken across RC as RC × iC . This output voltage has a DC

component which is of no interest and can cause problems in the design of the next-stage,

two-port network.

The DC voltage needed to “bias” the BJT (establish the Q point) and the AC signal of

interest can be added together or separated using capacitor coupling as dis iscussed below.

6.1.1 Capacitive Coupling

For DC voltages (ω = 0), the capacitor is an open circuit (infinite impedance). For AC

voltages, the impedance of a capacitor, Z = −j/(ωC), can be made sufficiently small by

choosing an appropriately large value for C (the higher the frequency, the lower the C value

that one needs). This property of capacitors can be used to add and separate AC and DC

signals. Example below highlights this effect.

C1

1

2R

B

+15 V

A

vi+−

R

Consider the circuit below which includes a DC source of

15 V and an AC source of vi = Vi cos(ωt). We are inter-

ested to calculate voltages vA and vB. The best method

to solve this circuit is superposition. The circuit is bro-

ken into two circuits. In circuit 1, we “kill” the AC source

and keep the DC source. In circuit 2, we “kill” the DC

source and keep the AC source. Superposition principle

states that vA = vA1 + vA2 and vB = vB1 + vB2.

C1

2R

AB

1

+15 V +15 V

C1

2R

AB

1

C1

2R

AB

1

vi

vv

vv

+ vi

vv1

12

2

+−

R

+−

R

+−

+−

R

Consider the first circuit. It is driven by a DC source and, therefore, the capacitor will act

as open circuit. The voltage vA1 = 0 as it is connected to ground and vB1 can be found by


voltage divider formula: vB1 = 15R1/(R1 + R2). As can be seen both vA1 and vB1 are DC

voltages.

In the second circuit, resistors R1 and R2 are in parallel. Let RB = R1 ‖ R2. The circuit

is a high-pass filter: VA2 = Vi and VB2 = Vi(RB)/(RB + 1/jωC). If we operate the circuit

at frequency above the cut-off frequency of the filter, i.e., RB 1/ωC, we will have VB2 ≈VA2 = Vi and vB2 ≈ vA2 = Vi cos(ωt). Therefore, for ω 1/RBC

vA = vA1 + vA2 = Vi cos(ωt)

vB = vB1 + vB2 =R1

R1 + R2

× 15 + Vi cos(ωt)

Obviously, the capacitor is preventing the DC voltage to appear at point A, while the voltage

at point B is the sum of DC signal from 15-V supply and the AC signal.

Using capacitive coupling, we can reconfigure our previous amplifier circuit as is shown in

the figure below. Capacitive coupling is used extensively in transistor amplifiers.

BR

VCC

RCi B

i C i C

i B

vBEvBE

VBB

VBB

vCE vCE

vCEvCE vCE

+

_+

_+∆∆

~

+∆

∆+∆

+∆

+∆

−+

BJT amplifier circuits are analyzed using superposition, similar to the example above:

1) DC Biasing: The input AC signal is set to zero and capacitors act as open circuit. This

analysis establishes the Q point in the active-linear state.

2) AC Response: DC bias voltages are set to zero. The response of the circuit to an AC

input is calculated and the transfer function, input and output impedances, etc. are found.

The break up of the problem into these two parts have an additional advantage as the

requirement for accuracy are different in the two cases. For DC biasing, we are interested in

locating the Q point roughly in the middle of active-linear state. The exact location of the

Q point is not important. Thus, a simple model, such as large-signal model of page 114 is

quite adequate. We are, however, interested to compute the transfer function for AC signals

more accurately. We will develop a model which is more accurate for small AC signals in

this section.

FET-based amplifiers are similar. FET should be biased similar to BJT and the analysis

method is broken into the DC biasing and the AC response.


6.2 BJT Biasing

vCE

i C

i B

vBE

RCRB

VCC

+

_+

_

This simple bias circuit is usually referred to as “fixed bias” as a

fixed voltage is applied to the BJT base. As we like to have only one

power supply, the base circuit is also powered by VCC . (To avoid

confusion, we will use capital letters to denote DC bias values e.g.,

IC .) Assuming that BJT is in active-linear state, we have:

BE-KVL: VCC = IBRB + VBE → IB =VCC − VBE

RB

IC = βIB = βVCC − VBE

RB

CE-KVL: VCC = ICRC + VCE → VCE = VCC − ICRC

VCE = VCC − βRC

RB

(VCC − VBE)

For a given circuit (known RC , RB, VCC , and BJT β) the above equations can be solved to

find the Q-point (IB, IC , and VCE). Alternatively, one can use the above equations to design

a BJT circuit to operate at a certain Q point. (Note: Do not memorize the above equations

or use them as formulas, they can be easily derived from simple KVLs).

Example 1: Find values of RC , RB in the above circuit with β = 100 and VCC = 15 V so

that the Q-point is IC = 25 mA and VCE = 7.5 V.

Since the BJT is in the active-linear state (VCE = 7.5 > Vγ), IB = IC/β = 0.25 mA. BE-KVL

and CE-KVL result in:

BE-KVL: VCC + RBIB + VBE = 0 → RB =15 − 0.7

0.250= 57.2 kΩ

CE-KVL: VCC = ICRC + VCE → 15 = 25 × 10−3RC + 7.5 → RC = 300 Ω

Example 2: Consider the circuit designed in example 1. What is the Q point if β = 200.

We have RB = 57.2 kΩ, RC = 300 Ω, and VCC = 15 V but IB, IC , and VCE are unknown.

Assuming that the BJT is in the active-linear state:

BE-KVL: VCC + RBIB + VBE = 0 → IB =VCC − VBE

RB

= 0.25 mA

IC = β IB = 50 mA

CE-KVL: VCC = ICRC + VCE → VCE = 15 − 300 × 50 × 10−3 = 0


As VCE < vγ the BJT is not in the active-linear state (since IC > 0, the BJT should be in

saturation).

The above examples show the problem with our simple fixed-bias circuit as the β of a

commercial BJT can depart by a factor of 2 from its average value given in the manufacturers’

spec sheet. More importantly, environmental conditions (mainly temperature) can play an

important role. In a given BJT, IC increases by 9% per C for a fixed VBE (because of the

change in β). Consider a circuit which is tested to operate perfectly at 25C. At 35C, β

and IC will be roughly doubled and the BJT can be in saturation! In fact, the circuit has a

build-in positive feedback. If the temperature rises slightly, the corresponding increase in β

makes IC larger. Since the power dissipation in the transistor is VCEIC , the transistor may

get hotter which increases transistor β and IC further and can cause a “thermal runaway.”

The problem is that our biasing circuit fixes the value of IB (independent of BJT parameters)

and, as a result, both IC and VCE are directly proportional to BJT β (see formulas in the

previous page). A biasing scheme should be found that make the Q-point (IC and VCE)

independent of transistor β and insensitive to the above problems → Use negative feedback!

6.2.1 Voltage-Divider Biasing

vCE

i C

i B

vBE

RC

VCC

R1

RER2

+

_+

_

vCE

i C

i B

vBE

RC

RE

VCC

VBB

RB +

_+

_+−

TheveninEquivalent

This biasing scheme can be best analyzed and understood if we re-

place R1 and R2 of the voltage divider with its Thevenin equivalent:

VBB =R2

R1 + R2

VCC and RB = R1 ‖ R2

The emitter resistor, RE, provides the negative feedback. Suppose

IC becomes larger than the designed value (e.g., larger β due to an

increase in temperature). Then, VE = REIE will increase. Since

VBB and RB do not change, KVL in the BE loop shows that IB

should decrease which will reduce IC back towards its design value.

If IC becomes smaller than its design value opposite happens, IB

has to increase which will increase and stabilize IC .

Analysis below also shows that the Q point is independent of BJT

parameters:

IE ≈ IC = βIB

BE-KVL: VBB = RBIB + VBE + IERE → IB =VBB − VBE

RB + βRE

CE-KVL: VCC = RCIC + VCE + IERE → VCE = VCC − IC(RC + RE)


Choose RB such that RB βRE (this is the condition for the feedback to be effective):

IC ≈ IE ≈ VBB − VBE

RE

and IB ≈ VBB − VBE

βRE

VCE = VCC − IC(RC + RE) ≈ VCC − RC + RE

RE

(VBB − VBE)

Note that now both IC and VCE are independent of β.

Another way to see how the circuit works is to consider BE-KVL: VBB = RBIB+VBE+IERE.

If we choose RB βRE ≈ (IE/IB)RE or RBIB IERE (rhe feedback condition above),

the KVL reduces to VBB ≈ VBE + IERE, forcing a constant IE independent of the BJT β.

As IC ≈ IE this will also fixes the Q point of BJT. If the BJT parameters change (different

β due to a change in temperature), the circuit forces IE to remain fixed and changes IB

accordingly. This biasing scheme is one of several methods which fix IC (and VCE) and allow

the BJT to adjust IB (through negative feedback) to achieve the proper bias. This class of

biasing methods is usually called “self-bias” schemes.

Another important point follows from VBB ≈ VBE + IERE. As VBE is not a constant and

can change slightly (can drop to 0.6 or increase to 0.8 V for a Si BJT), we need to ensure

that IERE is much larger than possible changes in VBE . As changes in VBE = vγ is about

0.1 V, we need to ensure that VE = IERE 0.1 or VE > 10 × 0.1 = 1 V.

Example: Design a stable bias circuit with a Q point of IC = 2.5 mA and VCE = 7.5 V.

Transistor β ranges from 50 to 200.

Step 1: Find VCC : As we like to have the Q-point to be located in the middle of the load

line, we set VCC = 2VCE = 2 × 7.5 = 15 V.

Step 2: Find RC and RE:

VCE = VCC − IC(RC + RE) → RC + RE =7.5

2.5 × 10−3= 3 kΩ

We are free to choose RC and RE (usually the AC response sets the values of RC and RE as is

discussed later). We have to ensure, however, that VE = IERE > 1 V or RE > 1/IE = 400 Ω.

Let’s choose RE = 1 kΩ which gives RC = 3 − RE = 2 kΩ (both commercial values).

Step 3: Find RB and VBB : We need to set RB βRE. As any commercial BJT has a range

of β values and we want to ensure that the above inequality is always satisfied, we should

use the minimum β value:

RB βminRE → RB = 0.1βminRE = 0.1 ∗ 50 ∗ 1, 000 = 5 kΩ

VBB ≈ VBE + IERE = 0.7 + 2.5 × 10−3 × 103 = 3.2 V


Step 4: Find R1 and R2

RB = R1 ‖ R2 =R1R2

R1 + R2

= 5 kΩ

VBB

VCC

=R2

R1 + R2

=3.2

15= 0.21

The above are two equations in two unknowns (R1 and R2). The easiest way to solve these

equations are to divide the two equations to find R1 and use that in the equation for VBB :

R1 =5 kΩ

0.21= 24 kΩ

R2

R1 + R2

= 0.21 → 0.79R2 = 0.21R1 → R2 = 6.4 kΩ

Reasonable commercial values for R1 and R2 are and 24 kΩ and 6.2 kΩ, respectively.

The voltage divider biasing scheme is used frequently in BJT amplifiers. There are two

drawbacks to this biasing scheme that may make it unsuitable for some applications:

1) Because VB > 0, a coupling capacitor is needed to attach the input signal to the amplifier

circuit. As a result, this biasing scheme leads to an “AC” amplifier (cannot amplify DC

signals). In some applications, we need “DC” amplifiers. Biasing with two voltage sources,

discussed below, can solve this problem.

2) The voltage divider biasing requires 3 resistors (R1, R2, and RE), and a coupling capacitor.

In ICs, resistors and large capacitors take too much space compared to transistors. It is

preferable to reduce their numbers as much as possible. For IC applications, “current-

mirrors” are usually used to bias BJT amplifiers as is discussed below.

6.2.2 Biasing with 2 Voltage Sources

vCE

i C

i B

vBE

RC

RE

VCC

RB

−VEE

+

_+

_

This biasing scheme is also a self-bias method and is similar

to the voltage-divider biasing. Basically, we have assigned a

voltage of −VEE to the ground (reference voltage) and chosen

VEE = VBB . As such, all of the currents and voltages in the

circuit should be identical to the voltage-divider biasing. We

should find that this is a stable bias point as long as RB βRE.

BE-KVL: RBIB + VBE + REIE − VEE = 0

RB

IE

β+ REIE = VEE − VBE → IE =

VEE − VBE

RE + RB/β


Similar to the bias with one power supply, if we choose RB such that, RB βRE, we get:

IC ≈ IE ≈ VEE − VBE

RE

= const

CE-KVL: VCC = RCIC + VCE + REIE − VEE

VCE = VCC + VEE − IC(RC + RE) = const

Therefore, IC , and VCE are independent β and bias point is stable. Similar to the voltage-

divider bias, we need to ensure that REIE ≥ 1 V to account for possible variation in VBE .

Bias with two power supplies has certain advantages over biasing with one power supply, it

has two resistors, RB and RE (as opposed to three), and in fact, in most applications, we can

remove RB altogether and directly couple the input signal (without a coupling capacitor) to

the BJT). As such, such a configuration can also amplify “DC” signals.

6.2.3 Biasing in ICs: Current Mirrors

vCE

i C

i B

vBE

RC

RE

VCC

RB

−VEE

+

_+

_

I

The self-bias schemes above, voltage-divider and bias with 2 voltage

sources, essentially operate the same way: They force IE to have

a given value independent of the BJT parameters. In principle, the

same objective can be achieved if we could bias the BJT with a current

source as is shown. In this case, no bias resistor is needed and we only

need to include resistors necessary for AC operation. As such, biasing

with a current source is the preferred way in most integrated circuits.

Such a biasing can be achieved with a current mirror circuit.

i C

vBE1 vBE2

−VEE

i C

i E i E

E2i

+_

+_

refI

β +1Io

1Q Q2

Consider the circuit shown with two identical transistors, Q1

and Q2. Because both bases and emitters of the transistors

are connected together, KVL leads to vBE1 = vBE2. As BJT’s

are identical, they should have similar iB (iB1 = iB2 = iB)

and, therefore, similar iE = iE1 = iE2 and iC = iC1 = iC2

iB =iE

β + 1Io = iC =

βiEβ + 1

KCL: Iref = iC +2iE

β + 1=

iEβ + 1

+2iE

β + 1=

β + 2

β + 1iE

Io

Iref

=β

β + 2=

1

1 + 2/β

We have explicitly used iC = βiB and iE = (β + 1)iB to illustrate the impact of β.


For β 1, Io ≈ Iref (with an accuracy of 2/β). This circuit is called a “current mirror”

as the two transistors work in tandem to ensure that current Io remains the same as Iref

no matter what circuit is attached to the collector of Q2. As such, the circuit behaves as

a current source and can be used to bias BJT circuits, i.e., Q2 collector is attached to the

emitter circuit of the BJT amplifier to be biased.

i C

vBE1 vBE2

−VEE

i E i E

VCC

RC

+_

+_

Ioref

1Q Q2

IValue of Iref can be set in many ways. The simplest is by using

a resistor Rc as is shown. By KVL, we have:

VCC = RCIref + vBE1 − VEE

Iref =VCC + VEE − vBE1

RC

= const

Current mirror circuits are widely used for biasing BJTs. In the simple current mirror circuit

above, Io = Iref with a relative accuracy of 2/β and Iref is constant with an accuracy of

small changes in vBE1. Variations of the above simple current mirror, such as Wilson current

mirror and Widlar current mirror, have Io = Iref even with a higher accuracy and also

compensate for the small changes in vBE . Wilson mirror is especially popular because it

replace Rc with a transistor.

The right hand part of the current mirror circuit can be duplicated such that one current

mirror circuit can bias several BJT circuits as is shown. In fact, by coupling output of two

or more of the right hand BJTs, integer multiples of Iref can be made for biasing circuits

which require a higher bias current.

−VEE

VCC

RC

refI Io Io 2Io

A large family of BJT circuit, including current mirrors, differential amplifiers, and emitter-

coupled logic circuits include identical BJT pairs. These circuits are rarely made of discrete

transistors because if one chooses two commercial BJTs, e.g., two 2N3904, there is no guar-

anty that β1 = β2. However, if two identical BJTs are manufactured together on one chip

next to each other, β1 ≈ β2 within a couple of percent.


6.3 Biasing FETs

Field-effect transistors can also be used in amplifier circuits by operating the FET in the

active state. Similar to BJT amplifiers, we need to apply a DC bias (in addition to the input

AC signal) so that the FET remains in the active state for the entire period of the AC signal.

VDD

R RD

VGG

G

The fixed-bias scheme for FETs is shown. Note that RG is not necessary

for biasing but is necessary for AC operation as without RG the input

AC signal will be grounded through VGG.

GS-KVL: VGG = VGS

ID = K(VGS − Vt)2 = K(VGG − Vt)

2

DS-KVL: VDD = IDRD + VDS → VDS = VDD − KRD(VGG − Vt)2

Similar to the BJT β, both Vt and K vary due to the manufacturing and environmental

conditions. For example, as temperture is increased, both Vt and K decrease: decreasing

K decreases ID while decreasing Vt raises ID. The net effect (usually) is that ID decreases.

While the “thermal runaway” is not a problem in FETs, the bias point is not stable.

Similar to the BJT bias circuits, addition of a resistor RS provides the negative feedback

necessary to stabilize the bias point. For the voltage divider self bias, VG is set by R1 and R2.

Since VGS = VG −RSID, any decrease in ID would increase VGS and increases ID. Similarly,

any increase in ID would decrease VGS and decreases ID. As a result, ID will stay nearly

constant (because ID = K(VGS − Vt)2, ID does not remain constant like IC in a BJT, rather

it variation become much smaller by the negative feedback). Another difference between

voltage-divider self-bias for FET with that of BJT si that in the case of BJT, we have to

ensure that RB βRE for negative feedback to be effective. THis generally limits the value

of R1 and R2. In a FET, IG = 0 and no such limitaion exists. Therefore, R1 and R2 can be

taken to be large (MΩ) which is important in the AC response as is discussed later.

Self bias with 2 power supplies and FET current mirror bias are also shown below.

V

RR

R RD

S1

2

iD

DD

RR

R

DDV

i

D

D

S1

−VSS

R refI Io

VDD

Voltage-divider (Self Bias) Bias with 2 power supplies FET Current Mirror


6.4 BJT Small Signal Model

B

vBEvγ vsat

i i C

vCE

We calculated the DC behavior

of the BJT (DC biasing) with a

simple large-signal model. In the

active-linear state, this model is

simply: vBE = 0.7 V, iC = βiB.

This model is sufficient for calcu-

lating the Q point as we are only

interested in ensuring sufficient de-

sign space for the amplifier, i.e.,

Q point should be in the middle

of the load line in the active-linear

state. In fact, for our good bias-

ing scheme with negative feedback,

the Q point location is independent

of BJT parameters (and, therefore,

independent of model used!).

A comparison of the simple large-

signal model with the iv character-

istics of the BJT shows that our

simple large-signal model is crude.

For example, the input AC signal results in small changes in vBE around 0.7 V (Q point) and

corresponding changes in iB. The simple model cannot be used to calculate these changes

(It assumes vBE is constant!). Also for a fixed iB, iC is not exactly constant as is assumed

in the simple model (see iC vs vCE graphs). As a whole, the simple large signal model is not

sufficient to describe the AC behavior of BJT amplifiers where more accurate representations

of the amplifier gain, input and output resistance, etc. are needed.

A more accurate, but still linear, model can be developed by assuming that the changes in

transistor voltages and currents due to the AC signal are small compared to corresponding

Q-point values and using a Taylor series expansion. Consider function f(x). Suppose we

know the value of the function and all of its derivative at some known point x0. Then,

the value of the function in the neighborhood of x0 can be found from the Taylor Series


expansion as:

f(x0 + ∆x) = f(x0) + ∆xdf

dx

∣

∣

∣

∣

∣

x=x0

+(∆x)2

2

d2f

dx2

∣

∣

∣

∣

∣

x=x0

+ ...

Close to our original point of x0, ∆x is small and the high order terms of this expansion

(terms with (∆x)n, n = 2, 3, ...) usually become very small. Typically, we consider only the

first order term, i.e.,

f(x0 + ∆x) ≈ f(x0) + ∆xdf

dx

∣

∣

∣

∣

∣

x=x0

The Taylor series expansion can be similarly applied to function of two or more variables

such as f(x, y):

f(x0 + ∆x, y0 + ∆y) ≈ f(x0, y0) + ∆x∂f

∂x

∣

∣

∣

∣

∣

x0,y0

+ ∆y∂f

∂y

∣

∣

∣

∣

∣

x0,y0

In a BJT, there are four parameters of interest: iB, iC , vBE , and vCE . The BJT iv charac-

teristics plots, specify two of the above parameters, vBE and iC in terms of the other two,

iB and vCE, i.e., vBE is a function of iB and vCE (written as vBE(iB, vCE) similar to f(x, y))

and iC is a function of iB and vCE , iC(iB, vCE).

Let’s assume that BJT is biased and the Q point parameters are IB, IC , VBE and VCE. We

now apply a small AC signal to the BJT. This small AC signal changes vCE and iB by small

values around the Q point:

iB = IB + ∆iB vCE = VCE + ∆vCE

The AC changes, ∆iB and ∆vCE results in AC changes in vBE and iC that can be found

from Taylor series expansion in the neighborhood of the Q point, similar to expansion of

f(x0 + ∆x, y0 + ∆y) above:

vBE(IB + ∆iB, VCE + ∆vCE) = VBE +∂vBE

∂iB

∣

∣

∣

∣

∣

Q

∆iB +∂vBE

∂vCE

∣

∣

∣

∣

∣

Q

∆vCE

iC(IB + ∆iB, VCE + ∆vCE) = IC +∂iC∂iB

∣

∣

∣

∣

∣

Q

∆iB +∂iC

∂vCE

∣

∣

∣

∣

∣

Q

∆vCE


where all partial derivatives are calculated at the Q point and we have noted that at the Q

point, vBE(IB, VCE) = VBE and iC(IB, VCE) = IC . We denote the AC changes in vBE and iCas ∆vBE and ∆iC , respectively:

vBE(IB + ∆iB, VCE + ∆vCE) = VBE + ∆vBE

iC(IB + ∆iB, VCE + ∆vCE) = IC + ∆iC

So, by applying a small AC signal, we have changed iB and vCE by small amounts, ∆iB and

∆vCE , and BJT has responded by changing , vBE and iC by small AC amounts, ∆vBE and

∆iC . From the above two sets of equations we can find the BJT response to AC signals:

∆vBE =∂vBE

∂iB∆iB +

∂vBE

∂vCE

∆vCE , ∆iC =∂iC∂iB

∆iB +∂iC

∂vCE

∆vCE

where the partial derivatives are the slope of the iv curves near the Q point. We define

hie ≡∂vBE

∂iB, hre ≡

∂vBE

∂vCE

, hfe ≡∂iC∂iB

, hoe ≡∂iC

∂vCE

Thus, response of BJT to small signals can be written as:

∆vBE = hie∆iB + hre∆vCE ∆iC = hfe∆iB + hoe∆vCE

which is our small-signal model for BJT.

We now need to relate the above analytical model to circuit elements so that we can solve

BJT circuits. Consider the expression for ∆vBE

∆vBE = hie∆iB + hre∆vCE

Each term on the right hand side should have units of Volts. Thus, hie should have units of

resistance and hre should have no units (these are consistent with the definitions of hie and

hre). Furthermore, the above equation is like a KVL: the voltage drop between the base and

emitter (∆vBE) is equal to the sum of voltage drops across two elements. The voltage drop

across the first element is hie∆iB. So, it is a resistor with a value of hie. The voltage drop

across the second element is hre∆vCE . Thus, it is a dependent voltage source.

ie ∆V = h iB1∆iΒ

∆ΒΕ

v ∆re2 CEV = h v−+

∆iΒ

∆re CEh v∆ΒΕ

v

ieh

E

B+

−

+

−

+

+

−

−E

B


Now consider the expression for ∆iC :

∆iC = hfe∆iB + hoe∆vCE

Each term on the right hand side should have units of Amperes. Thus, hfe should have no

units and hoe should have units of conductance (these are consistent with the definitions of

hoe and hfe.) Furthermore, the above equation is like a KCL: the collector current (∆iC)

is equal to the sum of two currents. The current in first element is hfe∆iB. So, it is a

dependent current source. The current in the second element is proportional to hoe/∆vCE .

So it is a resistor with the value of 1/hoe.

i∆C

i = h i∆1 fe B

∆CE

v

2i = hoe∆CE

v

∆ Bfeh i

1/hoe

i∆C

∆CE

v

E

C

−

+

E

C+

−

Now, if put the models for BE and CE terminals together we arrive at the small signal

“hybrid” model for BJT. It is similar to the hybrid model for a two-port network.

Bfeh i

1/hoe

i∆C

-+ ∆

CEv∆

BEv ∆reh vCE

∆

_

+

B

E

C

-

+

E

Biehi∆

The small-signal model is mathematically valid only for signals with small amplitudes. But

this model is so useful that is often used for signals with amplitudes approaching those of

Q-point parameters by using average values of “h” parameters. “h” parameters are given in

the manufacturer’s spec sheets for each BJT. It should not be surprising to note that even in

a given BJT, “h” parameter can vary substantially depending on manufacturing statistics,

operating temperature, etc. Manufacturer’s’ spec sheets list these “h” parameters and give

the minimum and maximum values. Traditionally, the geometric mean of the minimum and

maximum values are used as the average value in design (see the table below).

Since hfe = ∂iC/∂iB and BJT β = iC/iB, β is sometimes called hFE in manufacturers’ spec

sheets and has a value quite close to hfe. In most electronic text books, β, hFE and hfe are

used interchangeably.


Typical hybrid parameters of a general-purpose 2N3904 NPN BJT

Minimum Maximum Average*

rπ = hie (kΩ) 1 10 3

hre 0.5 × 10−4 8 × 10−4 2 × 10−4

β ≈ hfe 100 400 200

hoe (µS) 1 40 6

ro = 1/hoe (kΩ) 25 1,000 150

re = hie/hfe (Ω) 10 25 15

* Geometric mean.

As hre is small, it is usually ignored in analytical calculations as it makes analysis much

simpler. This model, called the hybrid-π model, is most often used in analyzing BJT circuits.

In order to distinguish this model from the hybrid model, most electronic text books use a

different notation for various elements of the hybrid-π model:

rπ = hie ro =1

hoe

β = hfe

∆ Bfeh i

1/hoe

i∆C

i∆B

ieh∆BE

v

CB+

_

E

i∆C

i∆B

CB+

_

E

∆v

∆ Bβ iroπrBE=⇒

The above hybrid-π model includes a current-controlled current source. A variant of the

hybrid-π model can be developed which includes a voltage-controlled current source by noting

(∆vBE = rπ∆iB:

i∆C

i∆B

ro

∆m BEg v

πr∆BE

v

CB

E

+

_

β∆iB = β∆vBE

rπ

= gm∆vBE

gm ≡ β

rπ

Transfer conductance

re ≡1

gm

=rπ

βEmitter resistance


6.5 FET Small Signal Model

Similar to the BJT, the simple large-signal model of FET (page 127) is sufficient for finding

the bias point; but we need to develop a more accurate model for analysis of AC signals.

The main issue is that the FET large signal model indicates that iD only depends on vGS

and is independent of vDS in the active state. In reality, iD increases slightly with vDS in

the active state.

We can develop a small signal model for FET in a manner similar to the procedure described

in detail for the BJT. The FET characteristics equations specify two of the FET parameters,

iG and iD, in terms of the other two, vGS and vDS. (Actually FET is simpler than BJT as

iG = 0 at all times.) As before, we write the FET parameters as a sum of DC bias value

and a small AC signal, e.g., iD = ID + ∆iD. Performing a Taylor series expansion, similar

to pages 169 and 170, we get:

iG(VGS + ∆vGS, VDS + ∆vDS) = 0

iD(VGS + ∆vGS, VDS + ∆vDS) = iD(VGS, VDS) +∂iD∂vGS

∣

∣

∣

∣

∣

Q

∆vGS +∂iD∂vDS

∣

∣

∣

∣

∣

Q

∆vDS

Since iG(VGS +∆vGS , VDS +∆vDS) = IG+∆iG and iD(VGS +∆vGS, VDS +∆vDS) = ID +∆iD,

we find the AC components to be:

∆iG = 0 and ∆iD =∂iD∂vGS

∣

∣

∣

∣

∣

Q

∆vGS +∂iD∂vDS

∣

∣

∣

∣

∣

Q

∆vDS

Defining

gm ≡ ∂iD∂vGS

and ro ≡∂iD∂vDS

We get:

∆iG = 0 and ∆iD = gm∆vGS + ro∆vDS

∆vGS

∆mg vGS

∆Gi = 0

ro

∆iD

_

+

G D

S

This results in the hybrid-π model for

the FET as is shown. Note that the

FET hybrid-π model is similar to the BJT

hybrid-π model with rπ → ∞.


6.6 BJT Amplifier Circuits

As we have developed different models for DC signals (simple large-signal model) and AC

signals (small-signal model), analysis of BJT circuits follows these steps:

DC biasing analysis: Assume all capacitors are open circuit. Analyze the transistor circuit

using the simple large signal mode as described in page 114.

AC analysis:

1) Kill all DC sources

2) Assume coupling capacitors are short circuit. The effect of these capacitors is to set a

lower cut-off frequency for the circuit. This is analyzed in the last step.

3) Inspect the circuit. If you identify the circuit as a prototype circuit, you can directly use

the formulas for that circuit. Otherwise go to step 4.

4) Replace the BJT with its small signal model.

5) Solve for voltage and current transfer functions and input and output impedances (node-

voltage method is the best).

6) Compute the cut-off frequency of the amplifier circuit.

Several standard BJT amplifier configurations are discussed below and are analyzed. For

completeness, circuits include standard bias resistors R1 and R2. For bias configurations

that do not utilize these resistors (e.g., current mirror), simply set RB = R1 ‖ R2 → ∞.

6.6.1 Common Collector Amplifier (Emitter Follower)

RER2

VCC

vi

vo

R1

cC

DC analysis: With the capacitors open circuit, this circuit is the

same as our good biasing circuit of page 162 with RC = 0. The

bias point currents and voltages can be found using procedure

of pages 162-164.

AC analysis: To start the analysis, we kill all DC sources:

RE

vo

R1R2

vi

RER2

vi

vo

R1

CCV = 0

cC C

E

cC

B


We can combine R1 and R2 into RB (same resistance that we encountered in the biasing

analysis) and replace the BJT with its small signal model:

vi

RBRE

i∆B

ovvi

i∆C

i∆B

vo

RE

Cc

∆BE

v

Cc

rπ

rπ

ro ro

β ∆ B

β ∆ B

B

C

E

RB

C+

_

B

E

i

i

The figure above shows why this is a common collector configuration: the collector is common

between the input and output AC signals. We can now proceed with the analysis. Node

voltage method is usually the best approach to solve these circuits. For example, the above

circuit has only one node equation for node at point E with a voltage vo:

vo − vi

rπ

+vo − 0

ro

− β∆iB +vo − 0

RE

= 0

Because of the controlled source, we need to write an “auxiliary” equation relating the control

current (∆iB) to node voltages:

∆iB =vi − vo

rπ

Substituting the expression for ∆iB in our node equation, multiplying both sides by rπ, and

collecting terms, we get:

vi(1 + β) = vo

[

1 + β + rπ

(

1

ro

+1

RE

)]

= vo

[

1 + β +rπ

ro ‖ RE

]

Amplifier Gain can now be directly calculated:

Av ≡ vo

vi

=1

1 +rπ

(1 + β)(ro ‖ RE)

Unless RE is very small (tens of Ω), the fraction in the denominator is quite small compared

to 1 and Av ≈ 1.

To find the input impedance, we calculate ii by KCL:

ii = i1 + ∆iB =vi

RB

+vi − vo

rπ


Since vo ≈ vi, we have ii = vi/RB or

Ri ≡vi

ii= RB

Note that RB is the combination of our biasing resistors R1 and R2. With alternative biasing

schemes which do not require R1 and R2 (and, therefore, RB → ∞), the input resistance of

the emitter follower circuit will become large. In this case, we cannot use vo ≈ vi. Using the

full expression for vo from above, the input resistance of the emitter follower circuit becomes:

Ri ≡vi

ii= RB ‖ [rπ + (RE ‖ ro)(1 + β)]

which is quite large (hundreds of kΩ to several MΩ) for RB → ∞. Such a circuit is in fact

the first stage of the 741 OpAmp.

The output resistance of the common collector amplifier (in fact for all transistor amplifiers)

is somewhat complicated because the load can be configured in two ways (see figure): First,

RE, itself, is the load. This is the case when the common collector is used as a “current

amplifier” to raise the power level and to drive the load. The output resistance of the circuit

is Ro as is shown in the circuit model. This is usually the case when values of Ro and Ai

(current gain) is quoted in electronic text books.

R2

VCC

vi

vo

RL

R1

Cc

E

=RE

R is the Load

RER2

VCC

vi

vo

R1

Cc

RL

Separate Load

vi

RB

i∆B

ov

RE

Ro

Cc B

C

Eπr

ro

β∆ Bi

vi

RB

i∆B

Cc

RE

oR’

B

C

Eπr

ro

β∆ B

ov

RL

i

Alternatively, the load can be placed in parallel to RE. This is done when the common

collector amplifier is used as a buffer (Av ≈ 1, Ri large). In this case, the output resistance

is denoted by R′

o (see figure). For this circuit, BJT sees a resistance of RE ‖ RL. Obviously,

if we want the load not to affect the emitter follower circuit, we should use RL to be much


larger than RE. In this case, little current flows in RL which is fine because we are using

this configuration as a buffer and not to amplify the current and power. As such, value of

R′

o or Ai does not have much use.

vi

RB

i∆B

iT

vT

Cc

β∆ B

Ro

ro

B rπ E

C

i+−

When RE is the load, the output resistance can

be found by killing the source (short vi) and find-

ing the Thevenin resistance of the two-terminal

network (using a test voltage source).

KCL: iT = −∆iB +vT

ro

− β∆iB

KVL (outside loop): − rπ∆iB = vT

Substituting for ∆iB from the 2nd equation in the first and rearranging terms we get:

Ro ≡vT

iT=

(ro) rπ

(1 + β)(ro) + rπ

Since, (1 + β)(ro) rπ, the expression for Ro simplifies to

Ro ≈(ro) rπ

(1 + β)(ro)=

rπ

(1 + β)≈ rπ

β= re

As mentioned above, when RE is the load the common collector is used as a “current ampli-

fier” to raise the current and power levels . This can be seen by checking the current gain

in this amplifier: io = vo/RE, ii ≈ vi/RB and

Ai ≡ioii

=RB

RE

vi

RB

i∆B

Cc

β∆ Bro RE

iT

vT

R’o

B rπ E

C

i+−

vi

RB

i∆B

iT

vT

Cc

β∆ Br’o

R’o

B rπ E

C

i+−

We can calculate R′

o, the output resistance

when an additional load is attached to the cir-

cuit (i.e., RE is not the load) with a similar

procedure: we need to find the Thevenin re-

sistance of the two-terminal network (using a

test voltage source).

We can use our previous results by noting that

we can replace ro and RE with r′o = ro ‖ RE

which results in a circuit similar to the case

with no RL. Therefore, R′

o has a similar ex-

pression as Ro if we replace ro with r′o:


R′

o ≡vT

iT=

(r′o) rπ

(1 + β)(r′o) + rπ

In most circuits, (1 + β)(r′o) rπ (unless we choose a small value for RE) and R′

o ≈ re

In summary, the general properties of the common collector amplifier (emitter follower)

include a voltage gain of unity (Av ≈ 1), a very large input resistance Ri ≈ RB (and can

be made much larger with alternate biasing schemes). This circuit can be used as buffer for

matching impedance, at the first stage of an amplifier to provide very large input resistance

(such in 741 OpAmp). The common collector amplifier can be also used as the last stage

of some amplifier system to amplify the current (and thus, power) and drive a load. In this

case, RE is the load, Ro is small: Ro = re and current gain can be substantial: Ai = RB/RE.

Impact of Coupling Capacitor:

Up to now, we have neglected the impact of the coupling capacitor in the circuit (assumed

it was a short circuit). This is not a correct assumption at low frequencies. The coupling

capacitor results in a lower cut-off frequency for the transistor amplifiers. In order to find the

cut-off frequency, we need to repeat the above analysis and include the coupling capacitor

impedance in the calculation. In most cases, however, the impact of the coupling capacitor

and the lower cut-off frequency can be deduced be examining the amplifier circuit model.

+− V L

oI

o

+

−

i

i

+

−

o

AVi

i

V’

c

Voltage Amplifier Model

C

ZR

+−

V

RConsider our general model for any

amplifier circuit. If we assume that

coupling capacitor is short circuit

(similar to our AC analysis of BJT

amplifier), v′

i = vi.

When we account for impedance of the capacitor, we have set up a high pass filter in the

input part of the circuit (combination of the coupling capacitor and the input resistance of

the amplifier). This combination introduces a lower cut-off frequency for our amplifier which

is the same as the cut-off frequency of the high-pass filter:

ωl = 2π fl =1

RiCc

Lastly, our small signal model is a low-frequency model. As such, our analysis indicates

that the amplifier has no upper cut-off frequency (which is not true). At high frequencies,

the capacitance between BE , BC, CE layers become important and a high-frequency small-

signal model for BJT should be used for analysis. You will see these models in upper division


courses. Basically, these capacitances results in amplifier gain to drop at high frequencies.

PSpice includes a high-frequency model for BJT, so your simulation should show the upper

cut-off frequency for BJT amplifiers.

6.6.2 Common Emitter Amplifier

RC

VCC

R1

vo

viCc

R2

RC

VCC

R1

vo

viCc

C bRE

R2

Good Bias using aby−pass capacitorPoor Bias

DC analysis: Recall that an emitter resis-

tor is necessary to provide stability of the

bias point. As such, the circuit configura-

tion as is shown has as a poor bias. We

need to include RE for good biasing (DC

signals) and eliminate it for the AC sig-

nals. The solution is to include an emitter

resistance and use a “bypass” capacitor to

short it out for AC signals as is shown.

For this new circuit and with the capacitors open circuit, this circuit is the same as our

good biasing circuit of page 162. The bias point currents and voltages can be found using

procedure of pages 162-164.

AC analysis: To start the analysis, we kill all DC sources, short out Cb (which shorts out

RE), combine R1 and R2 into RB, and replace the BJT with its small signal model. We

see that the emitter is now common between the input and output AC signals (thus, the

common emitter amplifier). Examination of the circuit shows that:

vi

RB

i∆B

ovCc

Ro

RC

R’o

B

E

C

rπ

β∆ B

orivi = rπ∆iB vo = −(RC ‖ ro) β∆iB

Av ≡ vo

vi

= − β

rπ

(RC ‖ ro) ≈ − β

rπ

RC = − RC

re

Ri = RB ‖ rπ

The negative sign in Av indicates a 180 phase shift between the input and output signals.

This circuit has a large voltage gain but has a medium value for the input resistance.

As with the emitter follower circuit, the load can be configured in two ways: 1) RC is the

load; or 2) the load is placed in parallel to RC . The output resistance can be found by killing

the source (short vi) and finding the Thevenin resistance of the two-terminal network. For

this circuit, we see that if vi = 0 (killing the source), ∆iB = 0. In this case, the strength of


the dependent current source would be zero and this element would become an open circuit.

Therefore,

Ro = ro R′

o = RC ‖ ro

Lower cut-off frequency: Both the coupling and bypass capacitors contribute to setting

the lower cut-off frequency for this amplifier, both act as a high-pass filter with:

ωl(coupling) = 2π fl =1

RiCc

ωl(bypass) = 2π fl =1

R′

ECb

where R′

E ≡ RE ‖ re

Note that usually RE re and, therefore, R′

E ≈ re.

In the case when these two frequencies are far apart, the cut-off frequency of the amplifier

is set by the “larger” cut-off frequency. i.e.,

ωl(bypass) ωl(coupling) → ωl = 2π fl =1

RiCc

ωl(coupling) ωl(bypass) → ωl = 2π fl =1

R′

ECb

When the two frequencies are close to each other, there is no exact analytical formulas, the

cut-off frequency should be found from simulations. An approximate formula for the cut-off

frequency (accurate within a factor of two and exact at the limits) is:

ωl = 2π fl ≈1

RiCc

+1

R′

ECb


6.6.3 Common Emitter Amplifier with Emitter resistance

R1 RC

R2

Cc

vi

RE

vo

VCCA problem with the common emitter amplifier is that its gain

depend on BJT parameters: Av ≈ (β/rπ)RC . Some form of

feedback is necessary to ensure stable gain for this amplifier.

One way to achieve this is to add an emitter resistance. Recall

impact of negative feedback on OpAmp circuits: we traded gain

for stability of the output. Same principles apply here.

DC analysis: With the capacitors open circuit, this circuit is the

same as our good biasing circuit of page 162. The bias point

currents and voltages can be found using procedure of pages

162-164.

AC analysis: To start the analysis, we kill all DC sources, combine R1 and R2 into RB and

replace the BJT with its small signal model. Analysis is straight forward using node-voltage

method.1Cvi

i∆C

i∆B vo

∆BE

v

RE

RC

RB

+

_

B

E

C

πrβ∆ B

ro

ivE − vi

rπ

+vE

RE

− β∆iB +vE − vo

ro

= 0

vo

RC

+vo − vE

ro

+ β∆iB = 0

∆iB =vi − vE

rπ

(Controlled source aux. Eq.)

Substituting for ∆iB in the node equations and noting 1 + β ≈ β, we get :

vE

RE

+ βvE − vi

rπ

+vE − vo

ro

= 0

vo

RC

+vo − vE

ro

− βvE − vi

rπ

= 0

Above are two equations in two unknowns (vE and vo). Adding the two equation together

we get vE = −(RE/RC)vo and substituting that in either equations we can find vo. Using

rπ/β = re, we get:

Av =vo

vi

=RC

re(1 + RC/ro) + RE(1 + re/ro)≈ RC

re(1 + RC/ro) + RE

where we have simplified the equation noting re ro. For most circuits, RC ro and

re RE. In this case, the voltage gain is simply Av = −RC/RE.


The input resistance of the circuit can be found from (prove it!)

Ri = RB ‖ vi

∆iB

Noting that ∆iB = (vi − vE)/rπ and vE = −(RE/RC)vo = −(RE/RC)Avvi, we get:

Ri = RB ‖ rπ

1 + AvRC/RE

Substituting for Av from above (complete expression for Av with re/ro 1), we get:

Ri = RB ‖[

β

(

RE

1 + RC/ro

+ re

)]

For most circuits, RC ro and re RE. In this case, the input resistance is simply

Ri = RB ‖ (βRE).

As before the minus sign in Av indicates a 180 phase shift between input and output

signals. Note the impact of negative feedback introduced by the emitter resistance: The

voltage gain is independent of BJT parameters and is set by RC and RE (recall OpAmp

inverting amplifier!). The input resistance is also increased dramatically.

i∆B

RE

vT

iT

i1

i2

Ro

B

E

πrβ∆ B

ro

C

i

+−

i∆B

RE

RC

vT

iT

R’o

i1

i2

B

E

πrβ∆ B

ro

C

i

+−

As with the emitter follower circuit, the load can

be configured in two ways: 1) RC is the load. 2)

Load is placed in parallel to RC . The output re-

sistance can be found by killing the source (short

vi) and finding the Thevenin resistance of the

two-terminal network (by attaching a test voltage

source to the circuit).

Resistor RB drops out of the circuit because it is

shorted out. Resistors rπ and RE are in parallel.

Therefore, i1 = (rπ/RE)∆iB and by KCL, i2 =

(β + 1 + rπ/RE)∆iB. Then:

iT = −∆iB − i1 = −∆iB

(

1 +rπ

RE

)

vT = −∆iBrπ − i2ro = −∆iB

[

ro

(

β + 1 +rπ

RE

)

+ rπ

]

Then:

Ro =vT

iT= ro + RE × 1 + ro/re

1 + RE/rπ


where we have used rπ/β = re. Generally ro re (first approximation below) and for most

circuit, RE rπ (second approximation) leading to

Ro ≈ ro + ro ×RE/re

1 + RE/rπ

≈ ro +REro

re

= ro

(

RE

re

+ 1)

Value of R′

o can be found by a similar procedure. Alternatively, examination of the circuit

shows that

R′

o = RC ‖ Ro ≈ RC

Lower cut-off frequency: The coupling capacitor together with the input resistance of

the amplifier lead to a lower cut-off frequency for this amplifier (similar to emitter follower).

The lower cut-off frequency is given by:

ωl = 2π fl =1

RiCc

R1 RC

Cc

vi

vo

VCC

R2 RE1

CbRE2

A Possible Biasing Problem: The gain of the common

emitter amplifier with the emitter resistance is approximately

RC/RE. For cases when a high gain (gains larger than 5-10) is

needed, RE may be become so small that the necessary good

biasing condition, VE = REIE > 1 V cannot be fulfilled. The

solution is to use a by-pass capacitor as is shown. The AC signal

sees an emitter resistance of RE1 while for DC signal the emitter

resistance is the larger value of RE = RE1 +RE2. Obviously for-

mulas for common emitter amplifier with emitter resistance can

be applied here by replacing RE with RE1 as in deriving the am-

plifier gain, and input and output impedances, we “short” the

bypass capacitor so RE2 is effectively removed from the circuit.

The addition of by-pass capacitor, however, modifies the lower cut-off frequency of the circuit.

Similar to a regular common emitter amplifier with no emitter resistance, both the coupling

and bypass capacitors contribute to setting the lower cut-off frequency for this amplifier.

Similarly we find that an approximate formula for the cut-off frequency (accurate within a

factor of two and exact at the limits) is:

ωl = 2π fl =1

RiCc

+1

R′

ECb

where R′

E ≡ RE2 ‖ (RE1 + re)


6.6.4 Common Base Amplifier

RC

VCC

RE

−VEE

Cc

vi

vo

By setting the signal ground at the base of the BJT, one arrives

at the common base amplifier (the input sginal is still applied

between the base and the emitter). While it is possible to bias

this configuration with a voltage divider self-bias, the preferred

method is to bias this amplifier with two power supplies (or a

current mirror). The bias point currents and voltages can be

found using procedure of pages 164-165.

AC analysis: To start the analysis, we kill all DC sources and

replace the BJT with its small signal model. We see that base

is now common between the input and output AC signals (thus,

the common base amplifier).

i∆B

∆ B

RC

RE

vi

cC

voB

E

C

πrβ i

ro

vi

cC

∆ B

vo

RCREi∆B

E C

B

ii

β i

roπr

=⇒

Using node voltage method and noting ∆iB = −vi/rπ:

vo

RC

+ β∆iB +vo − vi

ro

= 0

vo

(

1

RC

+1

ro

)

+ vi

(

− β

rπ

− 1

ro

)

= 0

vo

1

RC ‖ ro

≈ vi

β

rπ

Av ≡ vo

vi

=β

rπ

(RC ‖ ro) ≈β

rπ

RC =RC

re

which is exactly the gain of the common emitter amplifier (with no emitter resistor) except

for the positive sign. This should not be surprising as compared to a common emitter, we

have switched the terminals of the input signal (leading to the change in the sign of Av) and

the output voltage is vCB = vCE − vBE ≈ vCE because of the high gain of the amplifier.


The input resistance of the circuit can be found by finding ii from the circuit above and

computing vi/ii to be

Ri =rπ(ro + RC)

rπ + RC + ro(1 + β)≈ rπ(ro + RC)

ro(1 + β)≈ rπ

1 + β≈ rπ

β= re

In the approximation, we first used the fact that rπ + RC ro(1 + β) and then RC ro.

Note that the input resistance is quite small.

As before, the load can be configured in two ways: 1) RC is the load; or 2) load is placed

in parallel to RC . The output resistance can be found by killing the source (short vi) and

finding the Thevenin resistance of the two-terminal network. For this circuit, we see that

if vi = 0 (killing the source), ∆iB = 0. In this case, the strength of the dependent current

source would be zero and this element would become an open circuit. In addition, emitter

would be effectively grounded and resistors RE and rπ are effectively shorted out of the

circuit. Therefore,

Ro = ro R′

o = RC ‖ ro ≈ RC

which are similar to the common amplifier with no emitter resistor.

As a whole, this circuit is similar to common emitter amplifier with no resistor (large voltage

gain, medium output resistance) but has a very low input resistance (re). As such, it is

rarely used as a voltage amplifier (except for very specialized cases).

Following the formula in page 13, the short circuit current-gain of this amplifier is:

Ai =ZI

ZL + Zo

Av =re

0 + Rc

RC

re

= 1

Therefore, this circuit has a low input resistance, a medium output resistance and current-

gain of unity and, therefore, is a “current buffer”: It accepts an input signal current with

a low input resistance and deliver nearly equal current to a much higher output resistance.

Common-base amplifiers are mostly used as a current buffer, typically forming circuits in-

cluding two BJTs (cascode amplifier) which are utilized specially in integrated circuits.


6.7 FET Amplifier Circuits

As expected, FET amplifiers are very similar to the BJT amplifiers. There are four basic

FET amplifiers: 1) common-drain or source follower (similar to common collector or emitter

follower), 2) common-source (similar to common emitter), 3) common source with a source

resistor (similar to common emitter with an emitter resistor) and common gate (similar to

common base).

The analysis technique are exactly the same: 1) DC-biasing analysis, and 2) AC analysis in

which we replace FET with its small signal model. In fact, by comparing the small signal

model for an FET that that of a BJT, we should be able to find the answer immediately by

replacing β/rπ = gm in the formulas of the equivalent BJT circuits and then let rπ → ∞ (and

of course, replace RC → RD, RE → RS, and RB = R1 ‖ R2 → RG = R1 ‖ R2). Therefore,

we will only solve the common-source amplifier in detail and summarize the results for the

other configurations.

6.7.1 Common Source Amplifier

R1

vo

viCc

R2

R1

vo

viCc

C b

R2

RD RD

RS

VDD VDD

Good Bias using aby−pass capacitorPoor Bias

DC analysis: Recall that a source resistor

is necessary to provide stability for the bias

point. As such, the circuit configuration as

is shown has a poor bias. We need to in-

clude RS for good biasing (DC signals) and

eliminate it for AC signals. The solution

is to include a source resistance and use a

“bypass” capacitor to short it out for AC

signals similar to the BJT common-emitter

amplifier.

AC analysis: To start the analysis, we kill all DC sources, short out Cb (which shorts out

RS), combine R1 and R2 into RG, and replace the FET with its small signal model. We see

that the source is now common between the input and output AC signals (thus, the common

source amplifier). Examination of the circuit shows that:

∆Gi = 0

∆vGS

∆mg vGS

ro

vi

RG

Ro R’o

voCc

RD_

+

S

DG

vi = ∆vGS vo = −(RD ‖ ro) gm∆vGS

Av ≡ vo

vi

= −gm(RD ‖ ro) ≈ −gmRD

Ri = RG

Ro = ro R′

o = RD ‖ ro


which are exactly the same as formulas for a BJT common emitter amplifier if we let β/rπ =

gm and rπ → ∞. Note that as an FET can be biased with large (MΩ) R1 and R2 (see

page 167), the input resistance of this amplifier is considerably larger than that of a common

emitter amplifier and can even be made to be infinitely large (resistance of the Gate insulator)

by removing RG and biasing the circuit with two voltage supplies or a current mirror.

Lower cut-off frequency: As Ri is very large, the lower cut-off frequency is set by the

bypass capacitor (unless Cc is chosen to be very small) .

ωl = ωl(bypass) = 2π fl =1

R′

SCb

where R′

S ≡ RS ‖ 1

gm

Note that usually RS 1/gm and, therefore, R′

S ≈ 1/gm.

6.7.2 Common Source Amplifier with Source resistance

R1

vo

viCc

RD

VDD

RSR2

Similar to common-emitter amplifier, the common source am-

plifier gain depends on the FET parameters (gm). Addition of

a source resistance will remove this dependency (similar to the

common emitter amplifier with an emitter resistor). Details of

the AC analysis is left as an exercise. The parameters of this

amplifier are:

Av = − gmRD

1 + gmRS

≈ − RD

RS

Ri = RG

Ro = 1/gm ‖ ro R′

o = RD ‖ Ro ≈ RD

ωl = 2π fl =1

RiCc

Similar to the common-emitter amplifier, the gain is set by RD and RS and is independent of

the FET parameters. The input resistance of the circuit is large (much larger than common

emitter amplifier because R1 and R2 can be large).


6.7.3 Common Drain Amplifier

R1

viCc

R2RS

vo

VDDThis circuit is similar to the common-collector amplifier (or the

emitter follower). Details of the AC analysis is left as an exercise.

The parameters of this amplifier are:

Av =gmroRS

ro + (1 + gmro)RS

≈ 1

Ri = RG


o = RS ‖ Ro ≈ RS

ωl = 2π fl =1

RiCc

Similar to the emitter follower, the source follower is a voltage buffer. It is superior to the

emitter follower because of its very large input resistance.

6.7.4 Common Gate Amplifier

Cc

vi

vo

RD

RS

VDD

−VSS

This circuit is similar to the BJT common-base amplifier. De-

tails of the AC analysis is left as an exercise. The parameters of

this amplifier are:

Av = −gm(RD ‖ ro) ≈ −gmRD

Ri =RS(ro + RD)

ro + RD + (1 + gmro)RS

≈ RS(ro + RD)

(1 + gmro)RS

≈ ro

gmro

=1

gm

Ro = ro R′

o = RD ‖ ro ≈ RD

ωl = 2π fl =1

RiCc

Note that in the approximation for Ri, we first used the fact that ro + RD (1 + gmro)RS

and then RD ro.

Similar to the common-base amplifier, this is a poor voltage amplifier because of its low input

resistance but has a short-circuit current gain of unity, low input impedance, and medium

output impedance and can be used as a current buffer.


Summary of Transistor Amplifiers?

RER2

VCC

vi

vo

R1

cC

Common Collector (Emitter Follower):

Av =(RE ‖ ro)(1 + β)

rπ + (RE ‖ ro)(1 + β)≈ 1

Ri = RB ‖ [rπ + (RE ‖ ro)(1 + β)] ≈ RB

Ro =(ro) rπ

(1 + β)(ro) + rπ

≈ rπ

β= re 2π fl =

1

RiCc

R′

o =(r′o) rπ

(1 + β)(r′o) + rπ

≈ rπ

βwhere ro = ro ‖ RC

C

VCC

R1

R2

vo

viCc

C b

R

RE

Common Emitter:

Av = − β

rπ

(RC ‖ ro) ≈ − β

rπ

RC = − RC

re

Ri = RB ‖ rπ

Ro = ro R′

o = RC ‖ ro ≈ RC

2π fl =1

RiCc

+1

R′

ECb

where R′

E ≡ RE ‖ re

Common Emitter with Emitter Resistance:

R1 RC

R2

Cc

vi

RE

vo

VCC

Av = − RC

re(1 + RC/ro) + RE

≈ − RC

re + RE

≈ − RC

RE

Ri = RB ‖[

β

(

RE

1 + RC/ro

+ re

)]

≈ RB ‖ βRE ≈ RB

Ro ≈ ro + ro ×RE/re

1 + RE/rπ

≈ ro

(

RE

re

+ 1)

R′

o = RC ‖ Ro ≈ RC and 2π fl =1

RiCc

Common Base Amplifer:RC

VCC

RE

−VEE

Cc

vi

voAv =β

rπ

(RC ‖ ro) ≈RC

re

Ri =rπ(ro + RC)

rπ + RC + ro(1 + β)≈ re

Ro = ro R′

o = RC ‖ ro ≈ RC and 2π fl =1

RiCc


R1

viCc

R2RS

vo

VDD

Common Drain (Source Follower):

Av =gmroRS

ro + (1 + gmro)RS

≈ 1

Ri = RG


o = RS ‖ Ro ≈ RS

ωl = 2π fl =1

RiCc

R1

vo

viCc

C b

R2

RD

RS

VDD

Common Source:


Ri = RG

Ro = ro R′

o = RD ‖ ro

ωl = ωl(bypass) = 2π fl =1

R′

SCb

where R′

S ≡ RS ‖ 1

gm

Common Source with Source Resistance:R1

vo

viCc

RD

VDD

RSR2

Av = − gmRD

1 + gmRS

≈ −RD

RS

Ri = RG


o = RD ‖ Ro ≈ RD

ωl = 2π fl =1

RiCc

Common Gate Amplifer:

Cc

vi

vo

RD

RS

VDD

−VSS


Ri =RS(ro + RD)

ro + RD + (1 + gmro)RS

≈ 1

gm

Ro = ro R′

o = RD ‖ ro ≈ RD

ωl = 2π fl =1

RiCc

?If bias resistors are not present (e.g., bias with current mirror), let RB or RG → ∞ in the

“full” expression for Ri.


6.8 Exercise Problems

In circuit design, use 5% commercial resistor and capacitor values (1, 1.1, 1.2, 1.3, 1.5, 1.6,

1.8, 2, 2.2, 2.4, 2.7, 3., 3.3, 3.6, 3.9, 4.3, 4.7, 5.1, 5.6, 6.2, 6.8, 7.5, 8.2, 9.1 × 10n where n is

an integer). Use Si BJTs, with β = 200, βmin = 100, rπ = 5 kΩ, ro = 100 kΩ.

Problem 1. Show that this circuit is a stable biasing scheme.

Problem 2 to 5. Compute Io assuming identical transistors.

Problem 6 to 8: Find the bias point and AC amplifier parameters of these circuits (Man-

ufacturers’ spec sheets give: β = 200, rπ = 5 kΩ, ro = 100 kΩ).

CI

RB

RC

VCC

I ref

Io

Q1 Q2

Q3

VCC

−VEE

IoI ref

Q1 Q2

−VSS

I refIo

Q1 Q2

Q3

−VEE

Problem 1 Problem 2 Problem 3 Problem 4

I refIo

Q1 Q2

Q3

−VSS

vo

vi

0.47 Fµ

18k

22k 1k

9 V

vi

vo

47 Fµ

µ4.7 F

270

240

15 V

34 k 1 k

5.9 k

vovi

16 V

1.5k

6.2k

510nF

30k

510


Problem 9: Design a BJT amplifier with a gain of 4 and a lower cut-off frequency of 100 Hz.

The Q point parameters should be IC = 3 mA and VCE = 7.5 V.

Problem 10: Design a BJT amplifier with a gain of 10 and a lower cut-off frequency of

100 Hz. The Q point parameters should be IC = 3 mA and VCE = 7.5 V. A power supply of

15 V is available.


Problem 11. Design a BJT amplifier with a gain of 5 and a lower cut-off frequency of 10 Hz,

powered by a 16 V supply. Set the Q-point parameters to be VCE = 10 V and Ic = 5 mA.

Problem 12. Consider the BJT circuit below with R1 = 47 kΩ, R2 = 39 kΩ, RE =

1.5 kΩ, RL = 50 kΩ, C1 = 100 nF, C2 = 0.47 µF, and VCC = 15 V. An input signal with

vi = cos(5000t) is applied to the circuit. Calculate expressions for voltages vB, vE, and vo

(include both AC and DC parts in the expression for each voltage). Manufacturers’ spec

sheets give: β = 200, rπ = 5 kΩ, ro = 100 kΩ.

Problems 13 to 16: Find the bias point and AC amplifier parameters of these circuits

(Manufacturers’ spec sheets give: β = 200, rπ = 5 kΩ, ro = 100 kΩ).

Problems 17. Find the bias point and AC amplifier parameters of these circuits (Manufac-

turers’ spec sheets give K = 0.25 mA/V2 and Vt = 1 V, gm = 0.25 mA/V, and ro = 100 kΩ).

Problems 18. Find the bias point and AC amplifier parameters of these circuits (Manufac-


Problem 19. Find the bias point and AC amplifier parameters of these circuits (Manufac-


1C

R1

R2 ER LR

2C

VCC

i vBEv o

v

v

vi

vo

47 Fµ

µ0.33 F

15 V

2 k39 k

5106.2 k 510

vo

vi

0.47 Fµ

18k

22k 1k

−9 V

vi vo

0.47 Fµ

18k

22k 1k

9 V


vo

vi

1k

4 V

−5 V

vi

vo

Cc

1k

110k 2k

51k

12 V

vi

vo

Cc

Cb1M

1k1M

1k

20 V

vivo

Cc

500k

1.3M10k

18 V



Problems 20 to 22: Find the bias point and AC amplifier parameters of these circuits


vivo

µ0.47 F

µ4.7 F

6.2k

Q1

33k

22k

18k

15 V

1k

Q2

2k

500

vi

voµ4.7 F

6.2k 500

15 V

1k

Q2

Q1

2k33k

vi

vo

µ4.7 F

Q1

5102.7k

18 V

510

Q2

1.5k3.6k15k

Problem 20 Problem 21 Problem 22


6.9 Solution to Selected Exercise Problems

Problem 1. Show that this is a stable biasing scheme.

This is another stable biasing scheme which eliminates RB thereby, greatly reducing the

input resistance and increasing the value of the coupling capacitor (or lowering the cut-off

frequency). This scheme uses Rc as the feedback resistor.

RB

CI

RC

1I

VCCWe assume that the BJT is in the active-linear state. Since IB IC ,

by KCL I1 = IC + IC ≈ IC . Then:

BE-KVL: VCC = RCIC + RBIB + VBE = (RC + RB/β) IC + VBE

IC =VCC − VBE

RC + RB/β

If, RB/β RC or RB βRC , we will have (setting VBE = Vγ):

IC =VCC − Vγ

RC

Since IC is independent of β, the bias point is stable. We still need to prove that the BJT

is in the active-linear state. We write a KVL through BE and CE terminals:

VCE = RBIB + VBE = RBIB + Vγ > Vγ

Since VCE > Vγ , BJT is indeed in the active state.

To see the negative feedback effect, rewrite BE-KVL as:

IB =VCC − Vγ − RCIC

RB

Suppose that the circuit is operating and BJT β is increased (e.g., an increase in the tem-

perature). In this case IC will increase which raises the voltage across resistor RC (RCIC).

From the above equation, this will lead to a reduction in IB which, in turn, will decrease

IC = βIB and compensate for any increase in β. If BJT β is decreased (e.g., a decrease

in the temperature), IC will decrease which reduces the voltage across resistor RC (RCIC).

From the above equation, this will lead to an increase in IB which, in turn, will increase

IC = βIB and compensate for any decrease in β.

Note: The drawback of this bias scheme is that the allowable AC signal on VCE is small.

Since VCE±∆VCE > Vγ in order for the BJT to remain in active state, we find the amplitude

of AC signal, ∆VCE < RBIB = (RB/β)IC . Since, RB/β RC for bias stability thus,

∆VCE RCIC . This is in contrast with the standard biasing with emitter resistor in which

∆VCE is comparable to RCIC . Also, there is a feedback for the AC signals.


Problem 2. Compute Io assuming identical transistors.

i C i C

i B i B

i B32iB

I ref

Io

Q1 Q2

Q3

V

−V

CC

EE

Because both bases and emitters of the transistors Q1 and Q2



and, therefore, similar iE = iE1 = iE2 and iC = iC1 = iC2.

Using iC = βiB and iE = (β + 1)iB to illustrate the impact

of β:

iB =iE

β + 1Io = iC =

βiEβ + 1

KCL: iE3 = 2iB =2iE

β + 1

iB3 =iE3

β + 1=

2iE(β + 1)2

KCL: Iref = iC + iB3 =βiE

β + 1+

2iE(β + 1)2

Io

Iref

=β

β + 2/(β + 1)=

1

1 + 2/β(β + 1)≈ 1

1 + 2/β2

As can be seen, this is a better current mirror than our simple version as Io ≈ Iref with an

accuracy of 2/β2. Similar to our simple current-mirror circuit, Iref can be set by using a

resistor Rc.


IoI ref

Q1 Q2

−VSS

This is the MOS version of our simple current mirror. Be-

cause both gates and sources of the transistors Q1 and Q2

are connected together, KVL leads to vGS1 = vGS2. The

drain of Q1 is connected to its gate: vDS1 = vGS1. Therefore,

vDS1 = vGS1 > vGS1 − Vt, Q1 will be in the active state with

Iref = iD1 = K(vGS1 −Vt)2. If Q2 is also in active state, then

Io = iD2 = K(vGS2−Vt)2. Since, vGS1 = vGS2, then Io = Iref .

Note that as opposed to the BJT version, there is no 2/β effect here. However, a sufficient

voltage should be applied to Q2 to ensure that it is in the active state.



i C

i E3i C

i B i B

2iB

i B3

I refIo

Q1 Q2

Q3

−VEE

Because both bases and emitters of the transistors Q1 and Q2



and, therefore, similar iE = iE1 = iE2 and iC = iC1 = iC2.

Using iC = βiB and iE = (β + 1)iB to illustrate the impact

of β:

iB =iE

β + 1

KCL: iE3 = 2iB + ic =2iE

β + 1+

βiEβ + 1

=β + 2

β + 1iE

iB3 =iE3

β + 1=

β + 2

(β + 1)2iE

KCL: Iref = iC + iB3 =βiE

β + 1+

β + 2

(β + 1)2iE =

β(β + 1) + β + 2

(β + 1)2iE

Io = iC3 =β

β + 1iE3 =

β(β + 2)

(β + 1)2iE

Io

Iref

=β(β + 2)

β(β + 1) + β + 2=

β(β + 2)

β(β + 2) + 2==

1

1 +2

β(β + 2)

≈ 1

1 + 2/β2

This circuit is called the Wilson current mirror after its inventor. It has a reduced β depen-

dence compared to our simple current mirror and has a greater output impedance compared

to the current mirror of problem 2.


I refIo

Q1 Q2

Q3

−VSS

This is the MOS version of the Wilson current mirror. Solu-

tion is similar to those of Problems 3 and 4. The advantage of

this current mirror over the simple current mirror of Problem

3 is its much larger output resistance.


Problem 6. Find the bias point and AC amplifier parameters of this circuit


vo

vi

0.47 Fµ

18k

22k 1k

9 V

VCC

VBB

RB

RE

DC analysis:

Replace R1 and R2 with their Thevenin equivalent and

proceed with DC analysis (all DC current and voltages

are denoted by capital letters):

RB = 18 k ‖ 22 k = 9.9 kΩ

VBB =22

18 + 229 = 4.95 V

KVL: VBB = RBIB + VBE + 103IE IB =IE

1 + β=

IE

201

4.95 − 0.7 = IE

(

9.9 × 103

201+ 103

)

IE = 4 mA ≈ IC , IB =IC

β= 20 µA

KVL: VCC = VCE + 103IE

VCE = 9 − 103 × 4 × 10−3 = 5 V

DC Bias summary: IE ≈ IC = 4 mA, IB = 20 µA, VCE = 5 V

AC analysis: The circuit is a common collector amplifier. Using the formulas in page 189,

Av ≈ 1

Ri ≈ RB = 9.9 kΩ

Ro ≈rπ

β= 25 Ω

fl =ωl

2π=

1

2πRiCc

=1

2π × 9.9 × 103 × 0.47 × 10−6= 36 Hz


Problem 7. Find the bias point and AC amplifier parameters of this circuit


vi

vo

47 Fµ

µ4.7 F

270

240

15 V

34 k 1 k

5.9 k

VCC

VBB

RB

RC

R =E270 + 240 =510

DC analysis: Replace R1 and R2 with their Thevenin equivalent

and proceed with DC analysis (all DC current and voltages are

denoted by capital letters). Since all capacitors are replaced with

open circuit, the emitter resistance for DC analysis is 270+240 =

510 Ω.

RB = 5.9 k ‖ 34 k = 5.0 kΩ

VBB =5.9

5.9 + 3415 = 2.22 V

KVL: VBB = RBIB + VBE + 510IE IB =IE

1 + β=

IE

201

2.22 − 0.7 = IE

(

5.0 × 103

201+ 510

)

IE = 3 mA ≈ IC , IB =IC

β= 15 µA

KVL: VCC = 1000IC + VCE + 510IE

VCE = 15 − 1, 510 × 3 × 10−3 = 10.5 V

DC Bias: IE ≈ IC = 3 mA, IB = 15 µA, VCE = 10.5 V

AC analysis: The circuit is a common collector amplifier with an emitter resistance. Note

that the 240 Ω resistor is shorted out with the by-pass capacitor. It only enters the formula

for the lower cut-off frequency. Using the formulas in page 189 (with RE = 270 Ω) and

noting re = rπ/beta = 25 Ω:

Av =RC

RE

=1, 000

270= 3.70

Ri ≈ RB = 5.0 kΩ Ro ≈ ro

(

RE

re

+ 1)

= 1.2 M Ω

The lower cut-off frequency can be found from formula on page 183:

R′

E = RE2 ‖ (RE1 + re) = 240 ‖ (270 + 25) = 132 Ω

fl =ωl

2π=

1

2πRiCc

+1

2πR′

ECb

=

1

2π × 5, 000 × 4.7 × 10−6+

1

2π × 132 × 47 × 10−6= 31.5 Hz


Problem 8. Find the bias point and AC amplifier parameters of these circuits


vovi

16 V

1.5k

6.2k

510nF

30k

510

R 2

R 1

VCC Vγ−

+

−

+

VCC

VBB

RB

RC

RE

Because the forward bias voltage for BE junction, VBE = vγ, changes

as the temperature changes, the bias point changes slightly even in

the presence of the RE. Although this change is small, in some cases

a diode is added to the the voltage divider self-bias to compensate

for this small changes. Assuming that the BJT is in active state, the

base voltage has to be large enough to forward bias the BE junction

and, therefore, the diode would also be forward biased.

We can find the Thevenin equivalent of our bias circuit

(see circuit) by noting:

VBB = Voc =R2

R1 + R2

(VCC − vγ) + vγ = 2.74 + 0.83vγ (V)

RB = RT = R1 ‖ R2 = 5.14 kΩ

DC analysis:

BE-KVL: VBB = RBIB + VBE + 510IE

2.74 + 0.83vγ = 5.14 × 103IE

201+ vγ + 510IE

IE =2.74 − 0.17vγ

536= 4.9 mA ≈ IC , IB =

IC

β= 24 µA

Note that the dependence of IE to vγ is reduced by a factor of 6 ı.e.,

IE now scales as 2.74 − 0.17vγ instead of 2.74 − vγ (the case with no

diode).

CE-KVL: VCC = 1, 500IC + VCE + 103IE

VCE = 16 − 2, 100 × 4.9 × 10−3 = 5.7 V

AC analysis: Since the diode is forward biased and can be represented by an independent

voltage source, it does not enter the AC analysis (because we short out the DC voltage

sources). As such, this is a common emitter amplifier with an emitter resistor. Using the

formulas in page 189:

Av =RC

RE

=1, 500

510= 2.94


Ri ≈ RB = 5.1 kΩ Ro ≈ ro

(

RE

re

+ 1)

= 2.14 M Ω

fl =ωl

2π=

1

2πRiCc

= 60.7 Hz

Problem 9: Design a BJT amplifier with a gain of 4 and a lower cut-off frequency

of 100 Hz. The Q point parameters should be IC = 3 mA and VCE = 7.5 V.

R1 RC

R2

Cc

vi

RE

vo

VCC

VCC

VBB

RB

RC

RE

The prototype of this circuit is a common emitter amplifier with an

emitter resistance. Using formulas of page 189

|Av| ≈RC

RE

= 4

The lower cut-off frequency will set the value of Cc.

We start with the DC bias: As VCC is not given, we need to

choose it. To set the Q-point in the middle of load line, set

VCC = 2VCE = 15 V. Then, noting IC ≈ IE,:

VCC = RCIC + VCE + REIE

15 − 7.5 = 3 × 10−3(RC + RE) → RC + RE = 2.5 kΩ

Values of RC and RE can be found from the above equation

together with the AC gain of the amplifier, AV = RC/RE = 4:

RC

RE

= 4 → 4RE + RE = 2.5 kΩ → RE = 500 Ω, RC = 2. kΩ

Commercial values are RE = 510 Ω and RC = 2 kΩ. Use these commercial values for the

rest of analysis.

We need to check if VE > 1 V, the condition for good biasing. VE = REIE = 510×3×10−3 =

1.5 > 1, it is OK (See next example for the case when VE is smaller than 1 V).

We now proceed to find RB and VBB . RB is found from good bias condition (and trying to

have RB as large as possible) and VBB from a KVL in BE loop:

RB (β + 1)RE → RB = 0.1(βmin + 1)RE = 0.1 × 101 × 510 = 5.1 kΩ

BE-KVL: VBB = RBIB + VBE + REIE

VBB = 5.1 × 1033 × 10−3

201+ 0.7 + 510 × 3 × 10−3 = 2.28 V


Bias resistors R1 and R2 are now found from RB and VBB :

RB = R1 ‖ R2 =R1R2

R1 + R2

= 5 kΩ

VBB

VCC

=R2

R1 + R2

=2.28

15= 0.152

R1 can be found by dividing the two equations: R1 = 33 kΩ. R2 is found from the equation

for VBB to be R2 = 5.9 kΩ. Commercial values are R1 = 33 kΩ and R2 = 6.2 kΩ.

Lastly, we have to find the value of the coupling capacitor:

ωl =1

RiCc

= 2π × 100

Using Ri ≈ RB = 5.1 kΩ, we find Cc = 3 × 10−7 F or a commercial values of Cc = 300 nF.

So, are design values are: R1 = 33 kΩ, R2 = 6.2 kΩ, RE = 510 Ω, RC = 2 kΩ. and

Cc = 300 nF.

Problem 10: Design a BJT amplifier with a gain of 10 and a lower cut-off fre-

quency of 100 Hz. The Q point parameters should be IC = 3 mA and VCE = 7.5 V.

A power supply of 15 V is available.

R1 RC

R2

Cc

vi

RE

vo

VCCThe prototype of this circuit is a common emitter amplifier with an

emitter resistance. Using formulas of page 184:

|Av| ≈RC

RE

= 10

The lower cut-off frequency will set the value of Cc.

We start with the DC bias: As the power supply voltage is given,

we set VCC = 15 V. Then, noting IC ≈ IE,:

VCC = RCIC + VCE + REIE

15 − 7.5 = 3 × 10−3(RC + RE) → RC + RE = 2.5 kΩ

Values of RC and RE can be found from the above equation together with the AC gain of

the amplifier AV = RC/RE = 10:

RC

RE

= 10 → 10RE + RE = 2.5 kΩ → RE = 227 Ω, and RC = 2.27 kΩ


We need to check if VE > 1 V which is the condition for good biasing: VE = REIE =

227 × 3 × 10−3 = 0.69 < 1. Therefore, we need to use a bypass capacitor and modify our

circuits as is shown.

R1 RC

Cc

vi

vo

VCC

R2 RE1

CbRE2

VBB

RB

R + RE1 E2

RC

VCC

For DC analysis, the emitter resistance is RE1 + RE2 while for

AC analysis, the emitter resistance will be RE1. Therefore:

DC Bias: RC + RE1 + RE2 = 2.5 kΩ

AC gain: Av =RC

RE1

= 10

Above are two equations in three unknowns. A third equation is

derived by setting VE = 1 V to minimize the value of RE1 +RE2.

VE = (RE1 + RE2)IE

RE1 + RE2 =1

3 × 10−3= 333

Now, solving for RC , RE1, and RE2, we find RC = 2.2 kΩ,

RE1 = 220 Ω, and RE2 = 110 Ω (All commercial values).

We can now proceed to find RB and VBB :

RB (β + 1)(RE1 + RE2)

RB = 0.1(βmin + 1)(RE1 + RE2) = 0.1 × 101 × 330 = 3.3 kΩ

KVL: VBB = RBIB + VBE + REIE

VBB = 3.3 × 1033 × 10−3

201+ 0.7 + 330 × 3 × 10−3 = 1.7 V

Bias resistors R1 and R2 are now found from RB and VBB:

RB = R1 ‖ R2 =R1R2

R1 + R2

= 3.3 kΩ

VBB

VCC

=R2

R1 + R2

=1

15= 0.066

R1 can be found by dividing the two equations: R1 = 50 kΩ and R2 is found from the

equation for VBB to be R2 = 3.6k Ω. Commercial values are R1 = 51 kΩ and R2 = 3.6k Ω


Lastly, we have to find the value of the coupling and bypass capacitors:

R′

E = RE2 ‖ (RE1 + re) = 110 ‖ (220 + 25) = 76 Ω

Ri ≈ RB = 3.3 kΩ

ωl =1

RiCc

+1

R′

ECb

= 2π × 100

This is one equation in two unknown (Cc and CB) so one can be chosen freely. Typically

Cb Cc as Ri ≈ RB RE R′

E. This means that unless we choose Cc to be very small,

the cut-off frequency is set by the bypass capacitor. The usual approach is the choose Cb

based on the cut-off frequency of the amplifier and choose Cc such that cut-off frequency of

the RiCc filter is at least a factor of ten lower than that of the bypass capacitor. Note that

in this case, our formula for the cut-off frequency is quite accurate (see discussion in page

179) and is

ωl ≈1

R′

ECb

= 2π × 100

This gives Cb = 20 µF. Then, setting

1

RiCc

1

R′

ECb

1

RiCc

= 0.11

R′

ECb

RiCc = 10R′

ECb → Cc = 4.7 × 10−6 = 4.7 µF

So, are design values are: R1 = 50 kΩ, R2 = 3.6 kΩ, RE1 = 220 Ω, RE2 = 110 Ω, RC =

2.2 kΩ, Cb = 20 µF, and Cc = 4.7 µF.

An alternative approach is to choose Cb (or Cc) and compute the value of the other from

the formula for the cut-off frequency. For example, if we choose Cb = 47 µF, we find

Cc = 0.86 µF.

Problem 11. Design a BJT amplifier with a gain of 5 and a lower cut-off frequency

of 10 Hz, powered by a 16 V supply. Set the Q-point parameters to be VCE = 10 V

and Ic = 5 mA.

Answer: A common-emitter amplifier with R1 = 18 kΩ, R2 = 2.2 kΩ, RE = 200 Ω,

RC = 1.0 kΩ. and Cc = 10 µF.


Problem 12. Consider the BJT circuit below with R1 = 47 kΩ, R2 = 39 kΩ,

RE = 1.5 kΩ, RL = 50 kΩ, C1 = 100 nF, C2 = 0.47 µF, and VCC = 15 V. An input

signal with vi = cos(5000t) is applied to the circuit. Calculate the expressions for

voltages vB, vE, and vo. (Include both AC and DC parts in the expression for

each voltage.)

1C

R1

R2 ER LR

2C

VCC

i vBEv o

v

v

VCC

VBB

RB

RE

The voltages at Base and Emitter will be the sum of DC

and AC signals, e.g., vB = VB + ∆vB. First we calculate

the DC voltages, VB and VE. Replacing R1 and R2 with

their Thevenin equivalent, we have:

RB = R1 ‖ R2 =47 × 103 × 39 × 103

47 × 103 + 39 × 103= 21.3 kΩ

VBB =R2

R1 + R2

VCC = 6.80 V

KVL: VBB = RBIB + VBE + REIE

VBB − VBE = [RB + RE(β + 1)]IB

IB =6.80 − 0.7

21.3 × 103 + 1.5 × 103 × 201= 18.9 µA

IC ≈ IE = βIB = 3.78 mA

VE = REIE = 1, 500 × 3.78 × 10−3 = 5.67 V

VB = VE + VBE = 5.67 + 0.7 = 6.37 V

AC voltages: The circuit is a voltage follower. But, we have to check to see if capacitors

affect the signal. The frequency of the input signal is 5000/(2π) = 796 Hz. The impact of

C1 coupling capacitor is to set a lower cut-off frequency for the amplifier.

Ri ≈ RB = 21.3 kΩ

2π fl =1

RiCc

→ fl = 75 Hz 796 Hz

Thus: ∆vB = vi → vB = VB + ∆vB = 6.37 + cos(5000t)

Av ≈ 1 → ∆vE = ∆vB = vi → vE = VE + ∆vE = 5.67 + cos(5000t)

Capacitor C2 and resistor RL act as a high-pass filter. They separate the DC voltage. To

consider their impact on the AC signal, note:

2π fl =1

RLC2

→ fl = 6.8 Hz 796 Hz

Thus: ∆vo = ∆vE = ∆vB = vi → vo = 0 + ∆vo = cos(5000t)




vi

vo

47 Fµ

µ0.33 F

15 V

2 k39 k

5106.2 k 510

vi

vo

µ0.33 F

15 V

2 k39 k

5106.2 k

vi

vo

µ0.33 F

510 || 510= 255

15 V

2 k

6.2 k

39 k

DC Response AC signals

For DC signals, capacitors are open circuit and the emitter resistor is only 510 Ω. For AC

signals, capacitors are short circuit and the emitter resistor is 510 ‖ 510 = 255 Ω.

DC analysis:

RB = 6.2 ‖ 39 = 5.35 kΩ VBB =6.2 k

6.2 k + 39 k× 15 = 2.06 V

VBB = RBIB + VBE + IERE = 5.35 × 103IC

200+ 0.7 + 510IC

IC ≈ IE = 2.53 mA → IB =IC

β= 12.6 µA

VCC = RCIC + VCE + REIE → VCE = 15 − 2.53 × 10−3(2, 510) = 8.65 V

So Q point values are: IC ≈ IE = 2.53 mA, IB = 12.6 µA, and VCE = 8.65 V.

AC analysis: This is common emitter amplifier with emitter resistance:

Av ≈ RC

RE

=2, 000

255= 7.8

Ri ≈ RB = 4.8 k

Ro ≈ ro

(

RE

re

+ 1)

= 1.1 MΩ


Problems 14 & 15. Find the bias point and AC amplifier parameters of these

circuits (Manufacturers’ spec sheets give: β = 200, rπ = 5 kΩ, ro = 100 kΩ).

Both of these circuits are PNP versions of problem 6. For DC bias we should get the

same value for currents and voltages would be negative: IC = IE = 4 mA, IB = 20 µA,

VCE = −5 V, and VBE = −0.7 V. The amplifier parameters are exactly identical to those of

problem 6.



vo

vi

1k

4 V

−5 V

vo

1k

4 V

−5 V

This circuit is also similar to the circuit of problem 6.

Here BJT is biased with two voltage sources (Note that

in problem 6, VBB ≈ 5 V and here −VEE = −5 and

VCC = 9 − 5 = 4 V. As such, the Q-point parameters

should be the same.

DC Analysis: We short vi and,therefore, the BJT base would be grounded:

BE-KVL: 0 = VBE + 103IE − 5 → IC ≈ IE = 4.3 mA

IB =IC

β= 20 µA

CE-KVL: 4 = VCE + 103IE − 5

VCE = 9 − 103 × 4.3 × 10−3 = 4.7 V

DC Bias summary: IE ≈ IC = 4 mA, IB = 20 µA, and VCE = 5 V.

AC analysis: The circuit is a common collector amplifier. Using the formulas in page 189,

Av ≈ 1

Ri = rπ + (RE ‖ ro)(1 + β) ≈ rπ + ro(1 + β) = 20 MΩ

Ro ≈rπ

β= 25 Ω

fl =ωl

2π=

1

2πRiCc

=1

2π × 2 × 107 × 0.47 × 10−6= 0.034 Hz

Note that because there are no bias resistors (RB → ∞), we have used the full formulas for

Ri and the amplifier has a large input resistance.



(Manufacturers’ spec sheets give K = 0.25 mA/V2, Vt = 1 V, gm = 0.25 mA/V,

and ro = 100 kΩ).

vi

vo

Cc

1k

110k 2k

51k

12 V

vo

1k

2k

12 V

34.8k

3.8 V−

+

DC Bias: Replacing the bias circuit with its Thevenin equivalent, we get:

VGG =51, 000

51, 000 + 110, 000× 12 = 3.80 V

RG = 51 k ‖ 110 k = 34.8 kΩ

Since iG = 0,

GS-KVL: 3.8 = 34, 800iG + VGS + 1, 000iD = VGS + 1, 000iD

Assume NMOS is in active state,

iD = K(VGS − Vt)2 = 0.25 × 10−3(VGS − 1)2

Substituting for iD in GS-KVL, we get:

3.8 = VGS + 0.25(VGS − 1)2 = 0.25V 2

GS + 0.5VGS + 0.25

VGS = 2.9 V and VGS = −4.9 V

Negative root is unphysical, so VGS = 2.9 and iD = 0.9 mA. Then,

DS-KVL: 12 = 2, 000iD + VDS + 1, 000iD = VDS + 2.7 → VDS = 9.3 V

As VDS = 9.3 > VGS − Vt = 2.9 − 1 = 1.95, our assumption of NMOS in active state is

correct. Therefore, Bias Summary: VGS = 2.9 V, VDS = 9.3 V, and iD = 0.9 mA.

AC Analysis: This is a common source amplifier with a source resistor. Using formulas in

page 190:

Av ≈ − gmRD

1 + gmRS

= − 0.25 × 10−3 × 2 × 103

1 + 0.25 × 10−3 × 103= − 0.5

1.25= −0.4

Ri = RG = 34.8 kΩ

Ro = 1/gm ‖ ro =1

0.25 × 10−3‖ 100 × 103 ≈ 4 kΩ

ωl = 2π fl =1

RiCc



(Manufacturers’ spec sheets give K = 0.20 mA/V2 and Vt = 3 V, gm = 0.2 mA/V,

and ro = 100 kΩ).

vi

vo

Cc

Cb1M

1k1M

1k

20 V

vo

1k

500k

10 V

1k

20 V

−

+

DC Bias:

Replacing the bias circuit with its Thevenin equivalent,

we have RG = 500 kΩ and VGG = 10V:

GS-KVL: 10 = vGS + 103iD

DS-KVL: 20 = vDS + 103iD

Assume NMOS in active state: iD = K(vGS − Vt)2 and

vDS > vGS − Vt. Substituting for iD in GS-KVL, we get:

GS-KVL: 10 = vGS + 103 × 0.2 × 10−3(vGS − 3)2

10 = vGS + 0.2v2

GS − 1.2vGS + 1.8

v2

GS − vGS − 41 = 0

→ vGS = −5.92 V and vGS = 6.92 V

Negative root is unphysical so vGS = 6.92 V.

GS-KVL give iD = 3.08 mA. DS-KVL gives vDS = 20 − 6.16 = 13.8 V Since vDS = 13.8 >

vGS − Vt = 6.92 − 3 = 3.92 V, our assumption of NMOS in active state is justified. Bias

summary: vGS = 6.92 V, vDS = 13.8 V, and iD = 3.08 mA

AC Analysis: This is a common source amplifier with NO source resistor. Using formulas in

page 190:

Av ≈ −gmRD = −0.2 × 10−3 × 103 = −0.2

Ri = RG = 500 kΩ

Ro = ro = 100 kΩ

Note: Problems 17 & 18 show some fundamental differences between FET and BJT ampli-

fiers. BJTs have a much larger gain compared to FET (compare gm = 20 − 40 mA/V for a

typical BJT with gm = 0.2− 05mA/V for an NMOS). Therefore, typically RD and RS are a

factor of 10 or more larger than typical RC and RE values.

In addition, BJTs are more “linear” as iC = βiB and β does not vary considerably, while in

a MOSFET, iD = (vGS − Vt)2 so FET response is quadratic instead of linear. Because of

the more linear behavior and the higher gain, BJTs are used most often in amplifier circuits.

A first-stage FET source follower is also used to increase the input resistance of the overall

circuit considerably.



(Manufacturers’ spec sheets give K = 0.20 mA/V2 and Vt = 4 V, gm = 0.2 mA/V,

and ro = 100 kΩ).

vivo

Cc

500k

1.3M10k

18 V

vo

10k

18 V

13 V

361k

−

+

DC Bias:

Replacing the bias circuit with its Thevenin equivalent,

we have RG = 360 kΩ and VGG = 5V:

GS-KVL: 13 = vGS + 104iD

DS-KVL: 18 = vDS + 104iD

Assume NMOS in active state: iD = K(vGS − Vt)2 and

vDS > vGS − Vt. Substituting for iD in GS-KVL, we get:

GS-KVL: 5 = vGS + 50 × 103 × 0.2 × 10−3(vGS − 4)2

5 = vGS + 10v2

GS − 80vGS + 160

10v2

GS − 81vGS + 155 = 0

→ vGS = 3.1 V and vGS = 5 V

Since VGS = 3.1 < Vt = 4 V required for NMOS On, this root is unphysical so vGS = 5 V.

GS-KVL give iD = 0.2 mA. DS-KVL gives vDS = 18− 10 = 8 V Since vDS = 8 > vGS −Vt =

5−4 = 1 V, our assumption of NMOS in active state is justified. Bias summary: vGS = 5 V,

vDS = 8 V, and iD = 0.2 mA

AC Analysis: This is a common drain amplifier (or source follower). Using formulas in page

190:

Av =gmroRS

ro + (1 + gmro)RS

=0.2 × 10−3 × 100 × 103 × 50 × 103

100 × 103 + (1 + 0.2−3 × 100 × 103) × 50 × 103= 0.87

Ri = RG = 360 kΩ

Ro = 1/gm ‖ ro ≈ 5 kΩ


Problem 20: Find the bias point and AC amplifier parameters of this circuit


vivo

µ0.47 F

µ4.7 F

6.2k

Q1

33k

22k

18k

15 V

1k

Q2

2k

500

This is a two-stage amplifier. The first stage (Q1)

is a common emitter amplifier and the second

stage (Q2) is an emitter follower. The two stages

are coupled by a coupling capacitor (0.47 µF).

DC analysis:

When we replace the coupling capacitors with

open circuits, we see the that bias circuits for

the two transistors are independent of each other.

Each bias circuit can be solved separately.

For Q1, we replace the bias resistors (6.2k and 33k) with their Thevenin equivalent and

proceed with DC analysis:

RB1 = 6.2 k ‖ 33 k = 5.22 kΩ and VBB1 =6.2

6.2 + 3315 = 2.37 V

BE-KVL: VBB1 = RB1IB1 + VBE1 + 103IE1 IB1 =IE1

1 + β=

IE1

201

2.37 − 0.7 = IE1

(

5.22 × 103

201+ 500

)

IE1 = 3.17 mA ≈ IC1, IB1 =IC1

β= 16 µA

CE-KVL: VCC = 2 × 103IC1 + VCE1 + 500IE1

VCE1 = 15 − 2.5 × 103 × 3.17 × 10−3 = 7.1 V

DC Bias summary for Q1: IE1 ≈ IC1 = 3.17 mA, IB1 = 16 µA, VCE1 = 7.1 V

Following similar procedure for Q2, we get:

RB2 = 18 k ‖ 22 k = 9.9 kΩ and VBB2 =22

18 + 2215 = 8.25 V


1 + β=

IE2

201

8.25 − 0.7 = IE2

(

9.9 × 103

201+ 103

)

IE2 = 7.2 mA ≈ IC2, IB2 =IC2

β= 36 µA


CE-KVL: VCC = VCE2 + 103IE2

VCE2 = 15 − 103 × 7.2 × 10−3 = 7.8 V


AC analysis:

We start with the emitter follower circuit (Q2) as the input resistance of this circuit will

appear as the load for the common emitter amplifier (Q1). Using the formulas in page 189:

Av2 ≈ 1

Ri2 ≈ RB2 = 9.9 kΩ

fl2 =ωl2

2π=

1

2πRB2Cc2

=1

2π × 9.9 × 103 × 0.47 × 10−6= 34 Hz

Since Ri2 = 9.9 kΩ is NOT much larger than the collector resistor of common emitter

amplifier (Q1), it will affect the first circuit. Following discussion in pages 176 and 177, the

effect of this load can be taken into by replacing RC in common emitter amplifiers formulas

with R′

C = RC ‖ RL = RC1 ‖ Ri2 = 2 k ‖ 9.9 kΩ = 1.66 kΩ.

|Av1| ≈R′

C

RE

=1.66k

500= 3.3

Ri1 ≈ RB1 = 5.22 kΩ

fl1 =ωl1

2π=

1

2πRB1Cc1

=1

2π × 5.22 × 103 × 4.7 × 10−6= 6.5 Hz

The overall gain of the two-stage amplifier is then Av = Av1×Av2 = 3.3. The input resistance

of the two-stage amplifier is the input resistance of the first-stage (Q1), Ri = 9.9 kΩ. To

find the lower cut-off frequency of the two-stage amplifier, we note that:

Av1(jω) =Av1

1 − jωl1/ωand Av2(jω) =

Av2

1 − jωl2/ω

Av(jω) = Av1(jω) × Av2(jω) =Av1Av2

(1 − jωl1/ω)(1− jωl2/ω)

From above, it is clear that the maximum value of Av(jω) is Av1Av2 and the cut-off frequency,

ωl can be found from |Av(jω = ωl)| = Av1Av2/√

2 (similar to procedure we used for filters).

For the circuit above, since ωl2 ωl1 the lower cut-off frequency would be very close to ωl2.

So, the lower-cut-off frequency of this amplifier is 34 Hz.




vi

voµ4.7 F

IB2

I1

IC1

6.2k 500

15 V

1k

Q2

Q1

2k33k

VB2

This is a two-stage amplifier. The first stage (Q1) is

a common emitter amplifier and the second stage (Q2)

is an emitter follower. The circuit is similar to the two-

stage amplifier of Problem 20. The only difference is that

Q2 is directly biased from Q1 and there is no coupling

capacitor between the two stages. This approach has its

own advantages and disadvantages that are discussed at

the end of this problem.

DC analysis:

Since the base current in BJTs are typically much smaller that the collector current, we start

by assuming IC1 IB2. In this case, I1 = IC1 + IB2 ≈ IC1 ≈ IE1 (the bias current IB2 has

no effect on bias parameters of Q1). This assumption simplifies the analysis considerably

and we will check the validity of this assumption later.

For Q1, we replace the bias resistors (6.2k and 33k) with their Thevenin equivalent and

proceed with DC analysis:

RB1 = 6.2 k ‖ 33 k = 5.22 kΩ and VBB1 =6.2

6.2 + 3315 = 2.37 V


1 + β=

IE1

201

2.37 − 0.7 = IE1

(

5.22 × 103

201+ 500

)

IE1 = 3.17 mA ≈ IC1, IB1 =IC1

β= 16 µA

CE-KVL: VCC = 2 × 103IC1 + VCE1 + 500IE1

VCE1 = 15 − 2.5 × 103 × 3.17 × 10−3 = 7.1 V


To find the bias point of Q2, we note:

VB2 = VCE1 + 500 × IE1 = 7.1 + 500 × 3.17 × 10−3 = 8.68 V

BE-KVL: VB2 = VBE2 + 103IE2

8.68 − 0.7 = 103IE2


IE2 = 8.0 mA ≈ IC2, IB2 =IC2

β= 40 µA

KVL: VCC = VCE2 + 103IE2

VCE2 = 15 − 103 × 8.0 × 10−3 = 7.0 V


We now check our assumption of IC1 IB2. We find IC1 = 3.17 mA IB2 = 41 µA. So,

our assumption was justified.

It should be noted that this bias arrangement is also stable to variation in transistor β. The

bias resistors in the first stage will ensure that IC1 (≈ IE1) and VCE1 is stable to variation

of Q1 β. Since VB2 = VCE1 + RE1 × IE1, VB2 will also be stable to variation in transistor β.

Finally, VB2 = VBE2 + RE2IE2. Thus, IC2 (≈ IE2) will also be stable (and VCE2 because of

CE-KVL).

AC analysis:

As in problem 20, we start with the emitter follower circuit (Q2) as the input resistance

of this circuit will appear as the load for the common emitter amplifier (Q1). Using the

formulas in page 189 and noting that this amplifier does not have bias resistors (RB1 → ∞):

Av2 ≈ 1

Ri2 = rπ + (RE ‖ ro)(1 + β) = 5 × 103 + 201 × 103 = 201 kΩ

Note that because of the absence of the bias resistors, the input resistance of the circuit is

very large, and because of the absence of the coupling capacitors, there is no lower cut-off

frequency for this stage.

Since Ri2 = 201 kΩ is much larger than the collector resistor of common emitter amplifier

(Q1), it will NOT affect the first circuit. The parameters of the first-stage common emitter

amplifier can be found using formulas of page 189.

|Av1| ≈RC

RE

=2, 000

500= 4

Ri1 ≈ RB1 = 5.22 kΩ

fl1 =ωl1

2π=

1

2πRB1Cc1

=1

2π × 5.22 × 103 × 4.7 × 10−6= 6.5 Hz

The overall gain of the two-stage amplifier is then Av = Av1 ×Av2 = 4. The input resistance

of the two-stage amplifier is the input resistance of the first-stage (Q1), Ri = 9.9 kΩ. The

lower cut-off frequency of the two-stage amplifier is 6.5 Hz.


This two-stage amplifier has many advantages over that of problem 20. It has three less

elements. Because of the absence of bias resistors, the second-stage does not load the first

stage and the overall gain is higher. Also because of the absence of a coupling capacitor

between the two-stages, the overall cut-off frequency of the circuit is lower. Some of these

issues can be resolved by design, e.g., use a large capacitor for coupling the two stages, use

a large RE2, etc.. The drawback of this circuit is that the bias circuit is more complicated

and harder to design.



vi

vo

µ4.7 F

IB2

IC1

I1

VB2

5102.7k

3.6k15k

18 V

510

1.5k

Q1Q2

We start with replacing 2.7 k and 15 kΩ voltage di-

vider with its Thevenin equivalent (as seen in circuit

below)

RB = 2.7 ‖ 15 = 2.29 kΩ

VBB =2.7 k

2.7 k + 15 k× 18 = 2.75 V

Writing a KVL through BE terminals of Q1 and assuming that

Q1 is in the active-linear state (IC1 ≈ IE1 = βIB1), we get:

VBB = RBIB1 + VBE1 + 510IE1 = 2.29 × 103IC1

100+ 0.7 + 510IC1

IC1 ≈ IE1 = 3.85 mA → IB1 = IC1/β = 38.5 µA

CE1-KVL: 18 = 3.6 × 103I1 + VCE1 + 510IE1

KCL: I1 = IC1 + IB2

We assume IB2 IC1. Then, from KCL above, I1 ≈ IC1 = 3.85 mA. Substituting for I1

and IE1 in CE1-KVL, we find VCE1 = 2.18 V. Since VCE1 > Vγ = 0.7 V, our assumption of

Q1 being in the active-linear state is justified.

To find the Q-point of Q2, we first calculate the voltage at the collector of Q1 through a

KVL its CE terminals:

VC1 = VB2 = VCE1 + 510IE1 = 2.18 + 1.96 = 4.14 V


We assume that Q2 is in the active-linear state. We can calculate IC2 ≈ IE2 from a KVL:

VC1 = VB2 = VBE2 + 510IE2 → 4.14 = 0.7 + 510IE2

IE2 ≈ IC2 = 6.75 mA → IB2 =IC2

β= 67.5 µA

Since IB2 = 67.5 µA IC1 = 3.85 mA, our assumption of IB2 IC1 is justified. Lastly, we

can find VCE2 from a KVL through CE terminals of Q2:

18 = 1.5 × 103IC2 + VCE2 + 510IE2 → VCE2 = 4.43 V

Ans since VCE2 = 4.43 V > Vγ = 0.7 V, our assumption of Q2 being in the active-linear

state is justified.

Therefore, the operating points of BJTs are: IE1 ≈ IC1 = 3.85 mA, IB1 = 38.5 µA, VCE2 =

2.18 V and IE2 ≈ IC2 = 6.75 mA, IB2 = 67.5 µA, VCE2 = 4.43 V

AC analysis:

As in problems 20 & 21, we start with the Q2 circuit as the input resistance of this circuit

will appear as the load for the Q1 circuit. Q2 is configured as a common emitter amplifer

with an emitter resistor. Using the formulas in page 189 and setting RB1 → ∞:

Av2 ≈ − RC

RE

= − 1, 500

510≈ −3

Ri2 = rπ + (RE ‖ ro)(1 + β) = 5 × 103 + 201 × 510 = 108 kΩ

Note that because of the absence of the bias resistors, the input resistance of the circuit is

very large, and because of the absence of any coupling capacitors, there is no lower cut-off

frequency for this stage.

Since Ri2 = 108 kΩ is much larger than the collector resistor of common emitter amplifier

(Q1), it will NOT affect the first circuit. The parameters of the first-stage common emitter

amplifier can be found using formulas of page 189.

Av1 ≈ − RC

RE

= − 3, 600

510= −7.06

Ri1 ≈ RB1 = 2.29 kΩ

fl1 =ωl1

2π=

1

2πRB1Cc1

=1

2π × 2.29 × 103 × 4.7 × 10−6= 14.8 Hz

The overall gain of the two-stage amplifier is then Av = Av1×Av2 = 21. The input resistance

of the two-stage amplifier is the input resistance of the first-stage (Q1), Ri = 2.3 kΩ. The

lower cut-off frequency of the two-stage amplifier is 14.8 Hz.


Documents

VI. Transistor ampli ers: Biasing and Small Signal Modelaries.ucsd.edu/NAJMABADI/CLASS/ECE65/06-S/NOTES/transistor-2.pdfVI. Transistor ampli ers: Biasing and Small Signal Model 6.1