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    HDL For EmbeddedHDL For EmbeddedHDL For EmbeddedHDL For Embedded

    SystemSystemSystemSystem

    1

    Mukesh Maheshwari

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    VHDLVHDLVHDLVHDL

    INTRODUCTION

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    2

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    IntroductionIntroductionIntroductionIntroduction

    WHAT IS VHDL ?

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    FEATURES OF VHDL

    HISTORY OF VHDL

    LEVELS OF ABSTRACTION

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    What is VHDL?What is VHDL?What is VHDL?What is VHDL?

    DIGITAL SYSTEM DESIGN USINGHDLS IS AN ESTABLISHED

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    .

    VHDL stands for

    Very High Speed Integrated Circuits

    Hardware Description Language.

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    Features of VHDLFeatures of VHDLFeatures of VHDLFeatures of VHDL

    VHDL is the amalgamation of following languages:

    Concurrent Language

    Sequential Language

    Timing Specification Simulation Language

    Test Language

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    Powerful Language Constructs Ex: if---else, with---select, etc.

    Design Hierarchies to create Modular designs

    Supports Design LibrariesFacilitates device independent design and

    Portability

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    Concurrent LanguageConcurrent LanguageConcurrent LanguageConcurrent Language

    Concurrent Statements execute atatatatthe same time in parallelthe same time in parallelthe same time in parallelthe same time in parallel, as in

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    .

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    Sequential LanguageSequential LanguageSequential LanguageSequential Language

    Sequential Statements execute one atone atone atone at

    a timea timea timea time in sequence.As the case with any conventional

    lan ua e

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    Sequence of statements is important.

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    Timing SpecificationTiming SpecificationTiming SpecificationTiming Specification

    Example:

    process

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    8

    clk

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    Test LanguageTest LanguageTest LanguageTest Language

    Test bench Is part of a VHDL model that generates a set of test

    vectors and sends them to the Module being tested.

    Collects the responses made by the Module Under Test

    and compares them against a specification of correct

    results.

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    Need

    To ensure that design is correct.

    Model is operating as required.

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    Design HierarchyDesign HierarchyDesign HierarchyDesign Hierarchy

    Hierarchy can be represented using VHDL.

    Consider example of a Full-adder which is the top-

    level module, being composed of three lower level

    modules I.e. Half-Adder and OR gate.

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    Design Unit

    Is any block of VHDL code or collection of VHDLcodes that may be independently analysed and

    inserted into a design library.

    Design librariesDesign librariesDesign librariesDesign libraries 11

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    Is a storage facility in which analysed VHDL

    descriptions are stored.

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    History of VHDLHistory of VHDLHistory of VHDLHistory of VHDL

    In 1981 the Institute for Defense Analysis (IDA) had arranged

    a workshop to study

    Various Hardware Description methods Need for a standard language

    Features required by such a standard.

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    A team of three companies, IBM, Texas Instruments, andIntermetrics were awarded contract by DoD to develop a

    language.

    Version 7.2 of VHDL was released along with LanguageReference Manual (LRM) in 1985.

    Standardized by IEEE in 1987 known as the IEEE Std 1076-

    1987.

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    Logic SystemsLogic SystemsLogic SystemsLogic Systems

    Need for a multi-valued Logic System

    Conventional Logic systems had only three valuesI.e. 0 , 1 and Z

    Consider truth table for AND gate

    A B Y

    0 0 0

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    1 0 0

    1 1 1

    For

    0 Z ???

    A 9-value package STD_LOGIC_1164 was developedand accepted as IEEE Std 1164-1993.

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    Logic SystemsLogic SystemsLogic SystemsLogic Systems

    Need for a standard Logic System

    Different vendors used different logic systems.

    Sharing of codes developed on different toolsets wasdifficult.

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    Multivalued logic

    Unknown : Value was known, but is not anymore.

    Un-initialized : Value was never known in the firstplace !

    High impedance : Net has no driver.

    Drive strengths : Handle different output drivers.

    Dont care : Optimizes synthesis implementation.

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    MultiMultiMultiMulti----Valued LogicValued LogicValued LogicValued Logic

    A 9-value package STD_LOGIC_1164

    was developed and accepted as IEEE

    Std 1164-1993.U : Uninitialized

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    : n nown

    0 : Logic 0

    1 : Logic 1

    Z : High impedance

    W : weak unknown

    L : weak logic 0

    H : weak logic 1

    - : Dont care

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    ELEMENTS OF VHDLELEMENTS OF VHDLELEMENTS OF VHDLELEMENTS OF VHDL AgendaAgendaAgendaAgenda

    BASIC BUILDING BLOCKS

    ENTITY

    ARCHITECTURE

    LANGUAGE ELEMENTS

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    SEQUENTIAL STATEMENTS

    SIGNALS & VARIABLES

    CONFIGURATION

    PACKAGE

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    Basic Building BlocksBasic Building BlocksBasic Building BlocksBasic Building Blocks

    Entity

    A designs interface to the external circuitry.

    Architecture

    Describes a designs behavior and functionality.

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    Configuration

    Binds an entity to an architecture when there are multiple

    architectures for a single entity.

    Package Contains frequently used declarations, constants,

    functions, procedures, user data types and components.

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    Basic Building BlocksBasic Building BlocksBasic Building BlocksBasic Building Blocks

    Library

    Is a collection of compiled VHDL units

    Promotes sharing of compiled designs and hides thesource code from the users

    Commonly used functions, procedure and user data types

    can be compiled into a user-defined library for use in all

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    designs Library should be declared before EACH entity declaration

    even if it is in the same VHDL file.

    Syntax library IEEE;

    use IEEE.std_logic_1164.all

    use IEEE.std_logic_unsigned.all

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    EntityEntityEntityEntity

    Equivalent to pin configuration of an IC.

    Syntax: entity entity_name is

    port (port_list);

    end entity_name;

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    Example :entity and_gate is

    port ( 1A, 2A, 3A, 4A : in std_logic;

    1B, 2B, 3B, 4B : in std_logic;

    1Y, 2Y, 3Y, 4Y : out std_logic) ;

    end and_gate ;

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    EntityEntityEntityEntity

    VHDL design description must include,

    ONLY ONE ENTITY

    Entity Declaration

    Defines the input and output ports of the design.

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    ac por n e por s mus e g ven,

    a name

    data flow direction

    a type.

    Can be used as a component in other entities after being

    compiled into a library.

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    EntityEntityEntityEntity

    Proper documentation of the ports in an entity

    is very important.

    A specified port should have a self explanatory

    name that provides information about its

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    .

    Ports should be well documented with

    comments at the end of the line providing

    additional information about the signal.

    Consider example of an ALU.

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    ModesModesModesModes

    Signal in the port has a Mode which

    indicates the driver direction.

    Mode also indicates whether or not theport can be read from within the

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    Four types of Modes are used in

    VHDL.

    Mode IN Mode OUT

    Mode INOUT

    Mode BUFFER

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    ModeModeModeMode ININININ

    Value can be read but notassigned.

    Example:

    Port SignalPort SignalPort SignalPort SignalEntityEntityEntityEntity

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    entity driver is

    port ( A : in std_logic;

    B : out std_logic;

    Data : inout std_logic;

    Count : buffer std_logic) ;

    end driver ;

    Drivers resideDrivers resideDrivers resideDrivers resideoutside the entityoutside the entityoutside the entityoutside the entity

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    ModeModeModeModeOUTOUTOUTOUT

    Value can be assigned but not

    read.

    Example:

    Entit

    y

    Port Signal

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    port ( A : in std_logic;B : out std_logic;

    Data : inout std_logic;

    Count : buffer std_logic )

    ;

    end driver ;

    Drivers resideinside the entity

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    ModeModeMod