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1/26
/200
21
Ve
rilo
g H
DL
In
trod
uc
tion
EC
E 5
54
Dig
ita
l
En
gin
ee
rin
g L
ab
ora
tory
Charle
s R
. K
ime
1/28
/200
12
Overvie
w
�Sim
ula
tion a
nd S
ynth
esi
s
�M
odule
s and P
rim
itiv
es
�Sty
les
�Str
uct
ura
l D
esc
riptions
�La
nguage C
onve
ntions
�D
ata
Typ
es
�D
ela
y
�Behavi
ora
l Const
ruct
s
�Com
pile
r D
irect
ives
�Sim
ula
tion a
nd T
est
bench
es
1/28
/200
13
Sim
ula
tion
an
d S
ynth
esis
�Sim
ula
tion t
ools
typic
ally
acc
ept
full
set
of
Verilo
g
language c
onst
ruct
s
�Som
e language c
onst
ruct
s and t
heir u
se in a
Verilo
g d
esc
ription m
ake s
imula
tion e
ffic
ient
and
are
ignore
d b
y s
ynth
esi
s to
ols
�Synth
esi
s to
ols
typic
ally
acc
ept
only
a s
ubse
t of
the f
ull
Verilo
g language c
onst
ruct
s•
In t
his
pre
senta
tion, Verilo
g language c
onst
ruct
s not
support
ed in S
ynopsy
s FPG
A E
xpre
ss a
re in r
ed ita
lics
•There
are
oth
er
rest
rict
ions
not
det
aile
d h
ere
, se
e [2].
1/28
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14
Mod
ule
s
�The M
odule
Conce
pt
•Basi
c desi
gn u
nit
•M
odule
s are
:�
Declare
d
�In
stantiated
•M
odule
s decl
ara
tions
cannot
be n
est
ed
1/28
/200
15
Mod
ule
Dec
lara
tion
(F
IO*)
�Synta
x
module
_decl
ara
tion
::=
module
_ke
yword
module
_id
entifier
[lis
t of
port
s];
{module
_item
} endmodule
module
_ke
yword
::=
module
|macro
module
list_
of_
port
s
::=
(port
{, port
})
* F
or
Info
rmat
ion O
nly
–not
to b
e c
ove
red in p
rese
nta
tion
1/28
/200
16
Mod
ule
Dec
lara
tion
(F
IO)
�Synta
x (
continued)
module
_item
::=
module
_item
_decl
ara
tion |
para
mete
r_overr
ide
| co
ntinuous_
ass
ign
| gate
_in
stantiation |
udp_in
stantiation |
module
_in
stantiation |
sp
eci
fy_blo
ck|
initia
l_co
nst
ruct
| alw
ays_
const
ruct
module
_item
_decl
ara
tion
::=
para
mete
r_decl
ara
tion |
input_
decl
ara
tion |
outp
ut_
decl
ara
tion |
in
out_
decl
ara
tion |
net_
decl
ara
tion |
reg_decl
ara
tion |
in
teger_
decl
ara
tion |
real_
decl
ara
tion
| tim
e_decl
ara
tion
| re
altim
e_decl
ara
tion
| event_
decl
ara
tion
| ta
sk_decl
ara
tion |
fu
nct
ion_decl
ara
tion
para
mete
r_overr
ide
::=
defparam
list_
of_
para
mete
r_ass
ignm
ents
udp d
ecl
ara
tion
1/28
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17
Mod
ule
Dec
lara
tion
�Annota
ted E
xam
ple
/* m
odul
e_ke
ywor
d m
odul
e_id
entif
ier
(list
of p
orts
) */
mo
du
leC
_2_4
_dec
oder
_with
_ena
ble
(A,
E_n
, D
) ;
inp
ut
[1:0
] A ;
// in
put_
decl
arat
ion
inp
ut
E_n
; //
inpu
t_de
clar
atio
no
utp
ut
[3:0
] D ;
// ou
tput
_dec
lara
tion
assi
gn
D =
{4{
~E
_n}}
& (
(A =
= 2
'b00
) ?
4'b0
001
:(A
==
2'b
01)
? 4'
b001
0 :
(A =
= 2
'b10
) ?
4'b0
100
:(A
==
2'b
11)
? 4'
b100
0 :
4'bx
xxx)
; //
cont
inuo
us_a
ssig
nen
dm
od
ule
1/28
/200
18
Mod
ule
Dec
lara
tion
�Id
entifiers
-m
ust
not
be k
eyw
ord
s!
�Port
s •First
exa
mple
of
signals
•Sca
lar:
e. g., E
_n
•Vect
or:
e. g., A
[1:0
], A
[0:1
], D
[3:0
], a
nd D
[0:3
]
�Range is
MSB t
o L
SB
�Can r
efe
r to
part
ial ra
nges
-D
[2:1
]
•Typ
e:
defined b
y ke
yword
s�
inp
ut
�o
utp
ut
�in
ou
t (bi-directional)
1/28
/200
19
Mod
ule
Insta
nti
ati
on
mo
du
le C
_4_16_deco
der_
with_enable
(A, E
_n, D
) ;
inp
ut
[3:0
] A ;
inp
ut
E_n ;
o
utp
ut
[15:0
] D
;
wir
e [
3:0
] S;
wir
e[3
:0]
S_n;
C_2_4_deco
der_
with_enable
DE (
A[3
:2],
E_n, S
);not
N0 (
S_n, S);
C_2_4_deco
der_
with_enable
D0 (
A[1
:0],
S_n[0
], D
[3:0
]);
C_2_4_deco
der_
with_enable
D1 (
A[1
:0],
S_n[1
], D
[7:4
]);
C_2_4_deco
der_
with_enable
D2 (
A[1
:0],
S_n[2
], D
[11:8
]);
C_2_4_deco
der_
with_enable
D3 (
A[1
:0],
S_n[3
], D
[15:1
2])
;
en
dm
od
ule
�Exam
ple
1/28
/200
110
Mod
ule
Insta
nti
ati
on
(F
IO)
module
_in
stantiation :
:=
module
_id
entifier
[para
mete
r_valu
e_ass
ignm
ent]
module
_in
stance
{,
module
_in
stance
};
para
mete
r_valu
e_ass
ignm
ent
::=
#
(expre
ssio
n {
, exp
ress
ion})
module
_in
stance
::=
nam
e_of_
inst
ance
([lis
t_of_
module
_co
nnect
ions]
)
nam
e_of_
inst
ance
::=
module
_in
stance
_id
entifier
[range]
list
of m
odule
connect
ions
::=
ord
ere
d_port
_co
nnect
ion {
, ord
ere
d_port
_co
nnect
ion}
| nam
ed_port
_co
nnect
ion {
, nam
ed_port
_co
nnect
ion}
ord
ere
d_port
_co
nnect
ion :
:= [
expre
ssio
n]
nam
ed_port
_co
nnect
ion :
:= . p
ort
_id
entifier
([expre
ssio
n])
�Synta
x
1/28
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111
Mod
ule
Insta
nti
ati
on
•Sin
gle
module
inst
antiation f
or
five
module
inst
ance
s
C_2_4_deco
der_
with_enable
DE (
A[3
:2],
E_n, S
),D
0 (
A[1
:0],
S_n[0
], D
[3:0
]),
D1 (
A[1
:0],
S_n[1
], D
[7:4
]),
D2 (
A[1
:0],
S_n[2
], D
[11:8
]),
D3 (
A[1
:0],
S_n[3
], D
[15:1
2])
;
•N
am
ed_port
connect
ion
C_2_4_deco
der_
with_enable
DE (
.E_n (
E_n),
.A (
A[3
:2])
.D
(S))
;//
Note
ord
er
in lis
t no longer
import
ant
(E_n a
nd A
inte
rchanged).
�M
ore
Exam
ple
s
1/28
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112
Pri
mit
ives
�G
ate
Level
•and, nand
•or,
nor
•xo
r, x
nor
•buf
, not
•bufif0
, bufif1
, notif0
, notif1
(th
ree-s
tate
)
�Sw
itch L
evel
•*m
os
where
* is
n,p, c,
rn, rp
, rc
; pullu
p, pulld
ow
n;
*tr
an+
where
* is
(null)
, r
and +
(null)
, if0, if1 w
ith
both
* a
nd +
not
(null)
1/28
/200
113
Pri
mit
ives
�N
o d
ecl
ara
tion;
can o
nly
be inst
antiate
d�
All
outp
ut
port
s appear
in lis
t befo
re a
ny
input
port
s �
Optional drive
str
ength
, dela
y, n
am
e o
f in
stance
�Exa
mple
: a
nd
N25
(Z, A, B, C);
//inst
ance
nam
e�
Exa
mple
: a
nd
#10
(Z, A, B, X);
//
dela
y(X
, C, D
, E);
//d
ela
y/*
Usu
ally
bett
er
to p
rovi
de inst
ance
nam
e f
or
debuggin
g.*
/
�Exa
mple
: o
rN
30
(SET, Q
1, AB, N
5),
�
N41
(N25, ABC, R1);
1/28
/200
114
Sty
les
�Str
uct
ura
l -
inst
antiation o
f prim
itiv
es
and
module
s
�RTL/D
ata
flow
-co
ntinuous
ass
ignm
ents
�Behavio
ral -
pro
cedura
l ass
ignm
ents
1/28
/200
115
Sty
le E
xam
ple
-S
tru
ctu
ral
module
half_add (
X, Y, S, C);
inp
ut
X, Y ;
ou
tpu
tS, C ;
xo
r(S
, X, Y)
;a
nd
(C, X, Y)
;
en
dm
od
ule
mo
du
lefu
ll_add (
A, B, CI,
S, CO
) ;
inp
ut
A, B, CI
;o
utp
ut
S,CO
;
wir
eN
1, N
2, N
3;
half_add H
A1 (
A, B, N
1, N
2),
HA2 (
N1, CI,
S, N
3);
or
P1 (
CO
, N
3, N
2);
en
dm
od
ule
1/28
/200
116
Sty
le E
xam
ple
-R
TL
/Da
tafl
ow
mo
du
lefa
_rt
l(A
, B, CI,
S, CO
) ;
inp
ut
A, B, CI
;o
utp
ut
S,CO
;
assig
nS =
A ^
B ^
CI;
//
continuous
ass
ignm
ent
assig
n C
O =
A &
B |
A &
CI
| B &
CI;
//c
ontinuous
ass
ignm
ent
en
dm
od
ule
1/28
/200
117
Sty
le E
xam
ple
-B
eh
avio
ral
mo
du
lefa
_b
hv
(A, B, CI,
S, CO
) ;
inp
ut
A, B, CI
;o
utp
ut
S,CO
;
reg
S, CO
;//
required t
o “
hold
” va
lues
betw
een e
vents
.
alw
ays@
(A o
rB o
rCI)
//;
b
eg
inS <
= A
^ B
^ C
I;//
pro
cedura
l ass
ignm
ent
CO
<=
A &
B |
A &
CI
| B &
CI;
// p
roce
dura
l ass
ignm
ent
en
d
en
dm
od
ule
1/
28/2
001
18
Str
uc
tura
l D
esc
rip
tio
ns
�Textu
al desc
ription o
f sc
hem
atic
�Form
of
netlis
t
�Connect
ions
�H
iera
rchy
�Arr
ays
of
inst
ance
s
�H
iera
rchy e
stablis
hed b
y inst
antiation o
f m
odule
s and p
rim
itiv
es
within
module
s
1/28
/200
119
Co
nn
ec
tion
s
�By p
osi
tion a
ssoci
ation
•m
od
ule
C_2
_4_d
ecod
er_w
ith_e
nabl
e (A
, E_n
, D);
•C_4_16_deco
der_
with_enable
DX (
X[3
:2],
W
_n, w
ord
);
•A =
X[3
:2],
E_n =
W_n, D
= w
ord
�By n
am
e a
ssoci
ation
•m
od
ule
C_2
_4_d
ecod
er_w
ith_e
nabl
e (A
, E_n
, D);
•C_2_4_deco
der_
with_enable
DX (
.E_n(W
_n),
.A(X
[3:2
]),
.D(w
ord
));
•A =
X[3
:2],
E_n =
W_n, D
= w
ord
1/28
/200
120
Co
nn
ec
tion
s
�Em
pty
Port
Connect
ions
•m
od
ule
C_2
_4_d
ecod
er_w
ith_e
nabl
e (A
, E_n
, D);
•C_2_4_deco
der_
with_enable
DX (
X[3
:2],
, w
ord
);
•E_n is
at
hig
h-im
pedance
sta
te (
z)
•C_2_4_deco
der_
with_enable
DX (
X[3
:2],
W_n ,);
•O
utp
uts
D[3
:0]
unuse
d.
1/28
/200
121
Arr
ays o
f In
sta
nces
�{
, }
is c
onca
tenate
�Exam
ple
mo
du
leadd_arr
ay (
A, B, CIN
, S, CO
UT)
;
inp
ut
[7:0
] A, B ;
inp
ut
CIN
;o
utp
ut
[7:0
] S ;
ou
tpu
t CO
UT ;
wir
e[7
:1]
carr
y;
full_
add F
A[7
:0]
(A,B
,{ca
rry, CIN
},S,{
CO
UT, ca
rry});
// f
ull_
add is
a m
odule
en
dm
od
ule
1/
28/2
001
22
La
ng
ua
ge
Co
nve
nti
on
s
�Case
-sensi
tivi
ty•
Verilo
g is
ca
se
-se
nsit
ive.
•Som
e s
imula
tors
are
case
-inse
nsi
tive
•Advic
e:
-D
on’t u
se c
ase
-sensi
tive featu
re!
•Keyw
ord
s are
lo
wer c
ase
�D
iffe
rent
nam
es
must
be u
sed f
or
diffe
rent
item
s w
ithin
th
e s
am
e s
cope
�Id
entifier
alp
habet:
•U
pper
and low
er
case
alp
habetica
ls
•deci
mal dig
its
•unders
core
1/28
/200
123
La
ng
ua
ge
Co
nve
nti
on
s
�M
axi
mum
of
1024 c
hara
cters
in identifier
�First
char
act
er
not
a d
igit
�Sta
tem
ent
term
inate
d b
y ;
�Fre
e f
orm
at
within
sta
tem
ent
exc
ept
for
within
quote
s
�Com
men
ts:
•All
chara
cters
aft
er
// in a
lin
e a
re t
reate
d a
s a c
om
ment
•M
ulti-lin
e c
om
ments
begin
with /
* a
nd e
nd w
ith *
/
�Com
pile
r direct
ives
begin
with /
/ sy
nopsy
s
�Built
-in s
yste
m t
ask
s or
funct
ions
begin
with $
�Str
ings
encl
ose
d in d
ouble
quote
s an
d m
ust
be o
n a
sin
gle
lin
e
1/28
/200
124
Log
ic V
alu
es
�Verilo
g s
ignal valu
es
•0 -
Logic
al 0 o
r FALS
E
•1 -
Logic
al 1 o
r TR
UE
•x,
X -
Unkn
ow
n logic
valu
e
•z,
Z -
Hig
h im
pedance
conditio
n
�Als
o m
ay h
ave a
ssoci
ate
d s
trength
for
switch
le
vel m
odelin
g o
f M
OS d
evic
es
•7 s
ignal st
rength
s plu
s 3 c
harg
e s
trength
s
1/28
/200
125
Nu
mb
er
Re
pre
se
nta
tio
n
�Form
at:
<si
ze>
<base
_fo
rmat>
<num
ber>
•<
size
> -
deci
mal sp
eci
fica
tion o
f num
ber
of
bits
�default
is u
nsi
zed a
nd m
ach
ine-d
ependent
but
at
least
32 b
its
•<
base
form
at>
-
' fo
llow
ed b
y arith
metic
base
of
num
ber
�<
d>
<D
> -
deci
mal -default
base
if no <
base
_fo
rmat>
giv
en
�<
h>
<H
> -
hexa
deci
mal
�<
o>
<O
> -
oct
al
�<
b>
<B>
-bin
ary
•<
num
ber
> -
valu
e g
iven in b
ase
of
<base
_fo
rmat
>�
_ c
an b
e u
sed for
readin
g c
larity
�If
first
chara
cter
of si
zed, bin
ary
num
ber
is
0, 1, th
e v
alu
e is 0-
filled
up t
o s
ize. If
x o
r z,
valu
e is
ex
te
nd
ed
usi
ng x
or
z,
resp
ect
ively
.
1/28
/200
126
Nu
mb
er
Re
pre
se
nta
tio
n
�Exa
mple
s:•
6’b
010_111
giv
es
010111
•8'b
0110
giv
es
00000110
•8’b
1110
giv
es
00001110
•4'b
x01
giv
es
xx01
•16'H
3AB
giv
es
0000001110101011
•24
giv
es
0…
0011000
•5'O
36
giv
es
11100
•16'H
xgiv
es
xxxx
xxxx
xxxx
xxxx
•8'h
zgiv
es
zzzz
zzzz
1/28
/200
127
Va
ria
ble
s
�N
ets
•U
sed f
or
stru
ctura
l co
nnect
ivity
�Regis
ters
•Abst
ract
ion o
f st
ora
ge (
May
or
may
not
be r
eal
phys
ical st
ora
ge)
�Pro
pert
ies
of
Both
•In
form
ally
calle
d s
ignals
•M
ay
be e
ither
scala
r or
vect
or
1/28
/200
128
Da
ta T
yp
es -
Ne
ts -
Sem
an
tics
�w
ire -
connect
ivity o
nly
; no logic
al
�tr
i -
sam
e a
s w
ire, but
will
be 3
-sta
ted in
hard
ware
�w
and -
multip
le d
rive
rs -
wired a
nd
�w
or
-m
ultip
le d
rive
rs -
wired o
r�
tria
nd -
sam
e a
s w
and, but
3-s
tate
�tr
ior
-sa
me a
s w
or
but
3-s
tate
�su
pply
0 -
Glo
bal net
GN
D
�su
pply
1 -
Glo
bal N
et
VCC (
VD
D)
�tr
i0, tr
i 1, tr
ireg
1/28
/200
129
Da
ta T
yp
es -
Ne
ts -
Syn
tax
�N
et
decl
ara
tion :
:=
net
type [vectore
d| scalare
d]
[range]
[dela
y3]
list_
of_
net_
identifiers
; | trireg
[vectore
d| scalare
d]
[charg
e s
trenth
] [r
ange]
[dela
y3]
list_
of_
net_
identifiers
;
| net
type [vecto
red
| scalare
d]
[drive s
trength
] [r
ange]
[dela
y 3
] lis
t_of_
net_
decl
_ass
ignm
ents
;
�Vectored
-m
ultip
le-b
it n
et
treat
ed a
s a s
ingle
obje
ct -
cannot
refe
rence
indiv
idual bits
or
part
-sele
ct
�Scalared
-bits
can b
e r
efe
rence
d indiv
idually
or
be p
art
se
lect
ed
�Valu
e im
plic
itly
ass
igned b
y co
nnect
ion t
o p
rim
itiv
e
or
module
outp
ut
1/28
/200
130
Ne
t E
xa
mp
les -
Sin
gle
Dri
ve
r
�w
ire x
;
�w
ire x
, y;
�w
ire [
15:0
] data
, addre
ss;
�w
ire v
ect
ore
d [
0:7
] co
ntr
ol;
�data
[15]
(inst
antiation)
�addre
ss[1
5:8
] (inst
antiation)
�w
ire a
ddre
ss =
off
set
+ index;
1/28
/200
131
Ne
t E
xa
mp
les -
Mu
ltip
le
Dri
ve
rs a
nd
Co
nsta
nt
Ne
ts
�w
or
inte
rrupt_
1, in
terr
upt_
2;
�tr
i [3
1:0
] data
_bus,
opera
nd_bus;
1/28
/200
132
Init
ial V
alu
e &
Un
dec
lare
d
Ne
ts
�In
itia
l valu
e o
f a n
et
•At
t sim
= 0
, in
itia
l va
lue is
x.
�U
ndecl
are
d N
ets
-D
efa
ult t
ype
•N
ot
exp
licitly
decl
are
d d
efa
ult t
o w
ire
•defa
ult_nett
ype c
om
pile
r direct
ive c
an s
peci
fy
oth
ers
exc
ept
for
supply
0 a
nd s
upply
1
1/28
/200
133
Da
ta T
yp
es -
Re
gis
ter
Sem
an
tics
�re
g -
store
s a logic
valu
e
�in
teger
–st
ore
s va
lues
whic
h a
re n
ot
to b
e
store
d in h
ard
ware
•D
efa
ults
to s
imula
tion c
om
pute
r re
gis
ter
length
or
32
bits
whic
heve
r is
larg
er
•N
o r
anges
or
arr
ays
support
ed
•M
ay
yield
exc
ess
hard
ware
if
valu
e n
eeds
to b
e
store
d in h
ard
ware
; in
such
a c
ase
, use
siz
ed r
eg.
�tim
e -
store
s tim
e 6
4-b
it u
nsi
gned
�re
al -
store
s va
lues
as
real num
�re
altim
e -
store
s tim
e v
alu
es
as
real num
bers
1/28
/200
134
Re
gis
ter
Assig
nm
en
t
�A r
egis
ter
may
be a
ssig
ned v
alu
e o
nly
within
:
•a p
roce
dura
l st
ate
ment
•a u
ser-
defined s
equential prim
itiv
e
•a t
ask
, or
•a funct
ion.
�A r
eg o
bje
ct m
ay
neve
r by
ass
igned v
alu
e b
y:
•a p
rim
itiv
e g
ate
outp
ut
or
•a c
ontinuous
ass
ignm
ent
1/28
/200
135
Re
gis
ter
Ex
am
ple
s
�re
g a
, b, c;
�re
g [
15:0
] co
unte
r, s
hift_
reg;
�in
teger
sum
, diffe
rence
;
1/28
/200
136
Str
ing
s
�N
o e
xplic
it d
ata
type
�M
ust
be s
tore
d in r
eg (
or
arr
ay)
�re
g [
255:0
] buff
er;
//s
tore
s 32 c
hara
cters
1/28
/200
137
Co
nsta
nts
�D
ecl
ara
tion o
f para
mete
rs
•para
mete
r A =
2’b
00, B =
2’b
01, C =
2’b
10;
•para
mete
r re
gsi
ze =
8;
�re
g [
regsi
ze -
1:0
]; /
* illu
stra
tes
use
of
para
mete
r re
gsi
ze *
/
1/28
/200
138
Op
era
tors
�Arith
metic
(bin
ary
: +
, -,
*,/
,%*);
(unary
: +
, -)
�Bitw
ise (
~, &
,|,^
,~^
,^~
)
�Reduct
ion (
&,~
&,|
,~|,
^,~
^,^
~)
�Lo
gic
al (!
,&&
,||,
==
,!=
,==
=,!
==
)
�Rela
tional (<
,<=
,>,>
=)
�Shift
(>>
,<<
)
�Conditio
nal ?
:
�Conca
tenation a
nd R
eplic
ations
{,}
{int{
}}
* u
nsu
pport
ed f
or
variable
s
1/28
/200
139
Exp
ressio
n B
it W
idth
s
�D
epends
on:
•w
idth
s of
opera
nds
and
•ty
pes
of
opera
tors
�Verilo
g f
ills
in s
malle
r-w
idth
opera
nds
by
usi
ng
zero
ext
ensi
on.
�Fin
al or
inte
rmedia
te r
esu
lt w
idth
may
incr
ease
exp
ress
ion w
idth
1/28
/200
140
Exp
ressio
n B
it W
idth
s
�U
nsi
zed c
onst
ant
num
ber-
sam
e a
s in
teger
(usu
ally
32)
�Siz
ed c
onst
ant
num
ber
-as
speci
fied
�x o
p y
where
op is
+, -,
*, /,
%, &
, |,
^,
^~
:
•Arith
metic
bin
ary
and b
itw
ise
•Bit w
idth
= m
ax
(wid
th(x
), w
idth
(y))
1/28
/200
141
Exp
ressio
n B
it W
idth
s
(con
tinu
ed
)
�op x
where
op is
+, -
•Arith
metic
unary
•Bit w
idth
= w
idth
(x)
•Carr
y ca
n b
e c
aptu
red if
final re
sult w
idth
>
wid
th(x
)
�op x
where
op is
~
•Bitw
ise n
egation
•Bit w
idth
= w
idth
(x)
1/28
/200
142
Exp
ressio
n B
it W
idth
s
(con
tinu
ed
)
�x o
p y
where
op is
==
, !=
=, =
==
, !=
==
,&
&, ||
, >
, >
=, <
, <
= o
r op y
where
op is
!, &
, |,
^, ~
&, ~
|, ~
^
•Lo
gic
al, r
ela
tional and r
educt
ion
•Bit w
idth
= 1
�x o
p y
where
op is
<<
, >
>•
Shift
•Bit w
idth
= w
idth
(x)
1/28
/200
143
Exp
ressio
n B
it W
idth
s
(con
tinu
ed
)
�x
? y
: z
•Conditio
nal
•Bit w
idth
= m
ax(
wid
th(y
), w
idth
(z))
�{x
, …
, y}
•Conca
tenat
ion
•Bit w
idth
= w
idth
(x)
+ …
+ w
idth
(y)
�{x
{y, …
, z}
} •
Replic
ation
•Bit w
idth
= x
* (
wid
th(y
) +
… +
wid
th(z
))
1/28
/200
144
Exp
ressio
ns w
ith
Op
era
nds
Co
nta
inin
g x
or
z
�Arith
metic
•If
any
bit is
x or
z, r
esu
lt is
all
x’s.
•D
ivid
e b
y 0 p
roduce
s all
x’s.
�Rela
tional
•If
any
bit is
x or
z, r
esu
lt is
x.
�Lo
gic
al
•=
= a
nd !
= I
f any
bit is
x or
z, r
esu
lt is
x.
•=
==
and !
==
All
bits
incl
udin
g x
and z
valu
es
must
m
atc
h f
or
equalit
y
1/28
/200
145
Exp
ressio
ns w
ith
Op
era
nds
Co
nta
inin
g x
or
z
�Bitw
ise
•D
efined b
y ta
ble
s fo
r 0, 1, x,
z o
pera
nds.
�Reduct
ion
•D
efined b
y ta
ble
s as
for
bitw
ise o
pera
tors
.
�Shifts
•z
changed t
o x
. Vaca
ted p
osi
tions
zero
fill
ed.
�Conditio
nal
•If
conditio
nal exp
ress
ion is
am
big
uous
(e.g
., x
or
z),
both
exp
ress
ions
are
eva
luate
d a
nd b
itw
ise c
om
bin
ed
as
follo
ws:
f(1
,1)
= 1
, f(
0,0
) =
0, oth
erw
ise x
.
1/28
/200
146
Syn
thesis
fro
m V
eri
log
�N
ote
use
of
reg in b
ehavio
ral desc
riptions;
does
no
talw
ays
imply
act
ual st
ora
ge
such
as
latc
hes
or
regis
ters
in s
ynth
esi
s re
sults.
�Pro
cedura
l st
ate
ments
are
execu
ted
sequentially
.
1/28
/200
147
De
lay U
ses a
nd
Type
s
�Ig
nore
d b
y FPG
A E
xpre
ss;
may
be u
sefu
l fo
r si
mula
tion
�U
ses
•Behavi
ora
l (P
re-s
ynth
esi
s) T
imin
g S
imula
tion
•Test
bench
es
•G
ate
Leve
l (P
ost
-syn
thesi
s and P
re-L
ayo
ut)
Tim
ing
Sim
ula
tion
•Post
-Layo
ut
Tim
ing S
imula
tion
�Typ
es
•G
ate
Dela
y (I
nert
ial D
ela
y)
•N
et
Dela
y (T
ransp
ort
Dela
y)
•M
odule
Path
Dela
y1/
28/2
001
48
Tra
nspo
rt a
nd
In
ert
ial D
ela
y
�Tra
nsp
ort
dela
y -
pure
tim
e d
ela
y
�In
ert
ial dela
y•
Multip
le e
vents
cannot
occ
ur
on t
he o
utp
ut
in a
tim
e
less
than t
he d
ela
y.
�Exa
mple
AN
D w
ith d
ela
y =
2A B C C
Tra
nsp
ort
Del
ay
Iner
tial
Del
ay
1 n
s
1/28
/200
149
Ga
te P
ropa
ga
tion
De
lay
(In
ert
ial)
-S
yn
tax
(F
IO)
�dela
y3 :
:= #
dela
y_va
lue |
# (
dela
y_va
lue [
, dela
y_va
lue [
,dela
y_va
lue]]
)
�dela
y2 :
:= #
dela
y_va
lue |
# (
dela
y_va
lue
[,dela
y_va
lue])
�dela
y_va
lue :
:= u
nsi
gned n
um
ber
| para
mete
r_id
entifier
| co
nst
ant_
min
typm
ax_
exp
ress
ion
�co
nst
ant_
min
typm
ax_
exp
ress
ion :
:=
const
ant_
exp
ress
ion |
const
ant_
exp
ress
ion :
co
nst
ant_
exp
ress
ion :
const
ant_
exp
ress
ion
1/28
/200
150
Ga
te P
ropa
ga
tion
De
lay
(In
ert
ial)
-E
xa
mp
les
�N
o d
ela
y va
lue -
defa
ult
-dela
ys a
re a
ll 0.
•nor
(z, x1
x2)
�D
ela
y_va
lue -
unsi
gned_num
ber
= 1
-unit d
ela
y•
nor
#1 (
z, x
1, x2
);
�D
ela
y_va
lue -
unsi
gned_num
ber
≠1
-pro
p d
ela
y•
nor
#5 (
z, x
1, x2
);
�D
ela
y_va
lue -
para
mete
r_id
entifier
-allo
ws
easy
ch
ange o
f dela
y v
alu
e•
nor
#nor_
dela
y (z
, x1
,x2);
1/28
/200
151
Ga
te P
ropa
ga
tion
De
lay
(In
ert
ial)
-E
xa
mp
les (
FIO
)
�D
ela
y_va
lue2 -
unsi
gned_num
ber
-risi
ng d
ela
y,
falli
ng d
ela
y•
nor
#(1
,2)
(z, x1
, x2
);
�D
ela
y_va
lue3 -
unsi
gned_num
ber
-risi
ng d
ela
y,
falli
ng d
ela
y, tu
rnoff
dela
y•
nor
#(3
,2,4
) (z
, x1
, x2
);
�D
ela
y_va
lue3 -
const
ant_
min
typm
ax_
exp
ress
ion -
risi
ng d
ela
y -
min
:typ:m
ax, fa
lling d
ela
y -
min
:typ:m
ax,
turn
off
dela
y -
min
:typ:m
ax
•nor
#(2
:3:4
, 1:2
:5, 2:4
:6)
1/28
/200
152
Sim
ula
tion
Tim
e S
ca
les
�Com
pile
r D
irect
ive `
tim
esc
ale
<tim
e_unit>
/
<tim
e_pre
cisi
on>
�tim
e_unit -
the t
ime m
ultip
lier
for
tim
e v
alu
es
�tim
e_pre
cisi
on -
min
imum
ste
p s
ize d
uring
sim
ula
tion -
dete
rmin
es
roundin
g o
f num
erica
l va
lues
�Allo
wed u
nit/p
reci
sion v
alu
es:
{1|
10 |
100, s
| m
s |
us
| ns
| ps}
1/28
/200
153
�Exa
mple
:`tim
esc
ale
10ps
/ 1ps
nor
#3.5
7 (
z, x
1, x2
);
nor
dela
y use
d =
3.5
7 x
10 p
s =
35.7
ps
=>
36 p
s
�D
iffe
rent
tim
esc
ale
s ca
n b
e u
sed f
or
diffe
rent
sequence
s of
module
s
�The s
malle
st t
ime p
reci
sion d
ete
rmin
es
the
pre
cisi
on o
f th
e s
imula
tion.
�W
ill ignore
tim
e iss
ues
for
syst
em
task
s/fu
nct
ions
Sim
ula
tion
Tim
e S
ca
les
(con
tinu
ed
)
1/28
/200
154
Ne
t D
ela
y (
Tra
nspo
rt)
�D
ela
y a
ssig
ned t
o n
et
such
as
wire
�Type o
f dela
y (
inert
ial or
transp
ort
) defined b
y o
bje
ct a
ssig
ned t
o.
�Exam
ple
-Str
uct
ura
l:`tim
esc
ale
10ps
/1ps
wire #
4 N
25;
nor
#(2
0,3
0)
GA (
N25, x1
, x2
), G
B (
z, N
25, X3);
For
risi
ng o
utp
ut
from
x1 t
o z
, 300 +
40 +
200 =
540 p
s
1/28
/200
155
Ne
t D
ela
y (
Tra
nspo
rt)
�Exam
ple
-Continuous
Ass
ignm
ent
`tim
esc
ale
10ps
/1ps
wire #
4 N
25;\
\tra
nsp
ort
dela
y
ass
ign #
(20,3
0)
N25 =
~ (
x1 |
x2);
\\inert
ial dela
y
For
risi
ng o
utp
ut
from
x1 t
o N
25, 200 +
40 =
240 p
s
�Exam
ple
-Im
plic
it C
ontinuous
Ass
ignm
ent
`tim
esc
ale
10ps
/1ps
wire #
(24,3
4)
N25 =
~ (
x1 |
x2);
\\in
ert
ial dela
y only
For
risi
ng o
utp
ut
from
x1 t
o N
25, 240 p
s
1/28
/200
156
Mod
ule
Dela
y -
Exa
mp
le
�Add t
o m
odule
:
sp
ecif
y
(x1, x2 *
> z
) =
(18:2
5:3
3, 24,
31, 40);
en
dsp
ecif
y
�Speci
fies
min
imum
, ty
pic
al, a
nd m
axim
um
dela
ys
on p
ath
s fr
om
x1 t
o z
and x
2 t
o z
.
1/28
/200
157
Be
ha
vio
ral C
on
str
ucts
�Concu
rrent
com
munic
ating b
ehavi
ors
=>
pro
cess
es
sam
e a
s behavi
ors
�Tw
o c
onst
ruct
s•
init
ial-
one-t
ime s
equential act
ivity
flow
-not
synth
esiz
able
but
good f
or
test
bench
es
•A
lwa
ys -
cycl
ic (
repetitive
) se
quential act
ivity
flo
w
�U
se p
roce
dura
l st
ate
ments
that
ass
ign o
nly
re
gis
ter
variable
s (w
ith o
ne e
xception)
1/28
/200
158
Be
ha
vio
ral C
on
str
ucts
(con
tinu
ed
)
�Continuous
ass
ignm
ents
and p
rim
itiv
es
ass
ign
outp
uts
wheneve
r th
ere
are
eve
nts
on t
he
inputs
�Behavi
ors
ass
ign v
alu
es
when a
n a
ssig
nm
ent
state
ment
in t
he a
ctiv
ity
flow
exe
cute
s. I
nput
eve
nts
on t
he R
HS d
o n
ot
initia
te a
ctiv
ity
-co
ntr
ol m
ust
be p
ass
ed t
o t
he s
tate
ment.
1/28
/200
159
Be
ha
vio
ral C
on
str
ucts
(con
tinu
ed
)
�Body
may
consi
st o
f a s
ingle
sta
tem
ent
or
a
blo
ck s
tate
ment
�A b
lock
sta
tem
ent
begin
s w
ith b
eg
in a
nd e
nds
with e
nd
�Sta
tem
ents
within
a b
lock
sta
tem
ent
exe
cute
se
quentially
�Behavi
ors
are
an e
labora
te f
orm
of
continuous
ass
ignm
ents
or
prim
itiv
es
but
opera
te o
n
regis
ters
(w
ith o
ne e
xception)
rath
er
than n
ets
1/28
/200
160
Be
ha
vio
ral C
on
str
ucts
-
Exa
mp
le
�In
itia
l:❚
Alw
ays:
init
ial
alw
ays
be
gin
b
eg
in
one =
1;
F1 =
0, F2 =
0;
two =
one +
1;
# 2
F1 =
1;
thre
e =
tw
o +
1;
# 4
F2 =
0;
four
= t
hre
e +
1;
# 2
F1 =
1;
five
=
four
+ 1
;#
4;
en
de
nd
�W
hat
are
resu
lts
of
each
of
above?
1/28
/200
161
Pro
ce
du
ral A
ssig
nm
en
ts
�Typ
es
•=
blo
ckin
g a
ssig
nm
ent
•ass
ign =
continuous
ass
ignm
ent
•<
= n
on-b
lock
ing a
ssig
nm
ent
�Ass
ignm
ents
(w
ith o
ne e
xception)
to:
•re
g
•in
teger
•re
al
•re
altim
e
•tim
e
1/28
/200
162
Pro
ce
du
ral A
ssig
nm
en
ts -
Som
e R
ule
s
�Regis
ter
variable
can b
e r
efe
rence
d a
nyw
here
in m
odule
�Regis
ter
variable
can b
e a
ssig
ned o
nly
with p
roce
dura
l st
ate
men
t, t
ask
or
funct
ion
�Regis
ter
variable
cannot
be i
np
ut
or
ino
ut
�N
et
variable
can b
e r
efe
rence
d a
nyw
here
in m
odule
�N
et
variable
may
not
be a
ssig
ned w
ithin
behavi
or,
task
or
funct
ion. Exc
eption:
forc
e…
re
lea
se
�N
et
variable
within
a m
odule
must
be d
rive
n b
y prim
itiv
e, co
ntinuous
ass
ignm
ent,
forc
e…
re
lea
se
or
module
port
1/28
/200
163
Pro
ce
du
ral C
on
tin
uou
s
Assig
nm
en
t (F
IO)
�Tw
o t
ypes
•ass
ign …
deass
ign
�to
regis
ter
variable
�dyn
am
ic b
indin
g t
o t
arg
et
regis
ter
•fo
rce …
rele
ase
�to
regis
ter
or
net
variable
�dyn
am
ic b
indin
g t
o t
arg
et
regis
ter
or
net
variable
1/28
/200
164
Pro
ce
du
ral C
on
tin
uou
s
Assig
nm
en
t -E
xam
ple
s
�Exam
ple
1:
// Q
is
a r
eg. W
hat
does
this
desc
ribe?
alw
ays @
(cl
k)if
clk
= 1
assig
nQ
= D
;
els
e a
ssig
nQ
= Q
;
1/28
/200
165
Pro
ce
du
ral C
on
tin
uou
s
Assig
nm
en
t -M
ore
(F
IO)
�A P
roce
dura
l Continuous
Ass
ignm
ent
overr
ides
all
regula
r pro
cedura
l
ass
ignm
ents
to v
ariable
s
�Ass
ignm
ent
Modes
-See [
5]
Fig
ure
7-8
p.
172
1/28
/200
166
Pro
ce
du
ral T
imin
g,
Co
ntr
ols
& S
ynch
ron
iza
tion
�M
ech
anis
ms
•D
ela
y Contr
ol O
pera
tor
(#)
•Eve
nt
Contr
ol O
pera
tor
(@)*
•Eve
nt
or
•N
am
ed E
vents
•w
ait
const
ruct
*Ig
nore
d b
y FPG
A e
xpre
ss u
nle
ss a
syn
chro
nous
trig
ger
that
infe
rs a
regis
ter
1/28
/200
167
Pro
ce
du
ral T
imin
g,
Co
ntr
ols
& S
ynch
ron
iza
tion
�D
ela
y C
ontr
ol O
pera
tor
(#)
•Pre
cedes
ass
ignm
ent
state
ment
-post
pones
exe
cution o
f st
ate
ment
•For
blo
ckin
g a
ssig
nm
ent
(=),
dela
ys a
ll st
ate
ments
that
follo
w it
•Blo
ckin
g a
ssig
nm
ent
state
ment
must
exe
cute
befo
re s
ubse
quent
state
ments
can e
xecu
te.
•Exa
mple
: a
lwa
ys
@(p
ose
dg
ecl
k),
#10 Q
= D
;
1/28
/200
168
Pro
ce
du
ral T
imin
g,
Co
ntr
ols
& S
ynch
ron
iza
tion
�Event
Contr
ol O
pera
tor
(@)*
•Syn
chro
niz
es
the a
ctiv
ity
flow
of
a b
ehavi
or
to a
n e
vent
(change)
in a
regis
ter
or
net
variable
or
exp
ress
ion
•Exa
mple
1:
@ (
start
) RegA =
Data
;
•Exa
mple
2:
@(t
oggle
) b
eg
in… @
(p
ose
dg
ecl
k) Q
= D
;
…end
�“t
oggle
” above w
ill b
e ignore
d u
nle
ss in b
lock
*Ig
nore
d b
y FPG
A e
xpre
ss u
nle
ss a
syn
chro
nous
trig
ger
that
infe
rs a
regis
ter
1/28
/200
169
Pro
ce
du
ral T
imin
g,
Co
ntr
ols
& S
ynch
ron
iza
tion
�Event
or
-allo
ws
form
ation o
f event
expre
ssio
n
�Exam
ple
:
alw
ays
@ (
X1 o
rX2 o
rX3)
assig
nY =
X1 &
X2 |
~ X
3;
�All
RH
S v
ariable
s in
sensi
tivity lis
t and n
o
unsp
eci
fied c
onditio
nal re
sults
=>
co
mbin
ational lo
gic
1/28
/200
170
Pro
ce
du
ral T
imin
g,
Co
ntr
ols
& S
ynch
ron
iza
tion
�M
eanin
g o
f p
osed
ge:
0 -
> 1
, 0 -
> x
, x -
> 1
�Speci
al Exam
ple
:
alw
ays
@ (
set
or
rese
t o
rp
ose
dg
ecl
k)
be
gin
if (
rese
t =
= 1
) Q
= 0
;
els
e i
f(s
et
==
1)
Q =
1;
els
e i
f(c
lk =
= 1
) Q
= d
ata
;
en
d
// D
oes
this
work
corr
ect
ly?
Why
or
why
not?
1/28
/200
171
Pro
ce
du
ral T
imin
g, C
on
tro
ls
& S
ynch
ron
iza
tion
(FIO
)
�N
am
ed E
vents
mo
du
lecp
u (
…);
alw
ays
@ (
periphera
l.in
terr
upt)
be
gin ...
en
d
mo
du
le p
eriphera
l (…
);
eve
nt
inte
rrupt;
…
-> inte
rrupt;
1/28
/200
172
Pro
ce
du
ral T
imin
g, C
on
tro
ls &
Sync
hro
niz
ati
on
(F
IO)
�w
ait
Const
ruct
•Susp
ends
act
ivity
in b
ehavi
or
until exp
ress
ion
follo
win
g w
ait
is T
RU
E
�Exa
mple
:a
lwa
ys
be
gin a =
b;
c =
d;
wa
it(a
dva
nce
);
en
d
1/28
/200
173
Blo
ck
ing
Assig
nm
en
ts
�Id
entified b
y =
�Sequence
of blo
ckin
g a
ssig
nm
ents
exe
cute
s se
quentially
�Exa
mple
:a
lwa
ys
@(p
ose
dg
ecl
k)
be
gin
b =
0;
c =
0;
b =
a +
a;
c =
b +
a;
d =
c +
a;
en
d
1/28
/200
174
No
n-B
lockin
g A
ssig
nm
en
ts
�Id
entified b
y <
=
�Sequen
ce o
f non-b
lock
ing a
ssig
nm
ents
exe
cute
s co
ncu
rrently
�Exa
mple
1:
alw
ays@(posedgeclk)
begin b
<=
0;
c <
= 0
;
b <
= a
+ a
;
c <
= b
+ a
;
d <
= c
+
a;
end
/*Calc
ula
tes
b =
2a, c
= b
+ a
, d <
= c
+ a
. All
valu
es
use
d o
n
RH
S a
re t
hose
at
pose
dge c
lock
. N
ote
that
there
are
tw
o
ass
ignm
ents
to b
and c
. O
nly
the last
one is
effect
ive. */
1/28
/200
175
Blo
ck
ing
Assig
nm
en
ts -
Inte
r-A
ssig
nm
en
t D
ela
y
�D
ela
ys e
valu
ation o
f RH
S a
nd
ass
ignm
ent
to L
HS
�Exam
ple
:
always@(posedge
clk)
be
gin
b =
0;
c =
0;
b =
a +
a;
/
/ use
s a a
t pose
dge c
lock
#5 c
= b
+ a
; //
use
s a a
t pose
dge c
lock
+ 5
d =
c +
a;
//
use
s a a
t pose
dge c
lock
+ 5
en
d /
*c
= 2
a(a
t pose
dge c
lock
)+ a
(at
pose
dge c
lock
+ 5
)
d =
2 a
(at
pose
dge c
lock
) +
2 a
(at
pose
dge c
lock
+ 5
)*/
1/28
/200
176
�D
ela
ys a
ssig
nm
ent
to L
HS,
no
teva
luation o
f RH
S
�Exam
ple
:
alw
ays
@(p
ose
dg
ecl
k)
be
gin
b =
0;
c =
0;
b =
a +
a;
/
/ use
s a a
t pose
dge c
lock
c =
#5 b
+ a
; //
use
s a a
t pose
dge c
lock
d =
c +
a;
//
use
s a a
t pose
dge c
lock
+ 5
en
d /
* c
= 3
a(a
t pose
dge c
lock
)
d =
3a (
at
pose
dge c
lock
)+ a
(at
pose
dge c
lock
+ 5
)*/
Blo
ck
ing
Assig
nm
en
t -
Intr
a-A
ssig
nm
en
t D
ela
y
1/28
/200
177
No
n-B
lockin
g A
ssig
nm
en
t -
Inte
r-A
ssig
nm
en
t D
ela
y
�D
ela
ys e
valu
ation o
f RH
S a
nd
ass
ignm
ent
to L
HS
�D
ela
ys s
ubse
quent
state
ments
�Exam
ple
:
alw
ays
@(posedge
clk)
begin
b <
= 0
; c
<=
0;
b <
= a
+ a
; /
/ use
s a a
t pose
dge c
lock
#5 c
<=
b +
a;
// u
ses
b a
nd a
at
pose
dge c
lock
+ 5
d <
= c
+
a;
//
use
s a a
t pose
dge c
lock
+ 5
end
/*c
= b
(at
pose
dge c
lock
+ 5
) +
a(a
t pose
dge c
lock
+ 5
) d =
c(a
t pose
dge c
lock
+ 5
) +
a (
at
pose
dge c
lock
+5)
*/
1/28
/200
178
No
n-B
lockin
g A
ssig
nm
en
t -
Intr
a-A
ssig
nm
en
t D
ela
y
�D
ela
ys o
nly
ass
ignm
ent
to L
HS
�Exam
ple
:
alw
ays
@(posedge
clk)
begin
b <
= 0
; c
<=
0;
b <
= a
+ a
; /
/ use
s a a
t pose
dge c
lock
c <
= #
5 b
+ a
; //
use
s a and b
at
pose
dge c
lock
d <
= c
+
a;
//
use
s a and c
at
pose
dge c
lock
en
d
/* C
alc
ula
tes
*c(
pose
dge c
lock
+ 5
) =
b(a
t pose
dge c
lock
) +
a(a
t pose
dge c
lock
); d(p
ose
dge c
lock
) =
c(at
pose
dge c
lock
) +
a (
at
pose
dge c
lock
) */
1/28
/200
179
Mix
ed
Blo
ck
ing
/Non-
Blo
ck
ing
Assig
nm
en
ts
�Exa
mple
1: alw
ays
@(posedge
clk)
begin
b =
0;
c =
0;
d =
0;
b =
a +
a;
c <
= b
+ a
+ d
;
d =
c +
a;
end
/*Calc
ula
tes
b =
2a, c
= 2
a, d =
a s
ince
1)
RH
S o
f c
evalu
ate
s
when s
tate
ment
reach
ed, but
LH
S a
ssig
ned t
o c
last
aft
er
all
blo
ckin
g a
ssig
nm
ents
incl
udin
g t
hat
for
d a
nd 2
) ass
ignm
ent
of c
does
not
dela
y e
xecu
tion o
f evalu
ation o
f d *
/
1/28
/200
180
Mix
ed
Blo
ck
ing
/Nonb
loc
kin
g
Assig
nm
en
ts
�Exa
mple
: alw
ays
@(posedge
clk)
begin d
<=
0;
b =
a +
a;
c =
b +
a;
d <
= c
+
a;
c =
d +
a;
end
/* S
ince
the d
<=
c +
a is
non-b
lock
ing,
c =
d +
a p
roce
eds
to
execu
te b
efo
re t
he a
ssig
nm
ent
of d <
= c
+ a
. The r
esu
ltin
g
valu
es
calc
ula
ted a
re b
= 2
a, d =
4a, and c
= a
+ d
(valu
e
of d is
that
at
pose
dge c
lk, not
that
due t
o n
on-b
lock
ing
ass
ignm
ent
state
ment.
*/
1/28
/200
181
Mix
ed
Blo
ck
ing
/Nonb
loc
kin
g
Assig
nm
en
t
�For
synth
esi
s in
ECE 5
54:
•A g
iven r
egis
ter
can h
ave
either
blo
ckin
g o
r non-b
lock
ing a
ssig
nm
ents
, not
both
.
•D
ela
ys c
annot
be u
sed in a
lways
sta
tem
ents
w
ith m
ixed a
ssig
nm
ents
•It
is
advi
sable
to a
void
the c
onfu
sion o
f th
e
prior
exa
mple
to w
rite
code w
ith a
ll non-
blo
ckin
g a
ssig
nm
ents
last
am
ong t
he c
ode
state
ments
1/28
/200
182
Ac
tivit
y C
on
tro
l
Overv
iew
�Const
ruct
s fo
r Act
ivity
Contr
ol
•Conditio
nal opera
tor
•ca
se s
tate
ment
•if …
els
e s
tate
ment
•Lo
ops
:re
peat,
for,
while
, fo
reve
r
•dis
able
sta
tem
ent
•fo
rk…
join
state
men
t
�Task
s and F
unct
ions
1/28
/200
183
Co
nd
itio
na
l O
pe
rato
r
�?
… :
�Sam
e a
s fo
r use
in c
ontinuous
ass
ignm
ent
state
ment
for
net
types
exce
pt
applie
d t
o
regis
ter
types
�Exam
ple
:
alw
ays
@(p
ose
dge c
lock
)Q
<=
S ?
A :
B /
/com
bin
ed D
FF a
nd 2
-to-1
MU
X
1/28
/200
184
Ca
se
Sta
tem
en
t (F
IO)
�ca
se S
ynta
x:
case
_st
ate
ment
::=
ca
se
(exp
ress
ion)
case
_item
{ca
se_item
} e
nd
ca
se
| ca
se
x(e
xpre
ssio
n)
case
_item
{ca
se_item
} e
nd
ca
se
| ca
se
z(e
xpre
ssio
n)
case
_item
{ca
se_item
} e
nd
ca
se
case
_item
::=
exp
ress
ion {
,exp
ress
ion}
: st
ate
men
t_or_
null
|defa
ult [
:] s
tate
men
t_or_
null
state
men
t_or_
null
::=
sta
tem
ent
| ;
1/28
/200
185
case
Sta
tem
en
t
�Requires
com
ple
te b
itw
ise m
atc
h o
ver
all
four
valu
es
so e
xpre
ssio
n a
nd c
ase
ite
m e
xpre
ssio
n
must
have
sam
e b
it length
�Exa
mple
: a
lwa
ys@
(sta
te, x)
be
gin
reg
[1:0
] sta
te;
case
(sta
te)
2’b
00:
next_
state
<=
s1;
2’b
01:
next_
state
<=
s2;
2’b
10:
if x
next_
state
<=
s0;
els
enext_
state
<=
s1;
en
d
de
fau
ltnext_
state
= 1
’bxx;
en
dca
se
en
d1/
28/2
001
86
case
x S
tate
me
nt
�Requires
bitw
ise m
atc
h o
ver
all
but
posi
tions
conta
inin
g x
or
z; e
xecu
tes
firs
t m
atc
h e
nco
unte
red
if m
ultip
le m
atc
hes.
�Exa
mple
:a
lwa
ys@
(code)
be
gin
ca
se
x (
code)
2’b
0x:
contr
ol <
= 8
’b00100110;
//sa
me for
2’b
0z
2’b
10:
contr
ol <
= 8
’b11000010;
2’b
11:
contr
ol <
= 8
’b00111101;
de
fau
lt c
ontr
ol <
= 8
b’x
xxxxxxx;
en
dca
se
en
d
1/28
/200
187
case
z S
tate
me
nt
�Requires
bitw
ise m
atc
h o
ver
all
but
posi
tions
conta
inin
g z
or
? (?
is
exp
licit d
on’t c
are
);
exe
cute
s firs
t m
atc
h e
nco
unte
red if
multip
le
matc
hes.
�Exa
mple
:re
g[1
:0]
code;
alw
ays@
(code)
be
gin
ca
se
z (
code)
2’b
0z:
contr
ol <
= 8
’b00100110;
2’b
1?:
contr
ol <
= 8
’b11000010;
de
fau
lt c
ontr
ol <
= 8
b’x
xxxxxxx;
en
dca
se
en
d
1/28
/200
188
Co
nd
itio
na
l (i
f …
els
e)
Sta
tem
en
t E
xa
mp
le
alw
ays@
(a o
r b o
r c)
be
gin
if (
a =
= b
)
be
gin
q <
= d
ata
;
stop <
= 1
’b1;
en
d
els
e
i
f (a
> b
)
q <
= a
;
els
e
q <
= b
;
en
d
en
d
en
d
1/28
/200
189
Co
nd
itio
na
l (i
f …
els
e)
Sta
tem
en
t (c
on
tin
ue
d)
�M
ust
be c
are
ful to
define o
utc
om
e f
or
all
poss
ible
conditio
ns
–fa
ilure
do d
o s
o c
an c
ause
unin
tentional in
fere
nce
of
latc
hes!
�e
lse
is p
aired w
ith n
eare
st i
fw
hen a
mbig
uous
-use
be
gin
and e
nd
in n
est
ing t
o c
larify
.
�N
est
ed i
f…
els
ew
ill g
enera
te a
“se
rial”
or
priority
lik
e c
ircu
it in s
ynth
esi
s w
hic
h m
ay
have
a v
ery
long d
ela
y -
bett
er
to u
se c
ase
state
ments
to g
et
“para
llel”
circu
it.
1/28
/200
190
for
Loop
Ex
am
ple
�Exa
mple
:
init
ial
inte
ge
rr,
I;
be
gin r
= 0
;
for
(i =
1;
i <
= 7
; i =
i +
2)
be
gin
r[i] =
1;
en
d
en
d
�If
the loop a
bove
were
in t
ime r
ath
er t
han
space
, sh
ould
use
re
gin
stead o
f in
teg
er!
1/28
/200
191
wh
ile
Lo
op
Ex
am
ple
�N
ot
syn
the
siz
ab
le s
ince
fo
rms c
om
bin
ati
on
al
loo
p!
init
ial
be
gin r
= 0
;
i =
0;
wh
ile
(i <
= 7
)
be
gin
r[2*i +
1]
= 1
;
i =
i +
1;
en
d
en
d1/
28/2
001
92
fore
ve
r L
oo
p E
xa
mp
le
init
ial
be
gin cl
k =
0;
fore
ve
r be
gin
#50 c
lk =
1;
#50 c
lk =
0;
en
d
en
d
�U
sually
use
d in t
est
bench
es
rath
er
than
for
synth
esiz
ed logic
.
1/28
/200
193
Task
s (
FIO
)
�D
ecl
are
d w
ithin
a m
odule
�Refe
rence
d o
nly
by
a b
ehavi
or
within
the m
odule
�Para
mete
rs p
ass
ed t
o t
ask
as
inputs
and inouts
and fro
m t
ask
as
outp
uts
or
inouts
�Lo
cal va
riable
s ca
n b
e d
ecl
are
d
�Recu
rsio
n n
ot
support
ed a
lthough n
est
ing
perm
itte
d (
nest
ed c
opie
s of
variable
s use
sam
e
stora
ge)
�See F
ig. 7.4
3 p
. 226 o
f [5
]for
rule
s
1/28
/200
194
Task
s (
FIO
)
�Syn
tax
task
_decl
ara
tion :
:=
task
task
_id
entifier
{task
_item
_decl
ara
tion}
state
men
t or
null
en
dta
sk
1/28
/200
195
Task
Ex
am
ple
taskleading_1;
input
[7:0
] data
_w
ord
;
ou
tpu
t[2
:0]
posi
tion;
reg
[7:0
] te
mp;
reg
[2:0
] posi
tion;
be
gin
tem
p =
data
_w
ord
;
posi
tion =
3'b
111;
wh
ile
(!te
mp[7
])
@(p
ose
dge c
lock
) //
*
begin
tem
p =
tem
p <
< 1
;
posi
tion =
posi
tion -
1;
en
d
en
d
en
dta
sk
//
* T
his
ma
y n
ot
wo
rk –
un
cle
ar
co
ntr
ad
icto
ry
sta
tem
en
ts i
n F
PG
A E
xp
ress d
ocu
me
nta
tio
n.
1/28
/200
196
Func
tion
s (
FIO
)
�Im
ple
ment
com
bin
ational behavi
or
�N
o t
imin
g c
ontr
ols
or
task
s w
hic
h im
plie
s no
wh
ile
�M
ay
call
oth
er
funct
ions
with n
o r
ecu
rsio
n
�Refe
rence
in a
n e
xpre
ssio
n, e.g
. RH
S
�N
o o
utp
ut
or
inout
allo
wed
�Im
plic
it r
egis
ter
havi
ng n
am
e a
nd r
ange o
f fu
nct
ion
1/28
/200
197
Func
tion
s (
FIO
)
�Synta
x:
funct
ion_decl
ara
tion :
:=
fun
cti
on
[range o
r ty
pe]
funct
ion_id
entifier;
funct
ion_ca
ll ::
=
funct
ion_id
entifier
(exp
ress
ion {
, exp
ress
ion})
�Exa
mple
:posi
tion =
leadin
g_1(d
ata
_va
l);
1/28
/200
198
Func
tion
Exa
mp
le
fun
cti
on
[2:0
] le
adin
g_1;
inp
ut
[7:0
] data
_w
ord
;
reg
[7:0
] te
mp;
be
gin
tem
p =
data
_w
ord
;
leadin
g_1 =
3'b
111;
wh
ile
(!te
mp[7
])
beg
in
tem
p =
tem
p <
< 1
;
leadin
g_1 =
leadin
g_1 -
1;
en
d
en
d
en
dfu
ncti
on
�Is
th
e a
bo
ve
co
de
syn
the
siz
ab
le? N
o
1/28
/200
199
Fin
ite
Sta
te M
ac
hin
es -
Exp
lic
it a
nd
Im
plic
it M
ode
ls
�Explic
it -
decl
are
s a s
tate
regis
ter
that
store
s th
e F
SM
sta
te
�Im
plic
it -
desc
ribes
state
im
plic
itly
by
usi
ng m
ultip
le e
vent
contr
ols
�M
ealy
vers
us
Moore
types
1/28
/200
110
0
Type
s o
f E
xp
lic
it M
od
els
�Sta
te r
egis
ter
-Com
bin
ational next
state
and o
utp
ut
logic
�Sta
te r
egis
ter
-Com
bin
ational next
state
lo
gic
-Com
bin
ational outp
ut
logic
�Sta
te r
egis
ter
-Com
bin
ational next
state
lo
gic
-R
egis
tere
d o
utp
ut
logic
1/28
/200
110
1
Sta
te r
eg
iste
r -
Co
mb
ina
tio
na
l
ne
xt
sta
te a
nd
ou
tpu
t lo
gic
Nex
t Sta
te a
nd
Out
put L
ogic
FF
Sta
te R
egis
ter
Inpu
tsO
utpu
ts
1/28
/200
110
2
Sta
te r
eg
iste
r -
Co
mb
ina
tio
na
l n
ex
t
sta
te lo
gic
-C
om
bin
ati
on
al o
utp
ut
log
ic
Nex
t Sta
teLo
gic
FF
Sta
te R
egis
ter
Inpu
tsO
utpu
tsO
utpu
tLo
gic
Mea
ly
1/28
/200
110
3
Sta
te r
eg
iste
r -
Co
mb
ina
tio
na
l n
ex
t
sta
te a
nd
ou
tpu
t lo
gic
-O
utp
ut
reg
iste
r
Nex
t Sta
te a
nd
Out
put L
ogic
FF
Sta
te R
egis
ter
Inpu
tsO
utpu
tsF
F
Out
put R
egis
ter
1/28
/200
110
4
Sta
te r
eg
iste
r -
Co
mb
ina
tio
na
l n
ex
t
sta
te lo
gic
-R
eg
iste
red
ou
tpu
t lo
gic
Nex
t Sta
teLo
gic
FF
Sta
te R
egis
ter
Inpu
ts
Out
put R
egis
ter
Out
put
Logi
c
Mea
ly
FF
Out
puts
1/28
/200
110
5
FS
M E
xa
mp
le: W
ashe
r
star
t_s
was
h_s
drai
n_s
wrin
g_s
fill_
s
rese
t = 1star
t = 0
empt
y =
0
full
= 0
timeo
ut =
0
wat
er =
1
full
= 1
star
t = 1
empt
y =
1
timeo
ut =
1
timeo
ut =
0
timeo
ut =
1
spin
= 1
spin
= 1
drai
n =
1
/tim
eset
= 1
/tim
eset
= 1
1/28
/200
110
6
Ve
rilo
g -
sta
te r
eg
iste
r -
ne
xt
sta
te a
nd
ou
tpu
t lo
gic
module
contr
ol_
es1
(re
set,
clk
, st
art
, fu
ll,
em
pty
, tim
eout,
dra
in,
spin
, tim
ese
t,
wate
r);
//st
ate
regis
ter
-co
mbin
ed n
ext
state
and
outp
ut
logic
inp
ut
rese
t, c
lk,
start
, fu
ll, e
mpty
, tim
eout;
ou
tpu
tdra
in,
spin
, tim
ese
t, w
ate
r;
reg
dra
in,
spin
, tim
ese
t, w
ate
r;
reg
[2:0
] st
ate
, next_
state
;
pa
ram
ete
rst
art
_s
= 3
'b000,
fill_
s =
3'b
001,
wash
_s
= 3
'b010,
dra
in_s
= 3
'b011,
wring_s
= 3
'b100;
alw
ay
s@
(po
se
dg
eclk
or
po
se
dg
ere
set)
be
gin
if (
rese
t) s
tate
<=
sta
rt_s;
els
e i
f(c
lk)
state
<=
next_
state
;
en
d
alw
ay
s@
(sta
te o
r st
art
or
full
or
em
pty
or
tim
eout)
be
gin
dra
in <
= 1
'b0;
spin
<=
1'b
0;
tim
ese
t <
= 1
'b0;
wate
r <
= 1
'b0;
// a
bove s
ets
outp
uts
to d
efa
ult v
alu
e -
in t
he
follo
win
g,
// o
nly
outp
ut
changes
to 1
are
speci
fied
ca
se
(st
ate
)
start
_s:
if
(sta
rt)
next_
state
<=
fill
_s;
els
enext_
state
<=
sta
rt_s;
fill_
s: b
eg
in
wate
r <
= 1
'b1;
if(f
ull)
begin
next_
state
<=
wash
_s;
tim
ese
t <
= 1
'b1;
en
d
els
e
next_
state
<=
fill
_s;
en
d
1/28
/200
110
7
Ve
rilo
g -
sta
te r
eg
iste
r -
ne
xt
sta
te a
nd
ou
tpu
t lo
gic
(c
on
tin
ue
d)
wash
_s:
be
gin
spin
<=
1'b
1;
if(t
imeout)
next_
state
<=
dra
in_s;
els
e
next_
state
<=
wash
_s;
en
d
dra
in_s:
be
gin
dra
in <
= 1
'b1;
if(e
mpty
) b
eg
in
next_
state
<=
wring_s;
tim
ese
t <
= 1
'b1;
en
d
els
e
next_
state
<=
dra
in_s;
en
d
wring_s:
be
gin
spin
<=
1'b
1;
dra
in <
= 1
’b1;
if (
tim
eout)
next_
state
<=
sta
rt_s;
els
e
next_
state
<=
wring_s;
en
d
de
fau
lt n
ext_
state
<=
sta
rt_s;
en
dca
se
en
d
en
dm
od
ule
1/28
/200
110
8
Ve
rilo
g -
sta
te r
eg
iste
r -
ne
xt
sta
te l
og
ic a
nd
ou
tpu
t lo
gic
(F
IO)
mo
du
leco
ntr
ol_
el1
(re
set,
clk
, st
art
, fu
ll, e
mpty
, tim
eout,
dra
in,
spin
, tim
ese
t, w
ate
r);
//st
ate
regis
ter
-next
state
logic
and o
utp
ut
logic
inp
ut
rese
t, c
lk,
start
, fu
ll, e
mpty
, tim
eout;
ou
tpu
tdra
in,
spin
, tim
ese
t, w
ate
r;
reg
dra
in,
spin
, tim
ese
t, w
ate
r;
reg
[2:0
] st
ate
, next_
state
;
pa
ram
ete
rst
art
_s
= 3
'b000,
fill_
s =
3'b
001,
wash
_s
= 3
'b010,
dra
in_s
= 3
'b011,
wring_s
= 3
'b100;
alw
ay
s@
(po
se
dg
eclk
or
po
se
dg
ere
set)
be
gin
if (
rese
t) s
tate
<=
sta
rt_s;
els
e i
f(c
lk)
state
<=
next_
state
;
en
d
alw
ay
s@
(sta
te o
r st
art
or
full
or
em
pty
or
tim
eout)
be
gin c
ase
(st
ate
)
start
_s:
if
(sta
rt)
next_
state
<=
fill
_s;
els
enext_
state
<=
sta
rt_s;
fill_
s: b
eg
in
if(f
ull)
begin
next_
state
<=
wash
_s;
tim
ese
t <
= 1
'b1;
en
d
els
e
next_
state
<=
fill
_s;
en
d
wash
_s:
be
gin
if(t
imeout)
next_
state
<=
dra
in_s;
els
enext_
state
<=
wash
_s;
en
d
1/28
/200
110
9
Ve
rilo
g -
sta
te r
eg
iste
r -n
ex
t sta
te lo
gic
an
d o
utp
ut
log
ic (
co
nti
nu
ed
) (F
IO)
dra
in_s:
be
gin
if(e
mpty
) next_
state
<=
wring_s;
els
enext_
state
<=
dra
in_s;
en
d
wring_s:
be
gin
if(t
imeout)
next_
state
<=
sta
rt_s;
els
enext_
state
<=
wring_s;
en
d
de
fau
ltnext_
state
<=
sta
rt_s;
en
dca
se
en
d
alw
ay
s@
(sta
te o
r fu
ll or
em
pty
)
dra
in <
= 1
'b0;
spin
<=
1'b
0;
tim
ese
t <
= 1
'b0;
wate
r <
= 1
'b0;
// s
ets
outp
uts
to d
efa
ult v
alu
e -
in t
he
follo
win
g,
// o
nly
outp
ut
changes
to 1
are
speci
fied
ca
se
(st
ate
)
start
_s:
;
fill_
s: b
eg
in
wate
r <
= 1
'b1;
if(f
ull)
tim
ese
t <
= 1
'b1;
en
d
wash
_s:
spin
<=
1’b
1;
dra
in_s:
be
gin
dra
in <
= 1
'b1;
if(e
mpty
) tim
ese
t <
= 1
'b1;
en
d
wring_s:
be
gin
spin
<=
1’b
1;
dra
in
<=
1’b
1;
en
dca
se
en
d
en
dm
od
ule
1/28
/200
111
0
Ve
rilo
g -
Sta
te r
eg
iste
r -
Co
mb
ina
tio
na
l
ne
xt
sta
te a
nd
ou
tpu
t lo
gic
-O
utp
ut
reg
iste
r (F
IO)
�Sam
e a
s st
ate
and o
utp
ut
regis
ter
-st
ate
and
outp
ut
logic
�Sam
e a
s co
mbin
ed s
tate
and o
utp
ut
logic
and
regis
ters
�Both
sta
te a
nd o
utp
uts
are
fro
m f
lip-f
lops
and
synch
roniz
ed w
ith t
he c
lock
.
1/28
/200
111
1
Ve
rilo
g -
Sta
te r
eg
iste
r -
Co
mb
ina
tio
na
l n
ex
t
sta
te a
nd
ou
tpu
t lo
gic
-O
utp
ut
reg
iste
r (F
IO)
�If
dela
y o
f th
e o
utp
ut
for
one c
lock
cycl
e
acc
epta
ble
, th
en s
am
e o
utp
ut
logic
can f
eed
outp
ut
flip
-flo
p inputs
as
origin
ally
feed
com
bin
ational outp
uts
�Suppose
outp
uts
are
to o
bey s
peci
fica
tions
on a
cl
ock
cycl
e s
peci
fic
basi
s, i. e., a
re n
ot
dela
yed
�Then t
he o
utp
ut
flip
-flo
p D
-input
funct
ions
must
be d
efined o
ne c
ycl
e e
arlie
r th
an t
he n
orm
al
com
bin
ational outp
ut.
1/28
/200
111
2
�H
ow
is
this
done?
�Exa
mple
:
�M
(t +
1)
= A
X +
B Y
+ C
Z (
Moore
)
�N
(t +
1):
Im
poss
ible
! (M
ealy
)
Ve
rilo
g -
Sta
te r
eg
iste
r -
Co
mb
ina
tio
na
l n
ex
t
sta
te a
nd
ou
tpu
t lo
gic
-O
utp
ut
reg
iste
r (F
IO)
A
Z =
0
M =
1Z
= 1
X =
1C
N =
1
B
Y =
1
1/28
/200
111
3
Ve
rilo
g -
Sta
te r
eg
iste
r -
Co
mb
ina
tio
na
l n
ex
t
sta
te a
nd
ou
tpu
t lo
gic
-O
utp
ut
reg
iste
r (F
IO)
module
contr
ol_
er1
(re
set,
clk
, st
art
, fu
ll, e
mpty
, tim
eout,
dra
in,
spin
, tim
ese
t, w
ate
r);
//st
ate
regis
ter
-co
mbin
ed n
ext
state
and o
utp
ut
logic
-outp
ut
regis
ter
inp
ut
rese
t, c
lk,
start
, fu
ll, e
mpty
, tim
eout;
ou
tpu
tdra
in,
spin
, tim
ese
t, w
ate
r;
reg
dra
in,
spin
, tim
ese
t, w
ate
r;
reg
[2:0
] st
ate
, next_
state
;
pa
ram
ete
rst
art
_s
= 3
'b000,
fill_
s =
3'b
001,
wash
_s
= 3
'b010,
dra
in_s
= 3
'b011,
wring_s
=
3'b
100;
alw
ay
s@
(po
se
dg
eclk
or
po
se
dg
ere
set)
be
gin
dra
in <
= 1
'b0;
spin
<=
1'b
0;
tim
ese
t <
= 1
'b0;
wate
r <
= 1
'b0;
// s
ets
outp
uts
to d
efa
ult v
alu
e -
in t
he f
ollo
win
g,
// o
nly
outp
ut
changes
to 1
are
speci
fied
if (
rese
t) s
tate
<=
sta
rt_s;
els
e i
f (c
lk)
ca
se
(st
ate
)
start
_s:
if
(sta
rt)
be
gin
state
<=
fill
_s;
wate
r <
= 1
’b1;
en
d
els
est
ate
<=
sta
rt_s;
fill_
s:
if(f
ull)
be
gin
state
<=
wash
_s;
spin
<=
1’b
1;
en
d
els
e b
eg
in
state
<=
fill
_s;
wate
r <
= 1
'b1;
tim
ese
t <
= 1
’b1;
en
d
1/28
/200
111
4
Ve
rilo
g -
Sta
te r
eg
iste
r -
Co
mb
ina
tio
na
l n
ex
t
sta
te a
nd
ou
tpu
t lo
gic
-O
utp
ut
reg
iste
r
(co
nti
nu
ed
)(F
IO)
wash
_s:
if(t
imeout)
be
gin
state
<=
dra
in_s;
dra
in <
= 1
’b1;
en
d
els
e s
pin
<=
1'b
1;
dra
in_s:
b
eg
in
dra
in <
= 1
’b1;
if(e
mpty
) b
eg
in
state
<=
wring_s;
spin
<=
1’b
1;
en
d
els
e b
eg
in
state
<=
dra
in_s;
dra
in <
= 1
'b1;
tim
ese
t <
= 1
'b1;
en
d
en
d
wring_s:
if(t
imeout)
state
<=
sta
rt_s;
els
e b
eg
in
state
<=
wring_s;
spin
<=
1'b
1;
dra
in <
=1’b
1;
en
d
de
fau
lt n
ext_
state
<=
sta
rt_s;
en
dca
se
en
d
en
dm
od
ule
1/28
/200
111
5
Ve
rilo
g -
Sta
te r
eg
iste
r -
Co
mb
ina
tio
na
l
ne
xt
sta
te a
nd
ou
tpu
t lo
gic
-O
utp
ut
reg
iste
r (c
on
tin
ue
d)(
FIO
)
�H
ow
is
(Mealy
) tim
ese
t handle
d?
•Tim
ese
t is
not
“use
d”
while
in s
tate
s fill_
s and
dra
in_s.
•Tim
e v
alu
e is
fixe
d d
uring last
cyc
le b
efo
re c
onditio
ns
to leave
these
sta
tes,
full
= 1
and e
mpty
= 1
, re
spect
ively
, occ
ur.
•Can “
ham
mer
” tim
ese
t eve
ry c
lock
cyc
le u
ntil
conditio
n t
o leave
these
sta
tes
stat
es
satisf
ied.
•End r
esu
lt in t
erm
s of lo
adin
g t
he t
ime v
alu
e is
the
sam
e a
s fo
r origin
al desi
gn
�W
ork
s only
for
speci
fic
conditio
ns!
1/28
/200
111
6
Imp
lic
it M
ode
l
�M
ore
abst
ract
repre
senta
tion
�Rest
rict
ed t
o s
truct
ure
s in
whic
h a
giv
en s
tate
ca
n b
e e
nte
red fro
m o
nly
one o
ther
state
!
�Yie
lds
sim
ple
r co
de
�D
esc
ription o
f re
set
behavio
r m
ore
com
ple
x
�Cile
tti exam
ple
s not
good illu
stra
tions
[5]
�For
novic
e, good r
oute
to d
isast
er!
1/28
/200
111
7
Co
mp
ile
r D
ire
cti
ve
s
�U
sefu
l fo
r co
ntr
olli
ng w
hat
is s
ynth
esi
zed a
nd
the r
esu
ltin
g logic
�W
arn
ing:
Not
reco
gniz
ed b
y o
ther
com
pile
rs –
there
fore
reduce
code p
ort
abili
ty
�Exam
ple
s:•
// s
ynopsy
s tr
ansl
ate
_off
Code h
ere
desc
ribes
som
eth
ing t
hat
is n
ot
to b
e
synth
esiz
ed s
uch
at
a si
mula
tion t
est
bench
-
can c
onta
in n
on-s
ynth
esi
zable
const
ruct
s su
ch a
s dela
ys)
// sy
nopsy
s tr
ansl
ate
_on
1/28
/200
111
8
Co
mp
ile
r D
ire
cti
ve
s
(Co
nti
nu
ed
)
�Exam
ple
s:•
// s
ynopsy
s para
llel_
case
Forc
es
genera
tion o
f m
ultip
lexe
r-lik
e s
truct
ure
in
stead o
f priority
str
uct
ure
when incl
uded a
fter
case
decl
ara
tion
•//
syn
opsy
s fu
ll_ca
se
Indic
ate
s th
at
all
case
s have
been c
onsi
dere
d w
hen
incl
uded in c
ase
decl
ara
tion;
when
use
d, no d
efa
ult
state
men
t needed a
nd latc
hes
will
not
be infe
rred
can b
e u
sed in c
om
bin
ation w
ith p
ara
llel ca
se:
case
(sta
te)
// s
ynopsy
s para
llel_
case
full_
case
1/28
/200
111
9
Co
mp
ile
r D
ire
cti
ve
s
(Co
nti
nu
ed
)
�O
ther
Direct
ives
•For
FSM
s:�
// s
ynopsy
s st
ate
_ve
ctor
�//
syn
opsy
s enum
•For
inst
antiating m
odule
s in
behavio
ral
(alw
ays)
code
�//
syn
opsy
s m
ap_to
_m
odule
module
nam
e
�//
syn
opsy
s re
turn
_port
_nam
e p
ort
nam
e
�See C
hapte
r 8 o
f [2
]
1/28
/200
112
0
Sim
ula
tion
an
d
Testb
ench
es
�G
eneric
Sim
ula
tion S
truct
ure
UU
TM
od
ule
Tes
t V
ecto
rs,
Fo
rce
File
s,W
avef
orm
s
Sti
mu
lus
Res
po
nse
Vec
tors
,W
avef
orm
s
Res
po
nse
1/28
/200
112
1
Testb
ench
Ap
pro
ach
�U
se V
erilo
g m
odule
to p
roduce
test
ing
environm
ent
incl
udin
g s
tim
ulu
s genera
tion
and/o
r re
sponse
monitoring
UU
TM
od
ule
Sti
mu
lus
Res
po
nse
Tes
tben
ch M
od
ule
1/28
/200
112
2
Sti
mu
lus G
en
era
tio
n
Ex
am
ple
`tim
esc
ale
1ns
/1ns
module
com
_te
st_bench
_v;
reg[8
:0]
stim
;
wire[3
:0]
S;
wire C
4;
adder_
4_b_v
a1(s
tim
[8:5
], s
tim
[4:1
], s
tim
[0],
S, C4);
//Continued o
n n
ext
slid
e
endm
odule
1/28
/200
112
3
Sti
mu
lus G
en
era
tio
n
Ex
am
ple
(C
on
tin
ue
d)
//G
ener
ate
stim
ulu
s
initia
l
begin
stim
= 9
'b000000000;
#10 s
tim
= 9
'b111100001;
#10 s
tim
= 9
'b000011111;
#10 s
tim
= 9
'b111100010;
#10 s
tim
= 9
'b000111110;
#10 s
tim
= 9
'b111100000;
#10 s
tim
= 9
'b000011110;
#10 $
stop;
end
1/28
/200
112
4
Oth
er
Testb
enc
h S
tim
uli
Ge
ne
rato
rs
�Counte
rs (
Good f
or
up t
o 8
or
9 input
Variable
s)
�Lin
ear
Feedback
Shift
Regis
ters
�Loadable
Shift
Regis
ter
with I
nitia
lization
Mem
ory
�M
em
ory
Conta
inin
g T
est
Vect
ors
�FSM
1/28
/200
112
5
Testb
ench
Re
spo
nse
An
aly
ze
rs
�Com
pariso
n t
o M
em
ory
Conta
inin
g
Resp
onse
Vect
ors
�Lin
ear
Feedback
Shift
Regis
ter
�Com
pariso
n t
o B
ehavio
ral Verilo
g M
odel
Resp
onse
�FSM
1/28
/200
112
6
Re
fere
nc
es
1.
IEEE, 1364-1
995 I
EEE S
tandar
d D
esc
ription L
anguage
Base
d o
n t
he V
erilo
g(T
M)
Hard
ware
Desc
ription L
anguage.
2.
Syn
opsy
s, F
PG
A C
om
pile
r II
/FPG
A E
xpre
ss:
Verilo
g H
DL
Refe
rence
Manual, V
ers
ion 1
999.0
5, M
ay
1999.
3.
Thom
as,
D. E., a
nd P
. R. M
oorb
y,The V
erilo
g H
ard
ware
D
esc
ription L
anguage,4th
Ed., K
luw
er
Aca
dem
ic
Publis
hers
, 1998.
4.
Sm
ith, D
. R., a
nd P
. D
. Fra
nzo
n, Verilo
g S
tyle
s fo
r Synth
esi
s of
Dig
ital Syst
em
s, P
rentice
Hall,
2000.
5.
Cile
tti, M
ichael D
., M
odelin
g, Synth
esi
s, a
nd R
apid
Pro
toty
pin
g, Pre
ntice
Hall,
1999.
6.
Paln
itka
r, S
am
ir, Verilo
g H
DL:
A G
uid
e t
o D
esi
gn a
nd
Synth
esi
s, S
unso
ft P
ress
, 1996.
