# Verilog HDL

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Verilog HDL. HDLs. Hardware Description Languages Widely used in logic design Verilog and VHDL Describe hardware using code Document logic functions Simulate logic before building Synthesize code into gates and layout Requires a library of standard cells. Module name. Module ports. - PowerPoint PPT Presentation

### Text of Verilog HDL

• Verilog HDL

• HDLsHardware Description LanguagesWidely used in logic designVerilog and VHDL

Describe hardware using codeDocument logic functionsSimulate logic before buildingSynthesize code into gates and layoutRequires a library of standard cells

• Taste of Verilogmodule Add_half ( sum, c_out, a, b ); inputa, b;outputsum, c_out;wire c_out_bar;

xor (sum, a, b);nand (c_out_bar, a, b);not (c_out, c_out_bar);endmodulec_outabsumc_out_bar

• Behavioral Descriptionmodule Add_half ( sum, c_out, a, b ); inputa, b;outputsum, c_out;reg sum, c_out;always @ ( a or b ) beginsum = a ^ b;// Exclusive orc_out = a & b;// And endendmodule

• Example of Flip-flopmodule Flip_flop ( q, data_in, clk, rst );input data_in, clk, rst;output q;reg q;always @ ( posedge clk ) beginif ( rst == 1) q = 0;else q = data_in; endendmodule

• Gate Delayand (yout, x1, x2);// default, zero gate delayand #3 (yout, x1, x2);// 3 units delay for all transitionsand #(2,3) G1(yout, x1, x2); // rising, falling delayand #(2,3) G1(yout, x1, x2), G2(yout2, x3, x4);// Multiple instancesa_buffer #(3,5,2) (yout, x); // UDP, rise, fall, turnoffbufif1 #(3:4:5, 6:7:9, 5:7:8) (yout, xin, enable);// min:typ:max / rise, fall, turnoffSimulators simulate with only one of min, typ and max delay values Selection is made through compiler directives or user interfacesDefault delay is typ delay

• Time ScalesTime scale directive: timescale / time_unit -> physical unit of measure, time scale of delay time_precision -> time resolution/minimum step size during simulation time_unit time_precision

Unit/precisionDelay specificationSimulator time step Delay value in simulation1ns / 100ps#40.1ns4.0ns100ns / ns#41ns400ns10ns / 100ps#4.6290.1ns46.3ns

• Net Delay wire #2 y_tran;and #3 (y_tran, x1, x2);buf #1 (buf_out, y_tran);and #3 (y_inertial, x1, x2); x1x2y_trany_inertialbuf_outx1x2y_inertialy_tranbuf_out

• Structural vs. Behavioral Descriptionsmodule my_module(); assign ; // continuous assignment and (); // instantiation of primitive adder_16 M(); // instantiation of module

always @() begin end initial begin endendmodule Structural, no orderBehavior, in order in each procedure

• Behavioral Statementsinitial | alwayssingle_statement; | begin block_of_statements;endinitialActivated from tsim = 0Executed onceInitialize a simulation

alwaysActivated from tsim = 0Executed cyclicallyContinue till simulation terminates

• Example of Behavioral Statementmodule clock1 ( clk );parameter half_cycle = 50;parameter max_time = 1000;output clk;reg clk;initial clk = 0;always begin#half_cycle clk = ~clk; endinitial #max_time \$finish;endmoduleclktsim50100150200

• AssignmentContinuous assignmentValues are assigned to net variables due to some input variable changesassign =

Procedural assignmentValues are assigned to register variables when certain statement is executed in a behavioral descriptionProcedural assignment, =Procedural continuous assignment, assign = [deassign] Non-blocking assignment,

• Procedural Continuous AssignmentContinuous assignment establishes static binding for net variables

Procedural continuous assignment (PCA) establishes dynamic binding for variablesassign deassign for register variables only

• assign deassign PCABinding takes effect when PCA statement is executed

Can be overridden by another PCA statement

deassign is optional

assign takes control, deassign release control

module flop ( q, qbar, preset, clear, clock, data );assign qbar = ~q;initial q = 0;always @ ( negedge clk )q = data;always @ ( clear or preset )begin if ( !preset ) assign q = 1; else if ( !clear ) assign q = 0; else deassign q;endendmodule

• Example of assign module mux4_PCA(a, b, c, d, select, y_out); input a, b, c, d; input [1:0] select; output y_out; reg y_out;

always @(select) begin if (select == 0) assign y_out=a; else if (select == 1) assign y_out=b; else if (select == 2) assign y_out=c; else if (select == 3) assign y_out=d; else assign y_out=1bx; end

endmoduley_out changes with a;

• Alternative module mux4_PCA(a, b, c, d, select, y_out); input a, b, c, d; input [1:0] select; output y_out; reg y_out;

always @(select or a or b or c or d) begin if (select == 0) y_out=a; else if (select == 1) y_out=b; else if (select == 2) y_out=c; else if (select == 3) y_out=d; else y_out=1bx; end

endmoduleValue of a is assigned to y_out at this time

• Blocking and Non-blocking Assignmentinitial begina = 1;b = 0;a = b; // a = 0;b = a; // b = 0; end initial begina = 1;b = 0;a
• Delay Control Operator (#)initialbegin#0in1 = 0; in2 = 1;#10 in3 = 1;#40 in4 = 0; in5 = 1;#60 in3 = 0;end

• Event Control Operator (@)@ ( eventA or eventB ) begin @ ( eventC ) begin endendEvent -> identifier or expression

When @ is reachedActivity flow is suspendedThe event is monitoredOther processes keep going

posedge: 0->1, 0->x, x->1negedge: 1->0, 1->x, x->0

• The wait Constructmodule modA ();always begin wait ( enable ) ra = rb; endendmoduleActivity flow is suspended if expression is false

It resumes when the expression is true Other processes keep going

• Intra-assignment Delay: Blocking Assignment// B = 0 at time 0// B = 1 at time 4#5 A = B; // A = 1C = D;A = #5 B; // A = 0C = D;A = @(enable) B;C = D;A = @(named_event) B;C= D;If timing control operator(#,@) on LHSBlocking delayRHS evaluated at (#,@)Assignment at (#,@)

If timing control operator(#,@) on RHSIntra-assignment delayRHS evaluated immediatelyAssignment at (#,@)

• Indeterminate Assignmentmodule multi_assign();reg a, b, c, d;initial begin #5 a = 1; b = 0; endalways @ ( posedge a ) begin c = a; endalways @ ( posedge a ) begin c = b; endalways @ ( posedge a ) begin d = b; endalways @ ( posedge a ) begin d = a; endendmodule

Multiple assignments are made to same variable in different behaviors

Value depends on code order or vendor specifications

Similar to race-conditions in hardware

• Activity Flow Control ( if else )if ( A == B ) P = d;if ( B < C );if ( a >= b ) begin end

if ( A < B ) P = d;else P = k;

if ( A > B ) P = d;else if ( A < B ) P = k;else P = Q;Syntax: if ( expression ) statement [ else statement ]

Value of expression 0, x or z => falseNon-zero number => true

• Conditional Operator ( ? : )always @ ( posedge clock ) yout = ( sel ) ? a + b : a b;Conditional operator can be applied in either continuous assignments or behavioral descriptions

• The case Statementmodule mux4 ( a, b, c, d, select, yout ); input a, b, c, d; input [1:0] select; output yout; reg yout; always @( a or b or c or d or select ) begin case ( select ) 0: yout = a; 1: yout = b; 2: yout = c; 3: yout = d; default yout = 1`bx; endcaseendmoduleCase items are examined in order

Exact match between case expression and case item

casez treats z as dont cares

casex treats both x and z as dont cares

• The for Loopreg [15:0] regA;integer k;for ( k = 4; k; k = k 1 )begin regA [ k+10 ] = 0; regA [ k+2 ] = 1;endLoop variables have to be either integer or reg

• The while Loopbegin cnt1s reg [7:0] tmp; cnt = 0; tmp = regA; while ( tmp ) begin cnt = cnt + tmp; tmp = tmp >> 1; endendmodule sth ( externalSig ); input externalSig;

always begin while ( externalSig ); endendmoduleLoop activities suspend external activities

• The disable Statementbegin k = 0; for ( k = 0; k
• The forever Loopparameter half_cycle = 50;

initial begin : clock_loop clock = 0; forever begin#half_cycle clock = 1;#half_cycle clock = 0; end end

initial #350 disable clock_loop;

• Task module bit_counter (data, count); input [7:0] data; output [3:0] count; reg [3:0] count;

always @(data) t(data, count);

task t; input [7:0] a; output [3:0] c; reg [3:0] c; reg [7:0] tmp; begin c = 0; tmp = a; while (tmp) begin c = c + tmp; tmp = tmp >> 1; end end endtaskendmodule

• Functionmodule word_aligner (w_in, w_out); input [7:0] w_in; output [7:0] w_out;

assign w_out = align (w_in);

function [7:0] align; input [7:0] word; begin align = word; if (align != 0) while (align == 0) align = align

• Switch Level NAND Gatemodule nand_2 ( Y, A, B );output Y;input A, B;supply0 GND;supply1 PWR;wire w;

pmos ( Y, PWR, A );pmos ( Y, PWR, B );nmos ( Y, w, A );nmos ( w, GND, B );endmoduleYVddAABB

• Assign Drive Strengthsnand ( pull1, strong0 ) G1( Y, A, B );wire ( pull0, weak1 ) A_wire = net1 || net2;assign ( pull1, weak0 ) A_net = reg_b;Drive strength is specified through an unordered pair one value from { supply0, strong0, pull0, weak0 , highz0 } the other from { supply1, strong1, pull1, weak1, highz1 }

Only scalar nets may receive strength assignment

• Latch Resulted from Unspecified Input Statemodule myMux( y, selA, selB, a, b );input selA, selB, a, b;output y;reg y;

always @ ( selA or selB

Recommended ##### Lab 1: Introduction to Verilog HDL and the Vivado 3Supplement: Verilog An introduction to Verilog HDL
Documents ##### INTRODUCTION TO VERILOG HDL - fke.utm.my Lآ­2: VERILOG HDL 2012/2013-1 â€¢ Verilog describes a digital
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