Using Atrenta Spyglass in GUI mode:

For all the documentation of the spyglass, do “spydocviewer &” in the command prompt of the unix machine.

Invoke the tool by:spyglass &

There are three steps to be performed:1. Design Setup: Design files, sgdc (spyglass design constraint file), HDL Libraries

and Tech libraries are added.2. Goal Set up and Run: Specify the goals, the severity level of tool run (initial rtl,

detailed rtl and rtl handoff levels) and run the goals.3. Analyze the results: The results of the tool run on the set up goals are analyzed

and reports are generated.

1. Design Setup:

a. Adding files:

Click Add File(s) to add design files. If .sgdc files are present, they can be added here. .sgdc files are the constraint files that have clocks, resets, auto-case analysis information. They can be automatically generated in latter stages. For now, you can add just design files ie .v files. Please make sure that you don’t add unnecessary verilog files, as they may affect the final results. You can omit ram files as they are out of the design.

Unnecessary files can be removed by selecting the file and then “Delete”. The .prj, .sgdc and unnecessary files are removed from above snapshot as shown below.

b. Run Design Read.

After adding the necessary design files, go to Run Design Read tab and click Run Design Read button. This will run very basic rules to check if all the design modules are present, hierarchy etc.

After the Run Design Read button is executed, the tool will ask for the project name.

After Run Design Read is executed, messages can be seen in the below session log. There are three type of messages that will be generated in session log name Info, Warning and Error messages.

2. Goal Set up and Run:

If there are no issues with Run Design Read we can proceed to Goal Setup and Run. We can three severity levels in Goal setup and run namely initial rtl, detailed rtl and rtl hand-off, with rtl handoff severity level being run with more stringent rules.

Select Central Set up for Designing clocks, resets and autocaseanalysis constraint files. Here Blackboxes can be found out if present. If they are present they can be resolved here. Sanity Checks can be performed on the generated .sgdc constraint files.

To Resolve Blackboxes select Blackboxes and then click next on the bottom left of the window.

If there are no blackboxes in the design the following will be displayed

Click Next in the bottom left to go to the next goal

Design Clocks set up will look as below

On the bottom left, as we don’t have any sgdc files, select No. And we also don’t have the sdc files to import constraints. So select No. Because we want to identify all the potential clocks in the design, selest Yes for the third Question. And then click Next.

Select Yes for “Show Clock Trees and finalize clock definition interactively”

The above run will create an sgdc file called cdc_setup_clocks.sgdc in <project>_files directory. It will display the potential clocks in the design as shown below. Check the clocks that need to be included and deleted the ones which are not important. It is very important to also include the missing important clocks in case the spyglass didn’t identify them. We can omit test clocks which are typically not used in the design.

The following message will be displayed after successful generation of clocks and then click Next in the bottom left window. The above run will create an sgdc file called cdc_setup_clocks.sgdc in <project>_files directory.

Select Yes for Verify clock setup. This will run a Sanity Check on the generated clocks .sgdc file.

Click Next to reach the step of creating resets sgdc file. Then click Yes for Edit and complete reset constraints file.

Spyglass will identify the potential resets in the Design. Add or Delete resets if tool generates incomplete set of resets.

After the above 3 sgdc files have been generated, go back to Design Setup and enable cdc_setup.clocks.sgdc and autoresets.sgdc files for them to have affect on the lint, cdc checks etc. You can use auto_case_analysis.sgdc file if required. You can set the values for the run in this constraint file.

The final step of “Central Set up ” would be to run a sanity check on sgdc file. Click Yes.

If there are no issues with set up, click Finish on the bottom left to exit the central set up

Now, click Select Goals for setup/run.

Select one of the initial_rtl or detailed_rtl or rtl_handoff options and then select all the goals in lint. That is, connectivity, simulation, synthesis and structure. Select Run in Group Mode on top of the window as shown below. Normally Detailed RTL option is selected. Here, for demo purpose we have used the initial_rtl option. We can use rtl_handoff option for a much stringent rule check.

Click Run Selected Goals and then click OK to run the selected goals as shown below. The messages will be shown below in the session log as the tool runs the goals.

If there are any warning, errors, they will be shown in the session log below.

Click Analyze Results

Expand Warning/Error/Info in Message tree and double click on the message. The relevant HDL file will be displayed in the source window.

Click Incremental Schematic on the left to open up the schematic window. The schematic relevant to the warning/error message will be displayed.

Select Goal Setup and Run to select different goals. Now, lets select clock domain crossing. Cdc_prep, cdc_verif, cdc_exhaustive check more rules incrementally. Cdc_exhaustive checks the design against more stringent cdc rules. Detailed_rtl/cdc_verif/cdc_verif should be adequate enough to run the checks on IPs.

Run the Selected Goal(s) after selecting the cdc option and then go to Analyze Results.

You can view HDL by expanding warning/error message in message tree as demonstrated with lint check. If you click the incremental schematic on the left of the message tree the relevant incremental schematic looks something like below. We can trace signals from this schematic.

To generate reports click on the reports on the top-right of the message tree. Usually the sign-off report contains the comprehensive tool run information and includes all the warnings/errors or info messages.

Save the project once in a while to save the project information. Likewise, you can select other goals from goals tab to check the design against various rules.