Uploads Notes Btech 5sem Cse VHDL Notes4X

Subprograms and Overloading

ByMr. Gaurav Verma

ECE Dept.NIEC

1ETEC-301- DCS-II BY: GAURAV VERMA

2ETEC-301- DCS-II BY: GAURAV

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Subprograms Similar to subprograms found in other languages

Allow repeatedly used code to be referenced multiple times without rewriting

Break down large blocks of code into small, more manageable partsparts

VHDL provides functions and procedures


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Subprograms (contd) Contain sequential statements similar to processes

May declare local variables, constants

Executed when called from a sequential statement.

Local Variables are re-initialized every time a subprogram is called. Local Variables are re-initialized every time a subprogram is called.

Parameters of calling routine are known as actuals, while the parameters of the declared subprogram are known as formals.

Up level referencing to higher level variables and signals is allowed.

Recursive calls by functions and procedures are allowed

Attributes of signals cannot be accessed within subprograms


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Produce a single return value Called by expressions Cannot modify the parameters passed to them Require a RETURN statement

FUNCTION add_bits (a, b : IN BIT) RETURN BIT IS

FUNCTION add_bits2 (a, b : IN BIT) RETURN BIT ISVARIABLE result : BIT; -- variable is local to function

BEGINresult := (a XOR b);RETURN result; -- the two functions are equivalent

END add_bits2;

FUNCTION add_bits (a, b : IN BIT) RETURN BIT ISBEGIN -- functions cannot return multiple values

RETURN (a XOR b);END add_bits;


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x 6ETEC-301- DCS-II BY: GAURAV VERMA

Functions


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Example of a Function


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Example of a Function (cont)


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ARCHITECTURE behavior OF adder ISBEGIN

PROCESS (enable, x, y)BEGINIF (enable = '1') THENresult


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Procedures (cont)


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Example of a Procedure


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Another Example of a Procedure


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Summary on Sequential Statements


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May produce multiple output values Are invoked by statements May modify the parameters

PROCEDURE add_bits3 (SIGNAL a, b, en : IN BIT;PROCEDURE add_bits3 (SIGNAL a, b, en : IN BIT;SIGNAL temp_result, temp_carry : OUT BIT) IS

BEGIN -- procedures can return multiple valuestemp_result

With parameter passing, it is possible to further simplify the architecture

ARCHITECTURE behavior OF adder ISBEGIN

PROCESS (enable, x, y)BEGINadd_bits3(x, y, enable,

result, carry);result, carry);END PROCESS;

END behavior;

PROCEDURE add_bits3

(SIGNAL a, b, en : IN BIT;SIGNAL temp_result,

temp_carry : OUT BIT)

The parameters must be compatible in terms of data flow and data type


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Signal Resolution and Buses

OR

Execution phase Signal update phase

Transaction queue

Bus Resolution Function

AND

Resolvedsignal


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Bus ResolutionSmoke Generator

VHDL does not allow multiple concurrent signal assignments to the same signal Multiple sequential signal assignments are allowedLIBRARY attlib; USE attlib.att_mvl.ALL;-- this code will generate an errorENTITY bus ISENTITY bus IS

PORT (a, b, c : IN MVL; z : OUT MVL);END bus;

ARCHITECTURE smoke_generator OF bus ISSIGNAL circuit_node : MVL;

BEGINcircuit_node

Bus Resolution Functions Are used to determine the assigned value when

there are multiple signal drivers to the same signal

FUNCTION wired_and (drivers : MVL_VECTOR) RETURN MVL ISVARIABLE accumulate : MVL := '1';

BEGINFOR i IN drivers'RANGE LOOPFOR i IN drivers'RANGE LOOPaccumulate := accumulate AND drivers(i);

END LOOP;RETURN accumulate;

END wired_and;

Bus resolution functions may be user defined or called from a package


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Bus ResolutionSmoke Generator Fixed

A signal which has a bus resolution function associated with it may have multiple drivers

LIBRARY attlib; USE attlib.att_mvl.ALL;USE WORK.bus_resolution.ALL;

ENTITY bus ISPORT (a, b, c : IN MVL; z : OUT MVL);PORT (a, b, c : IN MVL; z : OUT MVL);

END bus;

ARCHITECTURE fixed OF bus ISSIGNAL circuit_node : wired_and MVL;

BEGINcircuit_node

Null Transactions How can a driver be disconnected (i.e. not influence the output at

all)? Use the null waveform element

Examplebus_out

Exists outside of a process but in an architecture

The process is itself a concurrent statement all processes The process is itself a concurrent statement all processes scheduled to run concurrently

Concurrent signal assignment is a short hand form for a single statement process -- equivalent to process containing one statement, sensitive to changes on the right hand side.

Used frequently in DATAFLOW style descriptions27

ETEC-301- DCS-II BY: GAURAV VERMA

The Process


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Overloading Overloading refers to using the same procedure(or function) name to define two or more proceduresthat operate on different types or numberof parameters.

procedure incr (a :in integer; n :in integer);procedure incr (a :in integer; n :in integer);procedure incr (a :in bit_vector; n :in integer);procedure incr (a :in integer);

VHDL also permits overloading of operator symbolslike +, -, * and so on.


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Overloading: examplefunction + (left,right : bit_vector)

return bit_vector isbegin

end function;

variable a, b, c: bit_vector(7 downto 0);

c = a + b;


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Concurrent Signal Assignment


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Concurrent AssignmentConcurrent AssignmentStatementsStatements

Concurrent AssignmentConcurrent AssignmentStatementsStatements


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Concurrent Signal Sensitivity Concurrent Statements are sensitive to all signals on

the input side

If a signal appears on both sides, the statement is sensitive to changes in its own output. sensitive to changes in its own output.

A

Conditional SignalStatement


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Example of Conditional SignalStatement


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Selected Signal Statement


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Example of Selected SignalAssignment


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Concurrent Procedure Call IN, OUT and INOUT parameter modes

Allows return of more than 1 value (unlike function call)

Considered a statement

Equivalent to a process containing the single procedure call followed by a wait on parameters of mode in or inout


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Example of ConcurrentProcedure Call


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Sequential vs. ConcurrentStatement in Simulation Cycle

VHDL is inherently a concurrent language All VHDL processes execute concurrently Concurrent signal assignment statements are actually

oneline processesoneline processes VHDL statements execute sequentially within a process Concurrent processes with sequential execution within

a process offers maximum flexibility Supports various levels of abstraction Supports modeling of concurrent and sequential events

as observed in real systems40

ETEC-301- DCS-II BY: GAURAV VERMA


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Blocks Blocks are concurrent statements and provide a

mechanism to partition an architecture description

Items declared in declarative region of block are visible only inside the block, e.g. :visible only inside the block, e.g. : signals, subprograms

Blocks may be nested to define a hierarchical partitioning of the architectural description

Blocks may contain Guards for disabling drives.


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VLSI, Ohio University, Prof. Starzyk Professor K.J. Hintz. Professor K.J. Hintz. California State University Northridge


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