Unit II 16 Bit Microprocessor Architecture 9

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UNIT II

16 BIT MICROPROCESSOR ARCHITECTURE

Contents1.8086-Internal Architecture 2.Memory segmentation 3.Timing diagram 4.Interrupts-8086 CPU Hardware design 5.Maximum mode CPU Module 6.Minimum mode CPU module _______________________________________________________________

HISTORY OF 8086 Microprocessor The 8086 is a 16-bit microprocessor chip designed by Intel and introduced on the market in 1978, which gave rise to the x86 architecture. Intel 8088, released in 1979, was essentially the same chip, but with an external 8-bit data bus (allowing the use of cheaper and fewer supporting logic chips), and is notable as the processor used in the original IBM PC. The first multi-chip 16-bit microprocessor was the National Semiconductor IMP-16, introduced in early 1973. An 8-bit version of the chipset was introduced in 1974 as the IMP-8. During the same year, National introduced the first 16-bit single-chip microprocessor, the National Semiconductor PACE, which was later followed by an NMOS version, the INS8900. Intel followed a different path, having no minicomputers to emulate, and instead "upsized" their 8080 design into the 16-bit Intel 8086, the first member of the x86 family which powers most modern PC type computers.

Intel introduced the 8086 as a cost effective way of porting software from the 8080 lines, and succeeded in winning much business on that premise.

The 8088, a version of the 8086 that used an external 8-bit data bus, was the microprocessor in the first IBM PC, the model 5150. Following up their 8086 and 8088, Intel released the 80186, 80286 and, in 1985, the 32-bit 80386, cementing their PC market dominance with the processor family's backwards compatibility. The integrated microprocessor memory management unit (MMU) was developed by Childs et al. of Intel, and awarded US patent number 4,442,484.

1.8086-Internal ArchitectureCLOCK, POWER SUPPLY AND INSTRUCTION CYCLE Fig 8 shows the 8086 pin diagram. Vcc is on pin 40 and ground on pins 1 and 20. 8086 requires +5v supply. Clock input labeled CLK is on pin 19. An 8086 requires a clock signal from some external, crystal- controlled clock generator to synchronize internal operations in the processor. Different versions of the 8086 have maximum clock frequencies ranging from MHz to 10 MHz.

Pins 2 through 16 and pins 35 through 39 are used for the address bus. Pins 35 through 38 are used by multiplexing to provide information or status about the MPU. The status signals are labeled S3, S4, S5 and S6 as shown. The data bus lines AD0 through AD15 are used at the start of the machine cycle to send out addresses, and later in the machine cycle they are used to send or receive data. The 8086 sends out a signal called address latch enable or ALE on pin 25 to let external circuitry know that an address is on the data bus. The upper 4 bits of an address are sent on the lines labeled A16/ S 3 through A19/ S 6. Some of the control bus lines on a microprocessor usually have mnemonics such as RD, WR and M/ IO. Pin 32 of the 8086 is labeled RD.

A tri-state active-low output signal on pin 32 indicates that the 8086 is reading data from memory or from a port. Pin 29 has a label WR next to it. However, pin 29 also has a label LOCK next to it, because this pin has two functions. The function of this pin and the functions of the pins between 24 and 31 depend on the mode in which the 8086 is operating. The operating mode of the 8086 is determined by the logic level applied to the MN/ MX input on pin 33. If pin 33 is asserted high, then the 8086 will function in minimummode, and pins 24 through 31 will have functions shown in parentheses next to the pins in fig. 8. If the MN / MX pin is asserted low, then the 8086 is in maximum mode. In this mode pins 24 through 31 will have the functions described by the mnemonics next to the pins in fig. 8. A tri-state active-low output signal on pin 29 indicates that MPU has put valid and stable data on the data bus. Pin 28 will function as M / IO. The 8086 will assert this signal high if it is reading from or writing to a memory location, and it will assert a signal low if it is reading from or writing to a port. In the maximum mode the control bus signals (S0, S1, S2 ) are sent out in encoded form on pins 26,27 and 28. An external bus controller device decodes these signals to produce the control bus signals required for a system, which has two or more microprocessors sharing the same buses. If pin 21, the RESET input is made high, the 8086 will, no matter what it is doing, reset its DS, SS, ES, IP and flag registers to all 0s. It will set its CS register to FF.

When the RESET signal is removed from pin 21, the 8086 will then fetch its next instruction from physical address (FFFF0H). This address is produced in the 8086 Bus Interface unit (BIU) by shifting the FFFFH in the CS register 4 bits left by adding the 0000H in the instruction pointer to it. The first instruction that has to be executed after a reset is put at this address FFF0H. 8086 has two interrupt inputs, non-maskable interrupt (NMI) input on pin 17 and the interrupt (INTR) input on pin 18. An active-high on any one of these pins will cause the 8086 to stop execution of its current program and go execute a specified procedure. At the end of the procedure it can return to executing the interrupted program. The NMI cannot be ignored, or masked, by the MPU. The INTR (interrupt request) is maskable and can be made to be ignored by the MPU through software control.

A tri-state active-low output signal on pin 26 DEN (data enable) determines whether the data buffer is enabled or disabled. A tri-state output signal on pin 27 DT / R(data transmit receive) is used to control the direction of data flow. A logic level 1 indicates data bits are being transmitted from the MPU. A logic level 0 indicates that data bits are being received into the MPU. All microprocessors use an oscillator to generate a master frequency clock to synchronize or time operations. For the 8086 microprocessor the oscillator frequency, or clock frequency is typically 5 MHz. The period of one clock cycle is then equal to. T = 1/F = 1/5 x 106 Hz = 0.2 x 10-6 sec. = 200 n sec The 8086 operates in time periods called bus cycles. Each bus cycle requires 4

clock cycles to complete. Therefore, the bus cycle is completed very 800 ns. A typical bus cycle is shown in fig 9. One cycle of this is referred to as a state. A state is measured from the 50 percent point on the falling edge of one clock pulse to 50 percent point on the falling edge of the next clock pulse- T1 in the figure is a state. Each basic bus operation such as reading a byte from memory or writing a word to a port requires some number of states. The group of states required for a basic bus operation is called a machine cycle. The total time it takes the 8086 to fetch and execute an instruction is called an instruction cycle. An instruction cycle consists of one or more machine cycles. To summarize, an instruction cycle is made up of machine cycles, and a machine cycle is made up of states. Two major bus cycles are the read bus cycle and the write bus cycle. The read bus cycle is activated when the microprocessor is reading information from the memory or an I/O device. During the read bus cycle, there are normally four clock cycles T1 ,T2, T3 and T4. However, if the device outputting data to the MPU needs more time to send the data, a wait state (Tw) is initiated by placing extra clock cycles (Tws) between cycles T3 and T4. Fetch-Execute cycle The microprocessor has two primary functions. Fetch and execute. First it must fetch or read the program instruction or data.

This can take one or more bus cycles. Once it has fetched the necessary program instructions and data through the BIU, the microprocessors next step is to execute the instructions. The EU receives the instruction from the instruction queue and executes it. Some instructions may take 2 clock cycles to execute, where as others may take as many as 100 clock cycles to execute. In older microprocessors this left the bus idle while the MPU was executing a long instruction, as shown in the fig. 10. however, since the 8086 MPU is broken up into two functional units,the BIU and EU, it avoids much of the idle time required by older microprocessors. It does this by having the BIU pre fetch instructions and place them into the instruction queue and data registers while the EU is executing the program instructions. Therefore,while the bus is busy during a read cycle, the EU can be executing the previous instructions. When the bus is busy during a write cycle, the EU can be executing another instruction. This greatly increases the effective speed of the entire system.

2.Memory SegmentationMemories of 8086 Program, data and stack memories occupy the same memory space. The total addressable memory size is 1MB KB. As the most

of the processor instructions use 16-bit pointers the processor can effectively address only 64 KB of memory.

To access memory outside of 64 KB the CPU uses special

segment registers to specify where the code, stack and data 64 KB segments are positioned within 1 MB of memory (see the "Registers" section below).

16-bit pointers and data are stored as: address: low-order byte address+1: high-order byte 32-bit addresses are stored in "segment:offset" format as: address: low-order byte of segment address+1: high-order byte of segment address+2: low-order byte of offset address+3: high-order byte of offset Physical memory address pointed by segment:offset pair is calculated as: address = ( * 16) +

Program memory program can be located anywhere in memory. Jump and call instructions can be used for short jumps within

currently selected 64 KB code segment, as well as for far jumps anywhere with