UNIT II

16 BIT MICROPROCESSOR ARCHITECTURE

Contents1.8086-Internal Architecture 2.Memory segmentation 3.Timing diagram 4.Interrupts-8086 CPU Hardware design5.Maximum mode CPU Module 6.Minimum mode CPU module_______________________________________________________________

HISTORY OF 8086 Microprocessor

The 8086 is a 16-bit microprocessor chip designed by Intel and

introduced on the market in 1978, which gave rise to the x86

architecture.

Intel 8088, released in 1979, was essentially the same chip, but

with an external 8-bit data bus (allowing the use of cheaper and

fewer supporting logic chips), and is notable as the processor

used in the original IBM PC.

The first multi-chip 16-bit microprocessor was the National

Semiconductor IMP-16, introduced in early 1973.

An 8-bit version of the chipset was introduced in 1974 as the

IMP-8. During the same year, National introduced the first 16-bit

single-chip microprocessor, the National Semiconductor PACE,

which was later followed by an NMOS version, the INS8900.

Intel followed a different path, having no minicomputers to

emulate, and instead "upsized" their 8080 design into the 16-bit

Intel 8086, the first member of the x86 family which powers most

modern PC type computers.

Intel introduced the 8086 as a cost effective way of porting

software from the 8080 lines, and succeeded in winning much

business on that premise.

The 8088, a version of the 8086 that used an external 8-bit data

bus, was the microprocessor in the first IBM PC, the model 5150.

Following up their 8086 and 8088, Intel released the 80186,

80286 and, in 1985, the 32-bit 80386, cementing their PC market

dominance with the processor family's backwards compatibility.

The integrated microprocessor memory management unit (MMU)

was developed by Childs et al. of Intel, and awarded US patent

number 4,442,484.

1.8086-Internal Architecture

CLOCK, POWER SUPPLY AND INSTRUCTION CYCLE

Fig 8 shows the 8086 pin diagram. Vcc is on pin 40 and ground on pins 1 and 20.

8086 requires +5v supply. Clock input labeled CLK is on pin 19.

An 8086 requires a clock signal from some external, crystal- controlled clock

generator to synchronize internal operations in the processor.

Different versions of the 8086 have maximum clock frequencies ranging from

MHz to 10 MHz.

Pins 2 through 16 and pins 35 through 39 are used for the address bus. Pins 35

through 38 are used by multiplexing to provide information or status about the

MPU.

The status signals are labeled S3, S4, S5 and S6 as shown. The data bus lines

AD0 through AD15 are used at the start of the machine cycle to send out

addresses, and later in the machine cycle they are used to send or receive data.

The 8086 sends out a signal called address latch enable or ALE on pin 25 to let

external circuitry know that an address is on the data bus.

The upper 4 bits of an address are sent on the lines labeled A16/ S 3 through

A19/ S 6.

Some of the control bus lines on a microprocessor usually have mnemonics such

as RD, WR and M/ IO. Pin 32 of the 8086 is labeled RD.

A tri-state active-low output signal on pin 32 indicates that the 8086 is reading

data from memory or from a port. Pin 29 has a label WR next to it. However, pin

29 also has a label LOCK next to it, because this pin has two functions.

The function of this pin and the functions of the pins between 24 and

31 depend on the mode in which the 8086 is operating.

The operating mode of the 8086 is determined by the logic level applied to the

MN/ MX input on pin 33. If pin 33 is asserted high, then the 8086 will function in

minimummode, and pins 24 through 31 will have functions shown in parentheses

next to the pins in fig. 8.

If the MN / MX pin is asserted low, then the 8086 is in maximum mode. In this

mode pins 24 through 31 will have the functions described by the mnemonics

next to the pins in fig. 8.

A tri-state active-low output signal on pin 29 indicates that MPU has put valid and

stable data on the data bus. Pin 28 will function as M / IO.

The 8086 will assert this signal high if it is reading from or writing to a memory

location, and it will assert a signal low if it is reading from or writing to a port. In

the maximum mode the control bus signals (S0, S1, S2 ) are sent out in encoded

form on pins 26,27 and 28.

An external bus controller device decodes these signals to produce the control bus

signals required for a system, which has two or more microprocessors sharing the

same buses.

If pin 21, the RESET input is made high, the 8086 will, no matter what it is doing,

reset its DS, SS, ES, IP and flag registers to all 0’s. It will set its CS register to FF.

When the RESET signal is removed from pin 21, the 8086 will then fetch its next

instruction from physical address (FFFF0H). This address is produced in the 8086

Bus Interface unit (BIU) by shifting the FFFFH in the CS register 4 bits left by

adding the 0000H in the instruction pointer to it. The first instruction that has to

be executed after a reset is put at this address FFF0H.

8086 has two interrupt inputs, non-maskable interrupt (NMI) input on pin 17 and

the interrupt (INTR) input on pin 18.

An active-high on any one of these pins will cause the 8086 to stop execution of

its current program and go execute a specified procedure.

At the end of the procedure it can return to executing the interrupted program.

The NMI cannot be ignored, or masked, by the MPU. The INTR (interrupt

request) is maskable and can be made to be ignored by the MPU through software

control.

A tri-state active-low output signal on pin 26 DEN (data enable) determines

whether the data buffer is enabled or disabled. A tri-state output signal on pin 27

DT / R(data transmit receive) is used to control the direction of data flow.

A logic level 1 indicates data bits are being transmitted from the MPU. A logic

level 0 indicates that data bits are being received into the MPU.

All microprocessors use an oscillator to generate a master frequency clock to

synchronize or time operations. For the 8086 microprocessor the oscillator

frequency, or clock frequency is typically 5 MHz. The period of one clock cycle

is then equal to.

T = 1/F

= 1/5 x 106 Hz

= 0.2 x 10-6 sec.

= 200 n sec

The 8086 operates in time periods called bus cycles. Each bus cycle requires 4

clock cycles to complete. Therefore, the bus cycle is completed very 800 ns. A

typical bus cycle is shown in fig 9.

One cycle of this is referred to as a state. A state is measured from the 50 percent

point on the falling edge of one clock pulse to 50 percent point on the falling edge

of the next clock pulse- T1 in the figure is a state.

Each basic bus operation such as reading a byte from memory or writing a word

to a port requires some number of states. The group of states required for a basic

bus operation is called a machine cycle.

The total time it takes the 8086 to fetch and execute an instruction is called an

instruction cycle.

An instruction cycle consists of one or more machine cycles. To summarize, an

instruction cycle is made up of machine cycles, and a machine cycle is made up of

states.

Two major bus cycles are the read bus cycle and the write bus cycle. The read bus

cycle is activated when the microprocessor is reading information from the

memory or an

I/O device. During the read bus cycle, there are normally four clock cycles

T1 ,T2, T3 and T4.

However, if the device outputting data to the MPU needs more time to send the

data, a wait state (Tw) is initiated by placing extra clock cycles (Tw’s) between

cycles T3 and T4.

Fetch-Execute cycle

The microprocessor has two primary functions. Fetch and execute. First it must

fetch or read the program instruction or data.

This can take one or more bus cycles. Once it has fetched the necessary program

instructions and data through the BIU, the microprocessor’s next step is to

execute the instructions.

The EU receives the instruction from the instruction queue and executes it. Some

instructions may take 2 clock cycles to execute, where as others may take as many

as 100 clock cycles to execute. In older microprocessors this left the bus idle

while the MPU was executing a long instruction, as shown in the fig. 10.

however, since the 8086 MPU is broken up into two functional units,the BIU and

EU, it avoids much of the idle time required by older microprocessors.

It does this by having the BIU pre fetch instructions and place them into the

instruction queue and data registers while the EU is executing the program

instructions.

Therefore,while the bus is busy during a read cycle, the EU can be executing the

previous instructions.

When the bus is busy during a write cycle, the EU can be executing another

instruction. This greatly increases the effective speed of the entire system.

2.Memory SegmentationMemories of 8086

Program, data and stack memories occupy the same memory

space.

The total addressable memory size is 1MB KB. As the most of

the processor instructions use 16-bit pointers the processor can

effectively address only 64 KB of memory.

To access memory outside of 64 KB the CPU uses special

segment registers to specify where the code, stack and data 64

KB segments are positioned within 1 MB of memory (see the

"Registers" section below).

16-bit pointers and data are stored as:

address: low-order byte

address+1: high-order byte

32-bit addresses are stored in "segment:offset" format as:

address: low-order byte of segment

address+1: high-order byte of segment

address+2: low-order byte of offset

address+3: high-order byte of offset

Physical memory address pointed by segment:offset pair is calculated

as:

address = (<segment> * 16) + <offset>

Program memory –

program can be located anywhere in memory.

Jump and call instructions can be used for short jumps within

currently selected 64 KB code segment, as well as for far jumps

anywhere within 1 MB of memory.

All conditional jump instructions can be used to jump within

approximately +127 - -127 bytes from current instruction.

Data memory –

• The processor can access data in any one out of 4 available

segments, which limits the size of accessible memory to 256 KB

(if all four segments point to different 64 KB blocks).

• Accessing data from the Data, Code, Stack or Extra segments

can be usually done by prefixing instructions with the DS:, CS:,

SS: or ES: (some registers and instructions by default may use

the ES or SS segments instead of DS segment).

• Word data can be located at odd or even byte boundaries.

• The processor uses two memory accesses to read 16-bit word

located at odd byte boundaries. Reading word data from even

byte boundaries requires only one memory access.

Stack memory can be placed anywhere in memory. The stack can be

located at odd memory addresses, but it is not recommended for

performance reasons (see "Data Memory" above).

Reserved locations:

0000h - 03FFh are reserved for interrupt vectors. Each interrupt

vector is a 32-bit pointer in format segment:offset.

FFFF0h - FFFFFh - after RESET the processor always starts

program execution at the FFFF0h address.

4.InterruptsThe processor has the following interrupts:

INTR is a maskable hardware interrupt. The interrupt can be

enabled/disabled using STI/CLI instructions or using more complicated

method of updating the FLAGS register with the help of the POPF

instruction. When an interrupt occurs, the processor stores FLAGS

register into stack, disables further interrupts, fetches from the bus

one byte representing interrupt type, and jumps to interrupt

processing routine address of which is stored in location 4 * <interrupt

type>. Interrupt processing routine should return with the IRET

instruction.

NMI is a non-maskable interrupt. Interrupt is processed in the same

way as the INTR interrupt. Interrupt type of the NMI is 2, i.e. the

address of the NMI processing routine is stored in location 0008h. This

interrupt has higher priority then the maskable interrupt.

Software interrupts can be caused by:

INT instruction - breakpoint interrupt. This is a type 3 interrupt.

INT <interrupt number> instruction - any one interrupt from

available 256 interrupts.

INTO instruction - interrupt on overflow

Single-step interrupt - generated if the TF flag is set. This is a

type 1 interrupt. When the CPU processes this interrupt it clears

TF flag before calling the interrupt processing routine.

Processor exceptions: divide error (type 0), unused opcode (type

6) and escape opcode (type 7).

Software interrupt processing is the same as for the hardware

interrupts.

I/O ports

65536 8-bit I/O ports. These ports can be also addressed as 32768 16-

bit I/O ports.

Registers

There are four different 64 KB segments for instructions, stack,

data and extra data. To specify where in 1 MB of processor memory

these 4 segments are located the processor uses four segment

registers:

Code segment (CS) is a 16-bit register containing address of 64

KB segment with processor instructions. The processor uses CS

segment for all accesses to instructions referenced by instruction

pointer (IP) register. CS register cannot be changed directly. The CS

register is automatically updated during far jump, far call and far

return instructions.

Stack segment (SS) is a 16-bit register containing address of

64KB segment with program stack. By default, the processor assumes

that all data referenced by the stack pointer (SP) and base pointer

(BP) registers is located in the stack segment. SS register can be

changed directly using POP instruction.

Data segment (DS) is a 16-bit register containing address of

64KB segment with program data. By default, the processor assumes

that all data referenced by general registers (AX, BX, CX, DX) and

index register (SI, DI) is located in the data segment. DS register can

be changed directly using POP and LDS instructions.

Extra segment (ES) is a 16-bit register containing address of

64KB segment, usually with program data. By default, the processor

assumes that the DI register references the ES segment in string

manipulation instructions. ES register can be changed directly using

POP and LES instructions.

It is possible to change default segments used by general and index

registers by prefixing instructions with a CS, SS, DS or ES prefix.

All general registers of the 8086 microprocessor can be used for

arithmetic and logic operations. The general registers are:

Accumulator register consists of 2 8-bit registers AL and AH, which

can be combined together and used as a 16-bit register AX. AL in this

case contains the low-order byte of the word, and AH contains the

high-order byte. Accumulator can be used for I/O operations and string

manipulation.

Base register consists of 2 8-bit registers BL and BH, which can be

combined together and used as a 16-bit register BX. BL in this case

contains the low-order byte of the word, and BH contains the high-

order byte. BX register usually contains a data pointer used for based,

based indexed or register indirect addressing.

Count register consists of 2 8-bit registers CL and CH, which can

be combined together and used as a 16-bit register CX. When

combined, CL register contains the low-order byte of the word, and CH

contains the high-order byte. Count register can be used as a counter

in string manipulation and shift/rotate instructions.

Data register consists of 2 8-bit registers DL and DH, which can be

combined together and used as a 16-bit register DX. When combined,

DL register contains the low-order byte of the word, and DH contains

the high-order byte. Data register can be used as a port number in I/O

operations. In integer 32-bit multiply and divide instruction the DX

register contains high-order word of the initial or resulting number.

The following registers are both general and index registers:

Stack Pointer (SP) is a 16-bit register pointing to program stack.

Base Pointer (BP) is a 16-bit register pointing to data in stack

segment. BP register is usually used for based, based indexed or

register indirect addressing.

Source Index (SI) is a 16-bit register. SI is used for indexed, based

indexed and register indirect addressing, as well as a source data

address in string manipulation instructions.

Destination Index (DI) is a 16-bit register. DI is used for indexed,

based indexed and register indirect addressing, as well as a

destination data address in string manipulation instructions.

Other registers:

Instruction Pointer (IP) is a 16-bit register.

Flags is a 16-bit register containing 9 1-bit flags:

Overflow Flag (OF) - set if the result is too large positive number,

or is too small negative number to fit into destination operand.

Direction Flag (DF) - if set then string manipulation instructions

will auto-decrement index registers. If cleared then the index

registers will be auto-incremented.

Interrupt-enable Flag (IF) - setting this bit enables maskable

interrupts.

Single-step Flag (TF) - if set then single-step interrupt will occur

after the next instruction.

Sign Flag (SF) - set if the most significant bit of the result is set.

Zero Flag (ZF) - set if the result is zero.

Auxiliary carry Flag (AF) - set if there was a carry from or borrow

to bits 0-3 in the AL register.

Parity Flag (PF) - set if parity (the number of "1" bits) in the low-

order byte of the result is even.

Carry Flag (CF) - set if there was a carry from or borrow to the

most significant bit during last result calculation.

MEMORY SEGMENTATION

There were also four sixteen-bit segment registers (CS, DS, SS, ES, standing for "code segment", "data segment", "stack segment" and "extra segment") that allowed the CPU to access one megabyte of memory in an unusual way.

Rather than concatenating the segment register with the address register, as in most processors whose address space exceeded their register size, the 8086 shifted the segment register left 4 bits and added it to the offset address (physical address = 16·segment + offset), producing a 20-bit effective address from the 32-bit segment:offset pair. As a result, each physical address could be referred to by 212 = 4096 different segment:offset pairs.

ADVANTAGE

This scheme had the advantage that a small program (less than 64 kilobytes) could be loaded starting at a fixed offset (such as 0) in its own segment, avoiding the need for relocation, with at most 15 bytes of alignment waste.

The 16-byte separation between segment bases was known as a "paragraph".

MINIMUM AND MAXIMUM MODE OF 8086

1:in min mode mn/mx- is connected to vcc .here now mn will be one AND IN MIN MODE ONLY ONE PROCESSOR IS PRESENT WITHOUT ANY CO PROCESSOR .

2: in max mode mn/mx- is cnnected to ground now the mx will become 1. AND IN MAX MODE MANY PROCESSORS ARE CONNECTED TO EACH OTHER WITHOUT ANY CO PROCESSOR EX FOR COPROCESSOR IS 8284

Minimum mode 8086 system

Turns MN/MX pin to logic 1

Control signals are given by microprocessor chip itselfSingle microprocessor with latches, transrecievers, clock generator memory & IO devices

Latches are used to separate valid address from address/data signals controlled by ALE

Transrecievers are bidirectional buffers Also termed as data amplifiersControlled by DEN or DT/R

A minimum mode of 8086 configuration depicts a stand alone system of computer

where no other processor is connected.

This is similar to 8085 block diagram with the following difference.

The Data transceiver block which helps the signals traveling a longer distance to

get boosted up.

Two control signals data transmit/ receive are connected to the direction input of

transceiver (Transmitter/Receiver) and DEN* signal works as enable for this

block

In the bus timing diagram, data transmit / receive signal goes low (RECEIVE) for

Read operation.

To validate the data, DEN* signal goes low. The Address/ Status bus carries A16

to A19 address lines during BHE* (low) and for the remaining time carries Status

information.

The Address/Data bus carries A0 to A15 address information during ALE going

high and for the remaining time it carries data.

The RD* line going low indicates that this is a Read operation. The curved arrows

indicate the relationship between valid data and RD* signal

The TW is Wait time needed to synchronize the fast processor with slow memory

etc.

The Ready pin is checked to see whether any peripheral needs more time for data

transmission.

This is the same as Read cycle Timing Diagram except that the DT/R* line goes high indicating it is a Data Transmission operation for the processor to memory / peripheral.

Again DEN* line goes low to validate data and WR* line goes low, indicating a Write operation.

The HOLD and HLDA timing diagram indicates in Time Space HOLD (input) occurs first and then the processor outputs HLDA (Hold Acknowledge).

5.MAXIMUM MODE

In the maximum mode of operation of 8086, wherein either a numeric

coprocessor of the type 8087 or another processor is interfaced with 8086.

The Memory, Address Bus, Data Buses are shared resources between the two

processors. The control signals for Maximum mode of operation are generated by

the Bus Controller chip 8788.

The three status outputs S0*, S1*, S2* from the processor are input to 8788. The

outputs of the bus controller are the Control Signals, namely DEN, DT/R*,

IORC*, IOWTC*, MWTC*, MRDC*, ALE etc.

These control signals perform the same task as the minimum mode operation.

However the DEN is an active HIGH signal which has to be converted to active

LOW by means of an inverter.

Here MRDC* signal is used instead of RD* as in case of Minimum Mode S0* to S2* are active and are used to generate control signal.

Here the maximum mode write signals are shown. Please note that the T states correspond to the time during which DEN* is LOW, WRITE Control goes LOW, DT/R* is HIGH and data output in available from the processor on the data bus.

Request / Grant pin may appear that both signals are active low. But in reality, Request signal goes low first (input to processor), and then the processor grants the request by outputting a low on the same pin.

ADDRESSING MEMORY AND i/o

BUS CONCEPT, DATA BUS, ADDRESS BUS, CONTROL BUSA Bus is a group of common wires in which signals travel. The three types of buses

used are the Address Bus, the Data Bus and the control Bus.

Address Bus

An address is a unique location in memory. It is like a mailbox in the post office, where each mail box has its own unique number to identify its location. An address bus consists of 16,20,24 or more parallel signal lines.

On these lines the CPU sends out the addresses of the memory location that is to be written to or read from.

The total number of memory locations is determined by the number or address lines. In the 8086 the address is determined by a 20-bit number. This gives us 220 possible address locations, or1,048,576 bytes of memory.

An address bus is made up of 20 wires, or conductors, labeled A0 through A19 , with A0 as the LSB and A19 as the MSB. It is used to locate or find information in memory. It is also used to define a location in memory where information is to be stored.

The address bus is some times used to identify which I/O port is used for input/output operations.

Data BusA data bus is used to move information ( data and instruction ) from the MPU to

memory and other devices. This is referred to as a write operation. The data bus is also

used to receive information into the MPU. This is called as a read operation. Because the

data bus receives and transmits information, it is known as a bi-directional bus.

However, it cannot receive and transmit data at the same time.

The Intel 8086 has a 16-bit data bus labeled D0 to D15, where D0 is the LSB and

D15 is the MSB.

The 8086 microprocessor multiplex the address and data buses.

Multiplexing is the process of using the same wires or pins to do different things at

different times.

When acting as a data bus, the signal lines carry read/write information for memory or

input/output information for I/O devices. When acting as an address bus, the same signal

lines are used to locate information.

Control Bus

The CPU sends out signals on the control bus to enable the outputs of addressed

memory devices or port devices.

The control line determines the sequence of operations to be performed. The control bus

consists of 4 to 10 parallel signal lines.

Typical control bus signals are memory read, memory write, I/O read, and I/O write. To

read a byte of data from a memory location, for example, the CPU sends out the address

of the desired byte on the address byte and then sends out a memory read signal on the

control bus.

The memory read signal enables the addressed memory device to output the byte of data

on to the data bus where it is required by the CPU.

Chapter 5

RAM & ROM, ADDRESSING MODES & CONTEXT SWITCHING

MemoryA memory stores large number of binary words. Since the early 1970s, ICs or semi

conductor memory have been the most widely used type of primary memory found in

micro computers.

The simplest form of computer memory is the basic flip-flop and a flipflop

is called a memory cell which can be used store a single bit ( 0 or 1). 8 or 16 cells are

connected together to form a memory byte or memory word.

Each memory byte or word has a unique location in the memory called an address.

Therefore, memory is a place where data bits ( 0 or 1) can be stored and then later

retrieved when the computer needs it. The process of storing data into the memory is

called writing.

The process of retrieving data from the memory is called reading. Accordingly, we say

that a microprocessor is in a write cycle or performing a write operation when it is

storing data into memory.

The process by which a microprocessor retrieves data from memory is called a read

cycle or read operation.

Memory classificationMemory can be classified into three general types, ROM and RAM. ROM stands

for read- only memory.

ROM generally contains permanently stored data that cannot be

changed. It can be read but not written into.

The main feature of ROMs is that they are non-volatile, which means that the information stored in them is not lost when the power

is removed.

RAM, on the other hand, is memory that can be read from or written to. RAM

stands for random-access memory, but since ROMs are also random access, the major

difference is that RAM is memory that can be read or written to.

RAM is actually read/write memory. RAM memory is volatile memory, that is, it is lost whenever the power is switched off.

ROMROMs can be classified into three general types. A maskable ROM is a ROM that

is programmed with information or data by the manufacturer. Once programmed these

data bits cannot be altered or changed. A programmable ROM, or PROM, is a device that

can be programmed by a user. Once programmed, the data in a PROM, like a ROM,

cannot be altered or changed . An erasable PROM, or EPROM, is a type of ROM that

can be programmed by an user but whose data may be erased or changed with use of

specialized equipment.

A summary of the different types of ROMs is given below:

Mask-programmed ROM -Programmed during manufacture; cannot bechanged.PROM- user programs by blowing fuses; cannot be erased except toblow additional fuses.EPROM- Electrically programmable by the user; erased by passingultra violet light through a quartz window in the package.EEPROM-Electrically programmable by the user; erased with electricalsignals instead of ultra violet light.

RAMRAM or read/write memory, is a type of volatile memory from which data can be

read and into which data can be written. RAM can be classified as either Static or

dynamic.

A Static RAM is essentially a matrix of flip-flops. Therefore, we can write a new data word in a RAM location at any time by applying the word to the flip-flop data input

and clocking the flip-flops.

The stored data word will remain on the flip-flop outputs as long as the power is left on. This type of memory is volatile because data is lost when the power is turned off. These types of storage device is called static RAM.

In dynamicRAMs, binary 1’s and 0’s are stored as an electrical charge or no charge on a tiny capacitor.

The internal capacitance of a MOSFET is great enough to make it appear that a small

capacitor (a few pico-farads ) exists in the MOSFET. Each memory cell is essentially a

single MOSFET.

A logic 1 or a charged capacitor must be refreshed, or recharged, at least

once every 2 ms, or the capacitor will lose its charge and the data.

Addressing Modes

The different ways that a processor can access data are referred to as its

addressing modes. It is the way by which the location of the operand is determined.

How

an operand is addressed in a program depends on the types and location of the data.

There are three general types of addressing modes:

Immediate addressing modes.

Register addressing modes.

25

Memory addressing modes.

Immediate Addressing mode

Suppose that in a program we need to put the number 526AH in the CX register.

The MOV CX, 526AH instruction can be used to do this. This instruction will put the

immediate hexadecimal number 526AH in the 16- bit CX register. This is referred to

as

immediate addressing mode because the number to be loaded into the CX register will be

put in two memory locations immediately following the code for the MOV instruction.

A similar instruction, MOV CL, 48H could be used to load the 8-bit immediate

number 48H into the 8-bit CL register. It is also possible to write instructions to load an

8-

bit immediate number into an 8-bit memory location or to load a 16-bit number into two

consecutive memory locations.

Register Addressing mode

Register is the source of an operand for an instruction in Register Addressing

mode.

For example, the instruction MOV CX, AX copies the contents of the 16-bit AX

register into the 16-bit CX register. Destination register is specified in the

instruction before the source.

When it executes, the contents of AX are just copied to CX, not actually moved.

In other words, the previous contents of CX are written over, but the contents of

AX are not changed. For example, if CX contains 2A84H and AX contains

4971H before the execution, then after the execution of the instruction CX will

contain 4971H and AX will still contain 4971H.

The contents of any 16-bit register can be moved into any 16-bit register, or the

contents of any 8-bit register can be moved into any 8-bit register.

However, an instruction of the type MOV CX, AL cannot be used because this is

an attempt to copy a byte- type operand (AL) into a word type destination (CX).

A byte in AL would fit in CX, but the 8086 would not know which half of CX to

put it in.

But if the byte from AL is to be copied into the high byte of CX, the instruction

MOV CH, AL could execute it. The instruction MOV CL, AL will copy the byte

from AL to CL, the low byte of CX.

Memory Addressing Modes

To access data in memory the 8086 must produce a 20-bit physical address. It is

done by adding a 16-bit value called the effective address to one of the four

segment

bases.

This effective address (EA) represents the displacement or offset of the desired

operand from the segment base. Any of the segment bases can be specified, but the data

segment is the one most often used. Fig 11(a) shows a graphic form how EA is added to

the data segment base to point an operand in the memory.

The fig 11(b) shows how the 20-bit physical address is generated by the BIU. The

starting address for the data segment in fig 10 (b) is 2000H so that the data segment

register will contain 2000 H.

The BIU shifts the 2000 H four bit positions left and adds the effective address, 437AH,

to the result. The 20-bit physical address sent out to memory by the BIU will then be

2437AH.

The physical address can be represented either as a single number, 2437AH, or in the

segment base; offset form as 2000 : 437AH

Direct Addressing ModeFor the simplest memory addressing mode the effective address is just an 8-bit or

16-bit number written directly in the instruction. The instruction MOV CL ,[437AH] is

an example.

The brackets around the 437AH are shorthand for “the contents of the memory location at

a displacement from the segment base of”.

When executed, this instruction will copy the contents of the memory location, at a

displacement of 437AH from the data segment base into the CL register. The actual 20-

bit physical memory address will be produced by shifting the data segment base in DS

four bits left and adding the effective address 437AH to the result. Fig 10(b) shows how

the operation is done.

This addressing mode is called direct because the displacement of the operand from the

segment base is specified directly in the instruction.

Another example of this addressing mode is the instruction MOV BX, [437AH].

When executed, this instruction copies a word from memory into BX register. Since each

memory address of the 8086 represents a byte of storage, the word must come from two

memory locations.

The byte at a displacement of 437AH from the data segment base will

be copied into BL. The contents of the next higher address, displacement 437BH will be

copied into BH register.

The 8086 will automatically access the required number of bytes in memory for a given

instruction.

The previous examples showed how the direct addressing mode can be used to

specify the source of an operand. It can also be used to specify the destination of an

operand.

The instruction MOV[437AH], BX for example will copy the contents of the

BX register to two memory locations in the data segment. The contents of BL will be

copied to the memory location as a displacement of 437AH and the contents of BH will

be copied to the memory location at a displacement of 437BH.

Indirect Addressing modeIn the direct addressing mode, either the source or the destination operand is a

specific memory location defined by the address number or a label.

For example, in the instruction MOV AX, MEM 1 the contents of the memory address labeled MEM 1 is copied or moved into AX register.

In the indirect addressing mode, the memory address is not directly given. A

register is used to indicate the address where the data can be found. Therefore , the

register acts as an indirect address to locate the data. For example, in the instruction

MOV (BX), CX the source of data is the CX register.

The destination where the data are to be placed or copied to, is the address pointed to by the BX register. The brackets ( )

around BX indicate that the BX register contains an address and not a numeric value.

SegmentationIntel has designed the 8086 family devices to use memory segmentation. By

working with only 64 K bytes segments of memory at a time, the 8086 only has to work

with 16-bit effective addresses to access any location in the segment. In other words,

because of the segmentation scheme the 8086 has to manipulate and store 16-bit address

components.

Also, in a time-share microcomputer system several users share a CPU. The

CPU works on one user’s program for perhaps 20 milliseconds. After working for 20 m

sec on one user’s program, it then works on the next user’s program for 20 milliseconds.

After working for 20 milliseconds for each of the other users, the CPU comes back to

working on the first user’s program again.

Each time the CPU switches from one user’s program to the next it must access a new section of code and sections of data.

Segmentation makes this switching quite easy. Each user’s program can be assigned a

separate set of logical segments for its code and data. The user’s program will contain

offsets or displacements from these segment bases to change from one user’s program to a second user’s program all that has to be done is to reload the four segment registers with the segment base address assigned to the second user’s program. In other words,

segmentation makes it easy to keep user’s programs and data separate from each other,

and segmentation makes it easy to switch from one user’s program to another user’s

program.

QUESTION BANK1. How many bits does 8086 microprocessor have?2. What is the size of data bus in 8086?3. What is the size of address bus in 8086?4. What is the max memory addressing capacity of 8086?5. Which are the basic parts of 8086?6. What are the functions of BIU?7. What are the functions of EU?8. How many pin IC 8086 is?9. What IC8086 is?10. What is the size of instruction queue in 8086?11. What is the size of instruction queue in 8088?12. Which are the registers present in 8086?13. What is pipelining in 8086?14. How many 16 bit registers are available in 8086?15. Specify addressing modes for any instruction?16. What is assembler directives?17. What .model small stands for?18. What is the supply requirement of 8086?19. What is the relation between 8086 processor frequency &

crystal frequency?20. Functions of Accumulator or AX register?21. Functions of BX register?22. Functions of CX register?23. Functions of DX register?24. How Physical address is generated?25. Which are pointers present in this 8086?26. Which is by default pointer for CS/ES?27. How many segments present in it?28. What is the size of each segment?29. Basic difference between 8085 and 8086?30. Which operations are not available in 8085?

31. What is the difference between min mode and max mode of 8086?

32. What is the difference between near and far procedure?33. What is the difference between Macro and procedure?34. What is the difference between instructions RET & IRET?35. What is the difference between instructions MUL & IMUL?36. What is the difference between instructions DIV & IDIV?37. What is difference between shifts and rotate instructions?38. Which are strings related instructions?39. Which are addressing modes and their examples in 8086?40. What does u mean by directives?41. What does u mean by Prefix?42. What .model small means?43. Difference between small, medium, tiny, huge?44. What is dd, dw, db?45. Interrupts in 8086 and there function.46. What is the function of 01h of Int 21h?47. What is the function of 02h of Int 21h?48. What is the function of 09h of Int 21h?49. What is the function of 0Ah of Int 21h?50. What is the function of 4ch of Int 21h?51. What is the reset address of 8086?52. What is the size of flag register in 8086? Explain all.53. What is the difference between 08H and 01H functions of

INT 21H?54. Which is faster- Reading word size data whose starting

address is at even or at odd address of memory in 8086?55. Which are the default segment base: offset pairs?56. Can we use SP as offset address holder with CS?57. Which are the base registers in 8086?58. Which is the index registers in 8086?59. What is segment override prefix?60. Whether micro reduces memory requirements?61. What is macro?62. What is diff between macro and procedure?63. Types of procedure?64. What TASM is?65. What TLINK is?66. What TD is?67. What do u mean by assembler?68. What do u mean by linker?69. What do u mean by loader?70. What do u mean by compiler?71. What do u mean by emulator?72. Stack related instruction?73. .stack 100 means?

74. What is 20 dup (0)?75. Which flags of 8086 are not present in 8085?76. What is the size of flag register?77. Can you perform 32 bit operation with 8086? How?78. Whether 8086 is compatible with Pentium processor?79. What is 8087? How it is different from 8086?80. While accepting no. from user why u need to subtract 30

from that?81. While displaying no. from user why u need to add 30 to

that?82. What are ASCII codes for nos. 0 to F?83. How does U differentiate between positive and negative

numbers?84. What is range for these numbers?85. Which no. representation system you have used?86. What is LEA?87. What is @data indicates in instruction- MOV ax, @data?88. What is maximum size of the instruction in 8086?89. Why we indicate FF as 0FF in program?90. What is mul BX and div BX? Where result goes?91. Where queue is present?92. What is the advantage of using internal registers?93. What is SI, DI and their functions?94. Which are the pointers used in 8086 and their functions?95. What is a type of queue in 8086?96. What is minimum mode of 8086?97. What is maximum mode of 8086?98. Which are string instructions?99. In string operations which is by default string source

pointer?100. In string operations which is by default string destination

pointer?