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Prepared by: Dr.R.Umamaheswari, EEE/REC 1 UNIT V : VHDL VHDL stands for V HSIC (Very High Speed Integrated Circuits) H ardware D escription L anguage. In the mid-1980’s the U.S. Department of Defense in need to develop a common platform to describe different digital systems from different VLSI suppliers/vendors and later in 1987 VHDL is standardized by IEEE. It has become now one of industry’s standard languages used to describe, simulate, test complex digital system designs. Purpose of H ardware D escription L anguage: For describing hardware. As a modeling language. For simulation of hardware. For early performance estimation of system architecture. For synthesis of hardware. For fault simulation, test and verification of designs. The other widely used hardware description language is Verilog. Primarily targeted for design of ASICs (Application Specific Integrated Circuits). A third HDL language is ABEL (Advanced Boolean Equation Language) which was specifically designed for Programmable Logic Devices (PLD). ABEL is less powerful than the other two languages and is less popular in industry. This unit deals with VHDL, as described by the IEEE standard 1076-1993. A hardware description language is inherently parallel, i.e. commands, which correspond to logic gates, are executed (computed) in parallel, as soon as a new input arrives. A HDL program mimics the behavior of a physical digital system. It also allows incorporation of timing specifications (gate delays) as well as to describe a system as an interconnection of different component. VHDL is the integration of Sequential language Concurrent language Net-list language Timing specification language Waveform generation/simulation language Mechanisms to reduce complexity (improve flexibility) are Language abstraction Design hierarchy Abstraction levels A digital system can be represented at different levels of abstraction. This keeps the description and design of complex systems manageable. Figure shows different levels of abstraction. VHDL is rich in language abstractions, in addition to which the language can be used to describe different abstraction levels, from functions right down to a gate description. Abstraction levels are a means of concealing details Hierarchical design One can define components of units that are used over and over again. Once these components are defined they can be used as blocks, cells or macros in a higher level entity. This can significantly reduce the complexity of large designs. While designing complex systems Hierarchical design approaches are always preferred over flat designs. VHDL analysis: Reads one or more design units contained in a single file and compiles them into a design library after validating the syntax and performs static semantic checks. Model - - - analysis - - - > simulation VHDL design description file VHDL analyser Intermediate format WORK LIB STD IEEE Design library Syntax check Static semantic check Complied descriptions

UNIT 5_ VHDL

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Prepared by: Dr.R.Umamaheswari, EEE/REC 1

UNIT V : VHDL

VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language.In the mid-1980’s the U.S. Department of Defense in need to develop a common platform to describe different digital systems from different VLSI suppliers/vendors and later in 1987 VHDL is standardized by IEEE. It has become now one of industry’s standard languages used to describe, simulate, test complex digital system designs.

Purpose of Hardware Description Language: For describing hardware. As a modeling language. For simulation of hardware. For early performance estimation of system architecture. For synthesis of hardware. For fault simulation, test and verification of designs.

The other widely used hardware description language is Verilog. Primarily targeted for design of ASICs (Application Specific Integrated Circuits). A third HDL language is ABEL (Advanced Boolean Equation Language) which was specifically designed for Programmable Logic Devices (PLD). ABEL is less powerful than the other two languages and is less popular in industry. This unit deals with VHDL, as described by the IEEE standard 1076-1993.

A hardware description language is inherently parallel, i.e. commands, which correspond to logic gates, are executed (computed) in parallel, as soon as a new input arrives. A HDL program mimics the behavior of a physical digital system. It also allows incorporation of timing specifications (gate delays) as well as to describe a system as an interconnection of different component.

VHDL is the integration of Sequential language Concurrent language Net-list language Timing specification language Waveform generation/simulation language

Mechanisms to reduce complexity (improve flexibility) are Language abstraction Design hierarchy

Abstraction levelsA digital system can be represented at different levels of abstraction. This keeps the description and design of complex systems manageable. Figure shows different levels of abstraction. VHDL is rich in language abstractions, in addition to which the language can be used to describe different abstraction levels, from functions right down to a gate description. Abstraction levels are a means of concealing details Hierarchical designOne can define components of units that are used over and over again. Once these components are defined they can be used as blocks, cells or macros in a higher level entity. This can significantly reduce the complexity of large designs. While designing complex systems Hierarchical design approaches are always preferred over flat designs.

VHDL analysis:Reads one or more design units contained in a single file and compiles them into a design library after validating the syntax and performs static semantic checks. Model - - - analysis - - - > simulation

VHDL design description file

VHDL analyser

Intermediate format

WORK LIB

STD IEEE

Design library

Syntax checkStatic semantic check Complied descriptions

Prepared by: Dr.R.Umamaheswari, EEE/REC 2

VHDL Synthesis (design) strategies :Top to bottom design approach means Increasing Complexity. Synthesis can be done in each level. The volume of information increases between the various abstraction levels eg. Technology information is required to synthesize from Register Transfer Level (RTL) to gate level. Each transition (synthesis) generates more information. In order to implement a function in an IC, the followings are required: technology information - wiring information -gate information - set-up times.

The highest level of abstraction is the behavioral level that describes a system in terms of what it does (or how it behaves) rather than in terms of its components and interconnection between them. A behavioral description specifies the relationship between the input and output signals. This could be a Boolean expression or a more abstract description such as the Algorithmic or Register Transfer level. As an example, let us consider a simple circuit that warns car passengers when the door is open or the seatbelt is not used whenever the car key is inserted in the ignition lock. At the behavioral level this could be expressed as, Warning = Ignition_on AND ( Door_open OR Seatbelt_off)

On the other hand, the structural level describes a system as a collection of gates and components that are interconnected to perform a desired function. A structural description could be compared to a schematic of interconnected logic gates. It is a representation that is usually closer to the physical realization of a system. For the example above, the structural representation is given in fig.

VHDL allows one to describe a digital system at the structural or the behavioral level or both combined. The behavioral level can be further divided into two kinds of styles: Data flow and Algorithmic. The dataflow representation describes how data moves through the system. This is typically done in terms of data flow between registers (Register Transfer level). The data flow model makes use of concurrent statements that are executed in parallel as soon as data arrives at the input. On the other hand, sequential statements are executed in the sequence that they are specified. VHDL allows both concurrent and sequential signal assignments that will determine the manner in which they are executed.

RTL stands for Register-Transfer Level. It is an essential part of top-down digital design process. Logic synthesis offers an automated route from an RTL design to a Gate-Level design. In RTL design a circuit is described as a set of registers and a set of transfer functions describing the flow of data between the registers, (ie. FSM + Datapath). As an important part of a complex design, this division is the main objective of the hardware designer using synthesis. There are Examples illustrates that the RTL synthesis is more efficient than the behavior synthesis, although the simulation of previous one requires a few clock cycles.

• Register level /Dataflow- Most are like assigning expressions to signals –concurrent (if-then-else, Add, Subtract ) • Behavioral -Write an algorithm that describes the circuit’s output- sequential(functions and processes)• Structural - Define explicit components and the connections between them.(components, Gates and wires)

Register Transfer Level, or RTL design lies between a purely behavioral description of the desired circuit and a purely structural one. An RTL description describes a circuit’s registers and the sequence of transfers between these registers but does not describe the hardware used to carry out these operations. The steps in RTL design are: (1) determine the number and sizes of registers needed to hold the data used by the device, (2) determine the logic and arithmetic operations that need to be performed on these register contents, and (3) design a state machine whose outputs control how the register contents are updated in order to obtain the desired results.

Producing an RTL design is similar to writing a computer program in a conventional programming language. Choosing registers is the same as choosing variables. Designing the flow of data in the “datapath” is analogous to writing expressions involving the variables (registers) and operators (combinational functions). Designing the controller state machine is similar to deciding on the flow of control within the program (if/then/else, while-loops, etc).

Prepared by: Dr.R.Umamaheswari, EEE/REC 3

Circuits that divide up a computation into a sequence of arithmetic and logic operations are quite common and this type of design is called Register Transfer Level (RTL) or “dataflow” design.An RTL design is composed of (1) registers and combinational function blocks (e.g. adders and multiplexers) called the datapath and (2) a finite state machine, called the controller that controls the transfer of data through the function blocks and between the registers.In VHDL RTL design the gate-level design and optimization of the datapath (registers, multiplexers, and combinational functions) is done by the synthesizer. However, the designer must design the state machine and decide which register transfers are performed in which state. RTL design is well suited for the design of CPUs and special-purpose processors such as disk drive controllers, video display cards, network adapter cards, etc. It gives the designer great flexibility in choosing between processing speed and circuit complexity.

Basic Structure of a VHDL fileBasic designs constructs of VHDL model are an interface (entity declaration) and a body (architectural description). An entity-architecture pair is a design entity.A digital system described in VHDL consists of a design entity that can contain other entities that are then considered components of the top-level entity. Each entity is modeled by an entity declaration and an architecture body. One can consider the entity declaration as the interface to the outside world that defines the input and output signals, while the architecture body contains the description of the entity and is composed of interconnected entities, processes and components, all operating concurrently, as schematically shown in fig. In a typical design there will be many such entities connected together to perform the desired function.An VHDL model consist of 5 basic design units.Entity declaration, Architecture Body, Configuration declaration, Package declaration, Package body declaration

1. Entity Declarationentity NAME_OF_ENTITY is [ generic generic_declarations);]

port (signal_names: mode type; signal_names: mode type; : signal_names: mode type);end [NAME_OF_ENTITY] ;

The NAME_OF_ENTITY is a user-selected identifiermode: in – indicates that the signal is an input

out – indicates that the signal is an output of the entity whose value can only be read by other entities that use it.buffer – indicates that the signal is an output of the entity whose value can be read inside the entity’s architectureinout – the signal can be an input or an output.

type: bit – can have the value 0 and 1bit_vector – is a vector of bit values (e.g. bit_vector (0 to 7)std_logic, std_ulogic, std_logic_vector, std_ulogic_vector: can have 9 values to indicate the value and strength of a signal. Std_ulogic and std_logic are preferred over the bit or bit_vector types.boolean – can have the value TRUE and FALSEinteger – can have a range of integer valuesreal – can have a range of real valuescharacter – any printing charactertime – to indicate time

generic: generic declarations are optional and determine the local constants used for timing and sizing (e.g. bus widths) the entity. A generic can have a default value. The syntax for a generic follows,

generic ( constant_name: type [:=value] ;constant_name: type [:=value] ;:constant_name: type [:=value] );

Entity declaration

Architecture Body

Configuration declaration

Package declaration

Package body

Port

VHDL entity

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2. Architecture body architecture architecture_name of NAME_OF_ENTITY is -- Declarations -- components declarations -- signal declarations -- constant declarations -- function declarations -- procedure declarations -- type declarations

: begin -- Statements Label : component-name port map (port1=>signal1, port2=> signal2,… port3=>signaln); : end architecture_name;

Notice that the order in which these statements are written has no bearing on the execution since these statements are concurrent and therefore executed in parallel. Indeed, the schematic that is described by these statements is the same independent of the order of the statements.Delay models : 1) Inertial delay 2) temporal delayExample VHDL code half adder ( in all 3 different ways)-- Half adder in Data flow waylibrary ieee;use ieee.std_logic_1164.all;

entity halfAdder is port( A, B : in std_logic; sum, Cout : out std_logic);end halfAdder;

architecture HA_DFLOW of halfAdder isbegin sum <= A xor B after 8ns; Cout<= A and B after 4ns;end HA_DFLOW;

configuration HA_config of halfAdder is for HA_DFLOW end for;end HA_config-- Half adder in Behavioral waylibrary ieee;use ieee.std_logic_1164.all;

entity halfAdder is port( A, B : in std_logic; sum, Cout : out std_logic);end halfAdder;

architecture HA_BEHAV of halfAdder isbegin Process (A,B) Variable V1,V2:Bit; begin V1:=A xor B; V2:=A and B; sum <= V1; Cout <= V2; end process;end HA_BEHAV;

-- Half adder in structural waylibrary ieee;use ieee.std_logic_1164.all;

entity halfAdder is port( A, B : in std_logic; sum, Cout : out std_logic);end halfAdder;

architecture HA_STRC of halfAdder is component XOR2 is –- XOR2 separate entity model port( X, Y : in std_logic; Z : out std_logic); end component;

component AND2 is –- AND2 separate entity model port( L, M : in std_logic; N : out std_logic); end component;

begin G1 : XOR2 port map(A, B, sum); G2 : AND2 port map(A, B, Cout);end HA_STRC;

library CMOS_LIB, MY_LIB;

Configuration HA_BIND of halfAdder is for HA_STRC for G1 : XOR2 use entity CMOS_LIB.XOR_GATE(DATAFLOW); end for; for G2 : AND2 use entity CMOS_LIB.AND_GATE(DATAFLOW); end for; end for;end HA_BIND;

3. Configuration declaration: Used for Binding of componentsStructural modeling of design lends itself to hierarchical design, in which one can define components of units that are used over and over again. Once these components are defined they can be used as blocks, cells or macros in a higher level entity. This can significantly reduce the complexity of large designs.

Prepared by: Dr.R.Umamaheswari, EEE/REC 5

Library

If we keep the description of a circuit’s interface (the entity) separate from its contents (the architecture), we need a way to link or bind them togetherentity = block diagramarchitecture (for an entity) = a more detailed circuit schematic for the block diagramconfiguration = a parts list of the circuit components with their part numbers and manufacturers

-- configuration_declaration configuration identifier of entity_name is

block_configuration end [configuration] identifier;

4. Library and Packages: library and use keywordsA library can be considered as a place where the compiler stores information about a design project. A VHDL package is a file or module that contains declarations of commonly used objects, data type, component declarations, signal, procedures and functions that can be shared among different VHDL models.

e.g., std_logic is defined in the package ieee.std_logic_1164 in the ieee library. In order to use the std_logic one needs to specify the library and package. This is done at the beginning of the VHDL file using the library and the use keywords as follows:

library ieee;use ieee.std_logic_1164.all; -- The .all extension indicates to use all of the ieee.std_logic_1164 package.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_signed.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_misc.all;

5. Package body declarationOne can add other libraries and packages. The syntax to declare a package is as follows: -- Package declaration

package name_of_package is package declarations end package name_of_package;

-- Package body declarations package body name_of_package is package body declarations end package body name_of_package;

For instance, the basic functions of the AND2, OR2, NAND2, NOR2, XOR2, etc. components need to be defined before one can use them. This can be done in a package, e.g. basic_func for each of these components. library ieee; -- Package declarationuse ieee.std_logic_1164.all;package basic_func is component AND2 -- AND2 declaration generic (DELAY: time :=5ns); port (in1, in2: in std_logic; out1: out std_logic); end component; component OR2 -- OR2 declaration generic (DELAY: time :=5ns); port (in1, in2: in std_logic; out1: out std_logic); end component;end package basic_func;

package body basic_func is -- Package body declarations entity AND2 is -- 2 input AND gate

Package Package

component

component

component

component

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generic (DELAY: time); port (in1, in2: in std_logic; out1: out std_logic); end AND2; architecture model_conc of AND2 is begin out1 <= in1 and in2 after DELAY; end model_conc; entity OR2 is -- 2 input OR gate generic (DELAY: time);

port (in1, in2: in std_logic; out1: out std_logic); end OR2; architecture model_conc2 of AND2 is begin out1 <= in1 or in2 after DELAY; end model_conc2;end package body basic_func;

Basic language Elements of VHDLIdentifiers : _,A…Z,a…z,0…9Keywords (Reserved words): in, out, or, and, port, map, endDatatypes

1. Scalar type (enumeration, integer, physical, floating point)2. Composite type(Characters, Strings and Bit Strings)3. Access type4. File type

Data Objects (constants, variables, signal, file)A data object is created by an object declaration and has a value and type associated with it. An object can be a Constant, Variable, Signal or a File. Up to now we have seen signals that were used as input or output ports or internal nets. Signals can be considered wires in a schematic that can have a current value and future values, and that are a function of the signal assignment statements. On the other hand, Variables and Constants are used to model the behavior of a circuit and are used in processes, procedures and functions, similarly as they would be in a programming language. Following is a brief discussion of each class of objects.Variable assignment eg. V1 :=A and B;Signal assignment eg. Z <= A and B after 4 ns;

9 values for signal in IEEE std_logic:‘0’ -- Forcing 0‘1’ -- Forcing 1‘X’ -- Forcing Unknown‘-’ -- Don’t Care‘Z’ -- High Impedance

‘U’ – Uninitialized‘W’ – Weak‘L’ -- Weak 0‘H’ -- Weak 1

Operators: VHDL supports different classes of operators that operate on signals, variables and constants. The different classes of operators are summarized below.

Class1. Logical operators and or nand nor xor xnor2. Relational operators = /= < <= > >=3. Shift operators sll srl sla sra rol ror4.Addition operators + = &5. Unary operators + -6. Multiplying op. * / mod rem7. Miscellaneous op. ** abs not

StatementsBehavioral Modeling: Process (sequential statements) Concurrent statement If , if else Statements Case statements Loop statements

Next, Exit Statement Wait statement (postpone the execution of a process)

Null statement (does not cause any action)Structural Modeling

Component declaration

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Component Instantiation and interconnections(port map)

Test benchA model (written in VHDL) that is used to exercise and verify the correctness of the hardware model.

3 purposes of test bench(1) To generate stimulus for simulation/waveform.(2) To apply this stimulus to the entity under test and collect

the output responses.(3) To compare output responses with expected values.

example for n bit adder with test bench-- model design library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;

entity ADDER isgeneric(n: natural :=2);port( A: in std_logic_vector(n-1 downto 0);

B: in std_logic_vector(n-1 downto 0);carry: out std_logic;sum: out std_logic_vector(n-1 downto 0));

end ADDER;

architecture behv of ADDER is signal result: std_logic_vector(n downto 0); -- temparary signal to store the resultbegin -- the 3rd bit should be carry result <= ('0' & A)+('0' & B); sum <= result(n-1 downto 0); carry <= result(n);end behv;

-- test bench library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;

entity test_add is generic ( width : integer := 17 ); port ( clk : in std_ulogic; reset : in std_ulogic; enable : in std_ulogic; inp1, inp2 : in std_logic_vector ( width downto 0); sum : out std_logic_vector ( (width + 1) downto 0) );end test_add;-- RTL description. Adds two inputs together (unsigned) into an integer-- of "width + 1" in length.architecture rtl of test_add is constant terminal_count : integer := 2**( sum'high + 1 ) - 1; subtype adder_range is integer range 0 to terminal_count; signal sumx, inp1x, inp2x : adder_range;begin -- rtl sum <= std_logic_vector( to_unsigned ( sumx, width + 2 )); inp1x <= to_integer ( unsigned ( inp1 ) );

MatchNeed correction

Need correction

goodgood

simulationsimulation

VHDLEntity

SynthesisTool

Net list

RTL design

TEST BENCHCODE

Gate level design

FabricateIC

Results compare Results

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inp2x <= to_integer ( unsigned ( inp2 ) ); ADDER : process ( clk, reset ) begin if reset = '0' then sumx <= 0; elsif rising_edge (clk) then if enable = '1' then sumx <= inp1x + inp2x; end if; end if; end process adder;

end rtl;

VHDL sample design file

1. Gates operations

-- AND gate

library ieee;use ieee.std_logic_1164.all;

entity andGate is port( A, B : in std_logic; F : out std_logic);end andGate;

architecture func of andGate is begin F <= A and B;end func;

-- OR gate

library ieee;use ieee.std_logic_1164.all;

entity orGate is port( A, B : in std_logic; F : out std_logic);end orGate;

architecture func of orGate is begin F <= A or B;end func;

-- xor gate yxyxyx entity XOR2 is port (A, B: in std_logic; Z: out std_logic); end XOR2;

architecture behavioral_xor of XOR2 is-- signal declaration (of internal signals X, Y)

signal X, Y: std_logic;begin

X <= A and B;Y <= (not A) and (not B);Z <= X or Y;

End behavioral_xor;

-- VHDL code for AND-OR-INVERT gate

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity AOI isport ( A, B, C, D: in STD_LOGIC; F : out STD_LOGIC);end AOI;

architecture V1 of AOI isbegin F <= not ((A and B) or (C and D));end V1;-- end of VHDL code

2. Full adder

Structural Behavior

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library ieee;use ieee.std_logic_1164.all;

entity fullAdder is port( A, B, Cin : in std_logic; sum, Cout : out std_logic);end fullAdder;

architecture FAfromHA of fullAdder is

component halfAdder is --import Half Adder entity port( A, B : in std_logic; sum, Cout : out std_logic); end component;

component orGate is --import OR Gate entity port( A, B : in std_logic; F : out std_logic); end component;

signal halfTohalf, halfToOr1, halfToOr2: std_logic;

begin G1: halfAdder port map(A, B, halfTohalf, halfToOr1); G2: halfAdder port map(halfTohalf, Cin, sum, halfToOr2); G3: orGate port map(halfToOr1, halfToOr2, Cout);end fullAdder;

-- full adder in Behavioral waylibrary ieee;use ieee.std_logic_1164.all;ENTITY full_adder IS --- Full Adder PORT(a,b,c: IN BIT ; sum, carry : OUT BIT); END full_adder;ARCHITECTURE full_adder_beh OF full_adder ISBEGIN PROCESS(a,b,c) -- Sensitivity list VARIABLE temp :BIT; BEGIN temp := a XOR b; sum <= temp XOR c; carry <= (a AND b) OR (temp AND c); END PROCESS ; END full_adder_beh;

3. Four Bit Adder

Four Bit Adder – Illustrating a hierarchical VHDL model-- Example of a four bit adderlibrary ieee;use ieee.std_logic_1164.all;-- definition of a full adderentity FULLADDER is port (a, b, c: in std_logic;

sum, carry: out std_logic); end FULLADDER;

architecture fulladder_behav of FULLADDER isbegin

sum <= (a xor b) xor c ;carry <= (a and b) or (c and (a xor b));

end fulladder_behav;

-- 4-bit adderlibrary ieee;use ieee.std_logic_1164.all;

entity FOURBITADD is port (a, b: in std_logic_vector(3 downto 0); Cin : in std_logic;

sum: out std_logic_vector (3 downto 0); Cout, V: out std_logic); end FOURBITADD;

architecture fouradder_structure of FOURBITADD is signal c: std_logic_vector (4 downto 0);

component FULLADDER port(a, b, c: in std_logic;

sum, carry: out std_logic); end component;

begin FA0: FULLADDER port map (a(0), b(0), Cin, sum(0), c(1)); FA1: FULLADDER port map (a(1), b(1), C(1), sum(1), c(2)); FA2: FULLADDER port map (a(2), b(2), C(2), sum(2), c(3));

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FA3: FULLADDER port map (a(3), b(3), C(3), sum(3), c(4)); V <= c(3) xor c(4); Cout <= c(4);

end fouradder_structure;

5. 6.

7. flipflop

-- the description of JK Flip-Flop is based on functional truth table

library ieee;use ieee.std_logic_1164.all;

entity JK_FF isport ( clock: in std_logic;

J, K: in std_logic;reset: in std_logic;Q, Qbar: out std_logic);

end JK_FF;

architecture behv of JK_FF is signal state: std_logic; -- define the useful signals here signal input: std_logic_vector(1 downto 0);begin input <= J & K; -- combine inputs into vector p: process(clock, reset) is begin

if (reset='1') then state <= '0';elsif (rising_edge(clock)) then -- compare to the truth table case (input) is

when "11" => state <= not state;when "10" => state <= '1';when "01" => state <= '0';when others => null;end case;

end if; end process;

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Q <= state; -- concurrent statements Qbar <= not state;end behv;

8. synchronous counter (up/down counter with async. reset and synchronous parallel load.)

library IEEE; -- typical packages declarationuse IEEE.std_logic_1164.all;use IEEE.numeric_std.all;

entity COUNT_8B is -- entityport ( RESET,CLK,LD,UP : in std_logic;DIN : in std_logic_vector (7 downto 0);COUNT : out std_logic_vector (7 downto 0));

end COUNT_8B;

architecture my_count of COUNT_8B is -- architecture in Behavioral Modelsignal t_cnt : unsigned(7 downto 0); -- internal counter signalbegin

process (CLK, RESET)beginif (RESET = '1') then

t_cnt <= (others => '0'); -- clearelsif (rising_edge(CLK)) then

if (LD = '1') then t_cnt <= unsigned(DIN); -- loadelse

if (UP = '1') then t_cnt <= t_cnt + 1; -- increlse t_cnt <= t_cnt - 1; -- decrend if;

end if;end if;end process;

COUNT <= std_logic_vector(t_cnt);end my_count;

VHDL is a design description language – not a language that automatically design the circuits for you! You must first design on paper using truth table /state table and block

diagrams with interconnections, before you can describe it in VHDL!

VHDL versus C TerminologyAnalyze - compileElaborate - linkComponent - functionInstantiate - calluse - #includepackage - DLLlibrary - directory

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VHDL for n bit counter with test bench. – demonstration Counter Design Block

Counter Design Specifications

4-bit synchronous up counter. active high, synchronous reset. Active high enable.

Counter Design

1 library ieee ; 2 use ieee.std_logic_1164.all; 3 use ieee.std_logic_unsigned.all; 4 5 entity counter is 6 port( clk: in std_logic; 7 reset: in std_logic; 8 enable: in std_logic; 9 count: out std_logic_vector(3 downto 0)10 );11 end counter;1213 architecture behav of counter is 14 signal pre_count: std_logic_vector(3 downto 0);15 begin16 process(clk, enable, reset)17 begin18 if reset = '1' then19 pre_count <= "0000";20 elsif (clk='1' and clk'event) then21 if enable = '1' then22 pre_count <= pre_count + "1";23 end if;24 end if;25 end process; 26 count <= pre_count;27 end behav;

You could download file counter.vhd here

Counter Test BenchAny digital circuit, no matter how complex, needs to be tested. For the counter logic, we need to provide a clock and reset logic. Once the counter is out of reset, we toggle the enable input to the counter, and check the waveform to see if the counter is counting correctly. The same is done in VHDL

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Prepared by: Dr.R.Umamaheswari, EEE/REC 13

Counter testbench consists of clock generator, reset control, enable control and monitor/checker logic. Below is the simple code of testbench without the monitor/checker logic.

1 library ieee ; 2 use ieee.std_logic_1164.all; 3 use ieee.std_logic_unsigned.all; 4 use ieee.std_logic_textio.all; 5 use std.textio.all; 6 7 entity counter_tb is 8 end; 910 architecture counter_tb of counter_tb is1112 component counter13 port ( count : out std_logic_vector(3 downto 0);14 clk : in std_logic;15 enable: in std_logic;16 reset : in std_logic);17 end component ;1819 signal clk : std_logic := '0';20 signal reset : std_logic := '0';21 signal enable : std_logic := '0';22 signal count : std_logic_vector(3 downto 0);2324 begin2526 dut : counter 27 port map (28 count => count,29 clk => clk,30 enable=> enable,31 reset => reset );3233 clock : process34 begin35 wait for 1 ns; clk <= not clk;36 end process clock;37

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Prepared by: Dr.R.Umamaheswari, EEE/REC 14

38 stimulus : process39 begin40 wait for 5 ns; reset <= '1';41 wait for 4 ns; reset <= '0';42 wait for 4 ns; enable <= '1';43 wait;44 end process stimulus;4546 monitor : process (clk)47 variable c_str : line;48 begin49 if (clk = '1' and clk'event) then50 write(c_str,count);51 assert false report time'image(now) & 52 ": Current Count Value : " & c_str.all53 severity note;54 deallocate(c_str);55 end if;56 end process monitor;5758 end counter_tb;

You could download file counter_tb.vhd here

time clk reset enable counter0 1 0 0 xxxx5 0 1 0 xxxx10 1 1 0 xxxx11 1 1 0 000015 0 0 0 000020 1 0 0 000025 0 0 1 000030 1 0 1 000031 1 0 1 000135 0 0 1 000140 1 0 1 000141 1 0 1 001045 0 0 1 001050 1 0 1 001051 1 0 1 001155 0 0 1 001160 1 0 1 001161 1 0 1 010065 0 0 1 010070 1 0 1 010071 1 0 1 010175 0 0 1 010180 1 0 1 010181 1 0 1 011085 0 0 1 011090 1 0 1 011091 1 0 1 011195 0 0 1 0111100 1 0 1 0111101 1 0 1 1000105 0 0 1 1000110 1 0 1 1000111 1 0 1 1001

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Prepared by: Dr.R.Umamaheswari, EEE/REC 15

115 0 0 1 1001120 1 0 1 1001121 1 0 1 1010125 0 0 0 1010

Counter Waveform