1

Ultra-Rapid Polishing of Silicon

Carbide (SiC) substrates

Rajiv K. Singh

CTO & Founder, Sinmat Inc

Professor, University of Florida

Fellow: IEEE, ECS, APS, MRS, ASM & AAAS

rksingh@sinmat.com

2

Outline

1. Sinmat Overview

2. CMP Technology for SiC

3. CMP Technology for GaN

4. CMP of Diamond

5. Defect Reduction in SiC homo-epitaxy by

novel CMP enabled substrates

6. Conclusions

3

Overview: Sinmat Inc.

• University of Florida Spin-off

• Novel planarization technologies for the semiconductor industry

• Winner of four R&D 100 Awards 2004 & 2005, 2008, 2009

• Top 100 most significant technologies of the year

• 10 licensed and pending patents

• Employees : 28 and several consultants

• Currently the largest worldwide supplier of SiC CMP slurries

4

CMP Slurries and Processes for Current and Next

Generation Semiconductors

s

p

slurry feed

polishing pad platen

wafer

pressure

5

Challenges: Polishing of Hard/Inert Materials

Materials Hardness Knoop

(Kg/mm2)

Chemical

Action

Silicon Carbide 2150 - 2900 Inert

Quartz 820-1000

Porous Silica (SiO2) 200-500

Gallium Nitride 1580 - 1640 Inert

Sapphire (Al2O3) 2000-2050 Inert

Diamond 8000 - 10000 Inert

• Polishing rate is slow when soft particles such as

silica are used (10 nm -100 nm/hr)

Mechanical Polishing of SiC

Poor Surface Quality

High Density of Scratches

Rms roughness > 1 nm, sub-surface damage

Surface Morphology: Optical Finish 10 µm × 10 µm

Surface Preparation requires CMP

7

Challenges: Polishing Anisotropy

• Least removal rate and worst

surface finish in C-face polishing

• C-face polishing rates 20 times

less than Si face (6 nm/hr)

AFM of c-face after CMP

Example of Polishing Defects in GaN using

Conventional Processes

Sub-surface damage

Scratches

Non Planarity GaN on Silicon

Stresses

Ref . P Tavernier (JECS 2003)

9

Reactive CMP (RCMP) Approach : Soft Layer

Polishing

Surface reaction using surface modified nanoparticles. Soft layer Creation Soft layer removal by soft particles Ultra-smooth surfaces Low Friction process – no edge pull outs No silica contamination No defect delineation

Å t

o n

m

Substrate (GaN)

Chemically modified soft layer

10

RCMP SiC Polishing: Ultra-High Removal Rates

Synergistic role of particles + chemistry

Tunable Slurry for high finish/high rate

0

200

400

600

800

1000

1200

1400

1600

Conventional

CMP

State-of-the-Art

Si face CMP Si face

Sinmat

CMP

C face

Sinmat

CMP

10-20

nm/hr

Rem

oval

Rate

(n

m/h

r)

15-25

nm/hr

100 -125

nm/hr

1500 nm/hr

> 10000 nm/hr

Enhancement factor of 15

over state-of-the-art 1500

State-of-the-Art

C face CMP

≈

2000

4000

5000

≈

Enhancement factor of 200

over state-of-the-art

RCMP GaN Polishing Performance

Removal rate of up to 800 nm/hr obtained during planarization

Polish rate 10 - 20X higher than conventional CMP

0

100

200

300

400

500

600

700

800

900

1000

10-50

nm/hr Rem

oval

Rate

(n

m/h

r)

400-800

nm/hr

Enhancement factor of 25-40

over state-of-the-art

State-of-the-Art

GaN CMP Sinmat GaN RCMP

AFM Surface Finish of SiC Surfaces After RCMP Polishing:

Atomically Terraced Surfaces

After polishing Line scan

GaN AFM Surface Finish After RCMP

Polishing: Atomically Terraced Features

Ra- 0.9 A, RMS- 1.2 A, Rz- 1.2 nm

14

Sinmat Process Vs Conventional CMP

Pit Creation

Conventional Silica based CMP Sinmat CMP

No defect delineation

Cathodolumiscence Measurements- Sub

Surface Damage

Secondary Electron Mode CL Mode

Sinmat Polished Samples- No Sub-surface

damage

Secondary Electron Mode CL Mode

Sinmat Process Vs Conventional CMP-

Surface Contamination XPS Studies

Binding Energy (eV)

N(E)

Min: 0 Max: 590

118 116 114 112 110 108 106 104 102 100 98

1

2

3

Binding Energy (eV)

N(E)

Min: 0 Max: 929

118 116 114 112 110 108 106 104 102 100 98

1

2

a bGa 3pGa 3pSi 2p

Binding Energy (eV)

N(E)

Min: 0 Max: 590

118 116 114 112 110 108 106 104 102 100 98

1

2

3

Binding Energy (eV)

N(E)

Min: 0 Max: 929

118 116 114 112 110 108 106 104 102 100 98

1

2

a bGa 3pGa 3pSi 2p

Multiplex XPS spectra showing (a) Si 2p peak (peak 3) (Conventional

Silica polish and (b) no Si 2p peak after Sinmat CMP polish

No Silica contamination after Sinmat Polish

Large Area Uniform Surface Finish

1

2

3

4

5

6

7

8

9

10 11

12

13

2

1

3

4 6

7

8

5 9

10 11

12

13

1

2 4

3

5

6

7

8

9

10 11

12

Before

After Polish

13 spot inspection

19

RCMP Process Highlights

Ultra-Rapid Polishing Rates

• Rates up to 1500 nm/hr for SiC surfaces

• Polishing rates > 10- 20X higher than existing processes

• Polishing rates 100 to 1000X higher for C-face polishing

Ultra–Smooth Flawless Surfaces

• Atomic Terraced Finish

• Eliminates scratches

• Angstrom level roughness

SiC MOSFET Device Performance

8.00E+10

5.60E+11

8.40E+11

0.00E+00

5.00E+11

1.00E+12

Sinmat

Processed

Conventional As received

Wafer process type

Dit

(eV

-1cm

-2)

SiC Substrate

Ni / Pt

Dielectric (CaxMg(1-x)O)

Au/Pt (Dia 50µm)

3.723.26

2.58

0

1

2

3

4

Ele

ctr

ical

Bre

akd

ow

n

(MV

/cm

2)

Sinm

at

Conv

entiona

l

As re

ceived

Process

Electrical break down field

Lower Interface traps for MOSFETs devices

Reduced Dit and Increased Electrical Break

down field

(Courtesy: Prof. Cammy Abernathy, University of Florida)

21

Diamond Applications

Polished

Diamond

Substrates

RF MEMS

Nano

Imprinting

DNA

Sensors

Optical

Windows &

Mirrors

MEMS

Ultra-Low

Friction

Smooth surfaces combined with high

modulus results in very high frequency devices

High thermal conductivity and

smooth surface will help in fabrication of SOI devices

Smooth surface needed for achieving

nano-scale resolution in imprint lithography

Smooth surfaces allow reproducable

attachment/detachment of DNA molecules

Smooth surfaces ensure reduced

light scattering and better light transmission through windows

Smooth surfaces decrease friction

and increase lifetime of devices

Si/GaN On

Diamond

(SUD)

Diamond Applications

22

Diamond Polishing Examples

Starting PV 50 micron to 0.7 micron after

25 hrs processing

Thin sold films 212 (1992)43

23

23

Diamond and Related Materials 6(1997)1789

Sequential Laser-Assisted Polishing

Advancement in Diamond Polishing Technology

1

10

100

1,000

10,000

1992 1995 1996 2002 2002 2002 2004 2006 2009

Year

Su

rface R

ou

gh

ness (

Å) Ion Beam

(Hirata)

15-700Å

Laser Polishing

(Tokarev)

70-1,000Å

Thermo-Chemical

Polishing (Tokura)

80-100Å

EDM (Wang)

2,000-10,000Å

Mechanical

Polishing (Hird)

250-400Å

CVD-UNCD

(Krauss)

120-200Å

Dynamic

Friction (Iw ai)

300-4500Å

Chemo-Mechanical

Polishing (Wang)

100-250Å

RCMP Process

(SINMAT)

1-10Å

25

Timeline of Diamond Growth and Polishing

1950 1960 1970 1980 1990 2000 2010

1989 Large area CVD growth

of diamond company

established (Diamonex)

1968 Low pressure vapo-solid-

liquid technology for

diamond growth

(Derjayuin, Russia)

1952 First demonstration of

diamond by synthetic

methods. (Eversole,

Union Carbide)

2005 High-rate single-crystal

diamond growth ability

(Carnegie Institute,

Washington)

2009 Super-smooth 1Å

diamond finished

substrates up to

100mm commercialized

(SINMAT)

1954 High pressure, high

temperature

diamond growth

demonstration (GE)

1981 Consistent

demonstration of low

pressure CVD growth of

diamond (1 um/hr)

(Setaka NIRIM, Japan)

2002 Ultra Nano Crystalline Diamond

(UNCD) low-roughness diamond

(~100Å roughness) (Krauss,

Argonne National Lab)

2007 Sales of CVD diamond

plate products (Element

6, a De Beers company)

26

Removal Rate of Diamond

(Microcrystalline and Nanocrystalline)

100

150

250

0

50

100

150

200

250

300

UNCD NCD MCD

Re

mo

va

l ra

te

in a

.u

Diamond wafer type

27

AFM Topograph of Ultra-Nano Crystalline

Diamond (UNCD) Films Before and After CMP

As received RMS 2.5 nm Polished RMS < 1 nm

28

AFM Topograph of Nano Crystalline Diamond

Before and After CMP

As received RMS 16nm After polishing

Polishing RMS 2 nm

CMP Enabled Basal Plane Dislocation (BPD) Reduction

In SiC Homo-Epitaxy

0

5

10

15

20

25

Substrate Etched Substrate Novel CMPProcessed

BP

Ds

de

nsit

y/S

q.c

m

Substrate

Basal Plane Elimination from Conventional Vs Novel CMP Based

Substrate

(a) (b)

(c)

(a) Novel CMP enable substrate showing 1 order

reduction in BPD in the epi-layer

(b) Etched Epi layer grown on Etched Substrate

shows propagation of BPD from Substrate (B1′

oval pit)

(c) Etched Epi layer showing complete conversion

BPDs in to TEDs (Hexagonal pits)

30

Conclusions

Ultra-rapid Polishing Rates (SiC,GaN and Diamond)

• Rates up to 1500nm/hr for SiC surfaces

• Polishing rates 10X to 20X higher than existing industrial processes

Ultra–smooth Flawless Surfaces

• Atomic Terraced Finish

• Eliminates scratches

• Angstrom level roughness

Lower Defect Density Films

• Low friction

• Gentle non-scratching soft abrasives

Enhanced Device Performance

• SiC MOSFETs devices shows enhanced performance

31

RMS Roughness Measurements Using Atomic

Force Microscope (AFM) & Optical Profilometer

Samples Unpolished

(Roughness

average in nm)

After polishing

(Roughness average

in nm)

Micro-crystalline wafer 500 5

Nano-crystalline wafer 16 2-3

Ultra nano crystalline

wafer

2.5 ≤ 1

32

Optical Topograph of Micro-Crystalline

Diamond Before and After CMP

As received RMS

Before polishing

~500 nm

After Polishing

RMS ~20 nm

GaN Large Area Roughness

Surface 10 micron GaN template Bulk HVPE Grown GaN

After Sinmat Polish

Ra- 5A

RMS- 6A

Rz – 6 nm

Rt- 9 nm

Wyko Optical

Interferometer

Sinmat RCMP slurries overview (Cont’d)

Robust manufacturing

Tunability possible for LTV/ TTV control

Angstrom level surface finish (< 1.5 A) with atomic terracing on low miscut wafers. Wafers epi-ready after CMP.

No sub-surface damage

Scalable to 100-150 mm polishing

Less friction-sensitivity to edge-effects

Less slurry consumption

Excellent flowability of slurry on pad

Device Performance on Sinmat Polished GaN

Surfaces

1.56

1.9341.98

1.4

1.5

1.6

1.7

1.8

1.9

2

2.1

Sinmat processed

Conventional As received

Ideali

ty f

acto

r (n

)

Wafer Sample type

0.8260.74

0.4049

0.3

1.2

Sinmat processed

Conventional As received

Barr

ier

heig

ht

Wafer sample type

Ti/Au

GaN

Ti/Al/Pt/Au -5 -4 -3 -2 -1 0 1 2

1x10-9

1x10-7

1x10-5

1x10-3

1x10-1

1x101

1x103

200um diodes

basicacidicmore acidic

Curr

ent

(A/c

m2 )

Voltage (V)

No CMP

Formulation 2

Formulation 3

Formulation 4

-5 -4 -3 -2 -1 0 1 21x10

-9

1x10-7

1x10-5

1x10-3

1x10-1

1x101

1x103

200um diodes

basicacidicmore acidic

Curr

ent

(A/c

m2 )

Voltage (V)

No CMPConventionalUCMP

-5 -4 -3 -2 -1 0 1 21x10

-9

1x10-7

1x10-5

1x10-3

1x10-1

1x101

1x103

200um diodes

basicacidicmore acidic

Curr

ent

(A/c

m2 )

Voltage (V)-5 -4 -3 -2 -1 0 1 2

1x10-9

1x10-7

1x10-5

1x10-3

1x10-1

1x101

1x103

-5 -4 -3 -2 -1 0 1 21x10

-9

1x10-7

1x10-5

1x10-3

1x10-1

1x101

1x103

200um diodes

basicacidicmore acidic

Curr

ent

(A/c

m2 )

Voltage (V)

No CMP

Formulation 2

Formulation 3

Formulation 4

-5 -4 -3 -2 -1 0 1 21x10

-9

1x10-7

1x10-5

1x10-3

1x10-1

1x101

1x103

200um diodes

basicacidicmore acidic

Curr

ent

(A/c

m2 )

Voltage (V)-5 -4 -3 -2 -1 0 1 2

1x10-9

1x10-7

1x10-5

1x10-3

1x10-1

1x101

1x103

-5 -4 -3 -2 -1 0 1 21x10

-9

1x10-7

1x10-5

1x10-3

1x10-1

1x101

1x103

200um diodes

basicacidicmore acidic

Curr

ent

(A/c

m2 )

Voltage (V)

No CMPConventionalUCMP

Schottky

Diode

Sinmat Processed

Sinmat processed - Low Ideality Factor & Higher Barrier Height