ULTIMATE: Preliminary Test Results IPHC-LBNL Phone Conference

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ULTIMATE: Preliminary Test Results IPHC-LBNL Phone Conference. Outline Ultimate test status Analogue outputs (tested by Mathieu) Pixel array + Discriminators (tested by Mathieu) Zero suppression logic (tested by Gilles) Synchronous readout of N Ultimate (proposed by Kader & Gilles) - PowerPoint PPT Presentation

Text of ULTIMATE: Preliminary Test Results IPHC-LBNL Phone Conference

  • ULTIMATE: Preliminary Test Results IPHC-LBNL Phone Conference OutlineUltimate test statusAnalogue outputs (tested by Mathieu)Pixel array + Discriminators (tested by Mathieu)Zero suppression logic (tested by Gilles)Synchronous readout of N Ultimate (proposed by Kader & Gilles)DAQ development for BT (Gilles et al.)

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    IPHC christine.hu@ires.in2p3.fr*04/05/2011 Tel meeting LBNL/IPHCUltimate: test statusUltimate sensors have been received at IPHC March 24th 20111 wafer (No. 4) with HighRes EPI 15 m1 Diced wafer (No. 5) thinned down to 120 m with HighRes EPI 20 m

    AMS tested each wafer by using integrated PCM (test 5 sites/wafer)Process parameters are out of specification ranges in 2 sites on wafers No.4 and 5

    9 chips were bonded on PCB. All have passed the test of power on and JTAG1 for PLL test1 for regulator test7 for analogue & digital characterization

    Power on test results:IddA ~150 mA, IddD ~70 mA (low activity)730 mW (3.3 V) ~150 mW/cm

    In chip regulator for Vclamping works in 5 tested chips 4 chips have problemStill investigating

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    IPHC christine.hu@ires.in2p3.fr*04/05/2011 Tel meeting LBNL/IPHCUltimate: Analogue OutputPixel array scan at 40 MHz, T sensor ~ 20CJTAG Nominal valueVddA = 3.3 VVclamping provided by in chip regulatorGood noise uniformity, ENC ~ 14 e-Gain similar to Mimosa26 ~ 65 V/ e-

    CCE is not sensitive to temperature variation

    ChipsCalib peak(UADC)ENC (e-)CCESeed pixel2x2 pixels3x3 pixels5x5 pixelsUltimate39513.824%62%82%94%Mi22 AHR (S7) 45813.620%52%72%87%Mimosa263911223%59%77%89%

    Ultimate Sensor Calib peak(UADC)ENC (e-)CCESeed pixel2x2 pixels3x3 pixels5x5 pixels~20 C39513.824%62%82%94%~35 C38516.424%62%83%96%~45 C36920.723%63%85%99%

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    IPHC christine.hu@ires.in2p3.fr*04/05/2011 Tel meeting LBNL/IPHCUltimate: Analogue Output (2)Sensor performances remaining almost the same when VddA varies from 3.3 to 3 volt

    8 columns run at 160 MHzProblem 1: Large CDS (Vread-Vcalib) offset valueAnalogue output is distributed by READ signalProblem identifiedCoupling between the bias of the output buffer & READ in the layoutWorkaround: possible but need investigation

    Problem 2:Marker (MKA) despaired at 160 MHz (156 MHz is ok)

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    IPHC christine.hu@ires.in2p3.fr*04/05/2011 Tel meeting LBNL/IPHCUltimate: Pixel Array + DiscriminatorsTemporal noise uniformityTN ~ 0.96 mV

    FPN Without offset to 0 adjustmentWith offset to 0 adjustment, FPN ~ 0.55 mV

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    IPHC christine.hu@ires.in2p3.fr*04/05/2011 Tel meeting LBNL/IPHCUltimate: Pixel Array + Discriminators (2)ABCDNo strange behaviours observed

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    IPHC christine.hu@ires.in2p3.fr*04/05/2011 Tel meeting LBNL/IPHCUltimate: Pixel Array + Discriminators (3)ABCD1.0030.57470.94740.48960.92430.47680.89950.4707

    IPHC christine.hu@ires.in2p3.fr

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    IPHC christine.hu@ires.in2p3.fr*04/05/2011 Tel meeting LBNL/IPHCUltimate: Pixel Array + Discriminators (3)Observed pointsLarge offset in every 16 rowsStill within 4 sigmaStructure in the design, try to minimizeOffset dispersion in column & row"half moon" Not seen in Mimosa26Offset is frequency & temperature sensiblePower supply to 3 VVddA set to 3 V, Ultimate still works with similar performancesVddD set to 3 V, Ultimate losses its performances need more investigations

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    IPHC christine.hu@ires.in2p3.fr*04/05/2011 Tel meeting LBNL/IPHCUltimate: Zero suppression logicCheck (but not an exhaustive test)Conditions: VddD = 3.3V, Frequency at 150 MHz in most case (due to limitation on test board and tight planning) Test of critical patterns (defined by Guy) Done on 5000 frames Test N 1Line pattern 0 0Line pattern 1 Discri 0 & 959 = 1Test N 2Line pattern 0 Discri 0 & 959 = 1Line pattern 1 0Test N 3Line pattern 0 Discri 0, 63, 64, 127, 128 = 1Line pattern 1 0Test N 4 ( Test limited to 500 frames )Line pattern 0 Shift emulated hit on a single discri ( 0 .. 959 ) Line pattern 1 0Test N 5 ( Test limited to 500 frames )Line pattern 0 0Line pattern 1 Shift emulated hit on a single discri ( 0 .. 959 ) SUZE works without error

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    IPHC christine.hu@ires.in2p3.fr*04/05/2011 Tel meeting LBNL/IPHCSynchronous readout of N Ultimate (on a ladder)Standard protocol with Start synchro / clock not applicable Error in Ultimate ( bad clock used to sample Start 80 MHz instead of 160 MHz ) First workaround Difficult to implementSynchronize also Reset with clock ( Reset & Start )Reset is a slow control signal ( from boards to Ultimate ) NOT a fast signal Never tested Second workaround Easier to implement & Validated at lab Reset all UltimatesLoad JTAGStart clock ( gate controlled by flip/flop to get first clock cycle as full period )Send Start signal ( synchronized on clock falling edge as usual )

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    IPHC christine.hu@ires.in2p3.fr*04/05/2011 Tel meeting LBNL/IPHCStatus of DAQ for Beam Test (BT)Done Use FW developed for Mimosa26Upgrade to solve N x Ultimate synchronization problem doneTest of FW at 150 MHz done with one Ultimate To be doneCheck trigger handling FW running @ 150 MHzUpgrade of DAQ SW & Monitoring RemarkAll tests will be performed at 150 MHz because of limitation on test boards No time to investigateBT foreseen this summer

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  • ULTIMATE: Latch up free design IPHC-LBNL Phone Conference OutlineLatch-up free SRAM test setup status Latch up free digital design status

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    IPHC christine.hu@ires.in2p3.fr*04/05/2011 Tel meeting LBNL/IPHCLatch-up free SRAM design statusLatch-up free SRAM (256x8) is designed by a Ph.D student in the last year. BUT: 4 metal layers have been used

    If the evaluation of the designed module is OK Redesign with only 3 metal layers!We will extend it to the size of the memory used for Ultimate (2x2 x (2048x16))

    Planning proposed last year has to be revisited which was under estimated!

    SRAM test status:HW & SW needed to test SRAMHW ( G. Doziere + O. Clausse ) Mother board Power supply, buffers, connectorsDaughter board SRAM holder ( SIMM format ) FW & SW FW Pattern generator & DAQ with NI Flex RIO ( C. Santos )SW RAM test routines in C ( G. Doziere )

    Test planningHW stopped because Guy has an accident ( broken knee ~ 5 weeks )Boards ready for test at lab mid/end JulyFW & SWFW DoneSW To be done ( M. Specht?/G. Claus?) Ready for mi July

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    IPHC christine.hu@ires.in2p3.fr*04/05/2011 Tel meeting LBNL/IPHCLatch up free digital design statusHow? increase the spacing between Nplus and Pplus layerStretching all the AMS digital standard cells by 3 mAll the layout for AMS Standard cells have been stretch by hand or by using skill program (more than 250 cells)Abstract views have been created in a new libraryA trial has been done:Integration of these abstract in SOC Encounter flow (Digital placer and rooter)Design of SLOWCONTROL (JTAG) block with the stretched cells as a test case DRC, LVS without special problem

    Next steps: extend this procedure to all mixte and digital blocs

    Main difficulties: Limited space: Ultimate already used the maximum reticle size. All above modifications have to feet to the Ultimate size. Please pay attention that the memory will have 50% size incensement!!!Memory is a unknown bloc for us. Some questions such as how to simulate it with other digital blocs, how to test it (we have to use the same PAD ring), are not solvedSeveral iterations have to be planned due to optimisation of the size & timing (160 MHz) At least 6 month of development

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