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UNIT - I POWER DISSIPATION IN CMOS Presented By Presented By S.Kirubaveni Assistant Professor, ECE Dept

U I - Lecture 4 Basic Principle of Low Power Design

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Page 1: U I - Lecture 4 Basic Principle of Low Power Design

UNIT - IPOWER DISSIPATION

IN CMOS

Presented By Presented By

S.Kirubaveni

Assistant Professor, ECE Dept

Page 2: U I - Lecture 4 Basic Principle of Low Power Design

Presentation Outline

• Lecture 2: Physics of Power Dissipation in CMOS FET devices

• Lecture 3: Sources of Power ConsumptionConsumption

• Lecture 4: Basic Principle of Low Power Design

• Lecture 5: Hierarchy of Limits of Power

Page 3: U I - Lecture 4 Basic Principle of Low Power Design

Objectives

• To learn the basic principles of Low Power Design

–Reduce Switching Voltage

–Reduce Capacitance

–Reduce Switching Frequency –Reduce Switching Frequency

–Reduce Leakage & Static Current

• To understand the Low Power Figure of Merits.

Page 4: U I - Lecture 4 Basic Principle of Low Power Design

Basic Principles of Low Power Design

• The fundamental modes of power dissipations in CMOS VLSI circuits are given by the equations. By examining the equations, several basic principles of low power design techniques can be uncovered.

Charging & Discharging Capacitance

Subthreshold Channel Leakage

Diode Leakage Current

Short Circuit Current

Capacitance

Page 5: U I - Lecture 4 Basic Principle of Low Power Design

Reduce Switching Voltage

• The dynamic power of digital chips is generally

the largest portion of power dissipation.

• The P =CV2ƒ equation consists of three terms:

– Voltage, Capacitance and Frequency.

• Due to the quadratic effect of the voltage term,

reducing the switching voltage can achieve reducing the switching voltage can achieve

dramatic savings.

• The easiest method to achieve this is to reduce

the operating voltage of the CMOS circuit.

• Other methods seek to reduce voltage swing by

using well-known circuit techniques such as

charge sharing, transistor threshold voltage, etc.

Page 6: U I - Lecture 4 Basic Principle of Low Power Design

Reduce Switching Voltage

• There are many trade-offs to be considered in

voltage reduction.

• Performance is lost because MOS transistors

become slower at lower operating voltages.

• The main reason is that the threshold voltages of

the transistors do not scale accordingly with the the transistors do not scale accordingly with the

operating voltage to avoid excessive leakage

current.

• Noise immunity is also a concern at low voltage

swing.

• Special level converters are required to

interface low swing signals to the full-swing ones.

Page 7: U I - Lecture 4 Basic Principle of Low Power Design

Reduce Capacitance

• Reducing parasitic capacitance in digital design has always been a good way to improve performance as well as power.

• However, a blind reduction of capacitance may not achieve the desired result in power dissipation.

• The real goal is to reduce the product of • The real goal is to reduce the product of capacitance and its switching frequency.

• Signals with high switching frequency should be routed with minimum parasitic capacitance to conserve power.

• Conversely, nodes with large parasitic capacitance should not be allowed to switch at high frequency.

Page 8: U I - Lecture 4 Basic Principle of Low Power Design

Reduce Switching Frequency

• For the sake of power dissipation, the techniques for reducing switching frequency have the same effect as reducing capacitance.

• Again, frequency reduction is best applied to signals with large capacitance.

• The techniques are often applied to logic level • The techniques are often applied to logic level design and above.

• Those applied at a higher abstraction level generally have greater impact.

• Reduction of switching frequency also has the side effect of improving the reliability of a chip as some failure mechanism is related to the switching frequency.

Page 9: U I - Lecture 4 Basic Principle of Low Power Design

Reduce Switching Frequency

• One effective method of reducing switching

frequency is to eliminate logic switchingthat is not necessary for computation.

• Other methods involve alternate logicimplementation since there are many ways todesign a logic network to perform an identicaldesign a logic network to perform an identicalfunction.

• The use of different coding methods,number representation systems,counting sequences and datarepresentations can directly alter theswitching frequency of a design.

Page 10: U I - Lecture 4 Basic Principle of Low Power Design

Reduce Leakage & Static Current

• Leakage current, whether reverse biased junction

or subthreshold current, is generally not very

useful in digital design.

• However, designers often have very little control

over the leakage current of the digital circuit.

• Fortunately, the leakage power dissipation of a

CMOS digital circuit is several orders of

magnitude smaller than the dynamic power.

• The leakage power problem mainly appears in

very low frequency circuits or ones with "sleep

modes" where dynamic activities are

suppressed.

Page 11: U I - Lecture 4 Basic Principle of Low Power Design

Reduce Leakage & Static Current • Most leakage reduction techniques are applied at low-level design abstraction such as process, device and circuit design.

• Memory chips that have very high device density are most susceptible to high leakage power.

• Static current can be reduced by transistor • Static current can be reduced by transistor sizing, layout techniques and careful circuit design.

• Circuit modules that consume static current should be turned off if not used.

• Sometimes, static current depends on the logic state of its output and we can consider reversing the signal polarity to minimize the probability of static current flow.

Page 12: U I - Lecture 4 Basic Principle of Low Power Design

Low Power Figure of Merits

• Power Consumption in Watts

–Watt is the absolute measure of power consumed by a chip or a system

– Used in total power specification

– Useful for packaging considerations, system power supply & cooling requirements power supply & cooling requirements

• Peak Power

– The maximum power consumption of a chip at any time

– Useful for power ground wiring design, signal noise margin & reliability analysis.

Page 13: U I - Lecture 4 Basic Principle of Low Power Design

Low Power Figure of Merits

• Power Efficiency of a Chip

– A chip operates at a higher frequency can perform faster computation and hence consume more power.

– Watt is no longer useful.

– Power is the rate at which energy is – Power is the rate at which energy is consumed over time.

– Energy in Joules becomes important

– µW/MHz in numbers

– A low energy number is desirable because it requires less power to perform computation at the same frequency.

Page 14: U I - Lecture 4 Basic Principle of Low Power Design

Low Power Figure of Merits

• Power Efficiency of a Chip

– Different processors require different number of clock cycles for the same operation so µW/MHz in numbers is not suitable.

– µW/MIPS or µA/MIPS with unit Watt-Second per Instruction is introduced. Second per Instruction is introduced.

– MIPS is a measure of the performance level of a processor.

– This FOM is only useful when comparing power efficiency of two processors with similar instruction sets.

Page 15: U I - Lecture 4 Basic Principle of Low Power Design

Low Power Figure of Merits

• Power Efficiency of a Chip •When comparing two processor chips with different instruction sets or architecture µW/MIPS or µA/MIPS is still not suitable

• Example: CISC Vs RISC Vs VLIW Processors

–µW/SPEC is introduced

• SPEC is a measure of computation speed derived from executing some standard benchmarks software programs written in machine independent high level programming language

Page 16: U I - Lecture 4 Basic Principle of Low Power Design

Low Power Figure of Merits

• Power Efficiency of a Chip

–µW/MIPS and µW/SPEC

•Measure energy consumption of a typical instruction or operation regardless of the processor’s performance rating. processor’s performance rating.

• Encompass the merits of chip fabrication technology as well as architecture and circuit design techniques.

–Other Measures

• Energy Delay Product

–Used to assess the merits of a logic style.

Page 17: U I - Lecture 4 Basic Principle of Low Power Design

Conclusion

• The following basic principles of Low Power Design are discussed

–Reduce Switching Voltage

–Reduce Capacitance

–Reduce Switching Frequency –Reduce Switching Frequency

–Reduce Leakage & Static Current

• The Low Power Figure of Merits are introduced.